blob: 3c4e0614964bf641c57f5b2b7777ae19bca45b6e [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +08001/*
2 * Copyright (c) 2008, Google Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in
12 * the documentation and/or other materials provided with the
13 * distribution.
14 * * Neither the name of Google, Inc. nor the names of its contributors
15 * may be used to endorse or promote products derived from this
16 * software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
21 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
22 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
25 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
28 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include <arch/arm.h>
33#include <reg.h>
34#include <kernel/thread.h>
35#include <platform/interrupts.h>
36#include <platform/spm.h>
37#include <platform/mt_reg_base.h>
38#include <platform/mt_irq.h>
39#include <debug.h>
40
41/* set for mt_gic */
42void mt_irq_set_polarity(unsigned int irq, unsigned int polarity)
43{
44 unsigned int offset;
45 unsigned int reg_index;
46 unsigned int value;
47
48 /* peripheral device's IRQ line is using GIC's SPI, and line ID >= GIC_PRIVATE_SIGNALS */
49 if (irq < GIC_PRIVATE_SIGNALS) {
50 dprintf(SPEW, "The Interrupt ID < 32, please check!\n");
51 return;
52 }
53
54 offset = (irq - GIC_PRIVATE_SIGNALS) & 0x1F;
55 reg_index = (irq - GIC_PRIVATE_SIGNALS) >> 5;
56 if (polarity == 0) {
57 value = readl(INT_POL_CTL0 + (reg_index * 4));
58 value |= (1 << offset); /* always invert the incoming IRQ's polarity */
59 write_r((INT_POL_CTL0 + (reg_index * 4)), value);
60 } else {
61 value = readl(INT_POL_CTL0 + (reg_index * 4));
62 value &= ~(0x1 << offset);
63 write_r(INT_POL_CTL0 + (reg_index * 4), value);
64 }
65}
66
67/* set for arm gic */
68void mt_irq_set_sens(unsigned int irq, unsigned int sens)
69{
70 unsigned int config;
71
72 if (sens == EDGE_SENSITIVE) {
73 config = readl(GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4);
74 config |= (0x2 << (irq % 16) * 2);
75 write_r(GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4, config);
76 } else {
77 config = readl(GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4);
78 config &= ~(0x2 << (irq % 16) * 2);
79 write_r( GIC_DIST_BASE + GIC_DIST_CONFIG + (irq / 16) * 4, config);
80 }
81 DSB;
82}