blob: 5e9917c9425b512c0a93c203489c9e51bcffb4ee [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +08001/*
2 * Copyright (c) 2016 MediaTek Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files
6 * (the "Software"), to deal in the Software without restriction,
7 * including without limitation the rights to use, copy, modify, merge,
8 * publish, distribute, sublicense, and/or sell copies of the Software,
9 * and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22*/
23
24#include <arch.h>
25#include <dev/interrupt/arm_gic.h>
26#include <dev/uart.h>
27#include <dev/timer/arm_generic.h>
28#include <err.h>
29#include <kernel/vm.h>
30#include <kernel/spinlock.h>
31#include <lib/mempool.h>
32#include <platform.h>
33#include <platform/emi.h>
34#include <platform/memory.h>
35#include <platform/gic.h>
36#include <platform/memory.h>
37#include <platform/mtk_timer.h>
38#include <platform/mtk_wdt.h>
39#include <platform/pll.h>
40
41#if RAMBASE
42#define RSV_PAGE RAMBASE
43#else
44#define RSV_PAGE 0
45#endif
46
47#define L2C_MAPPING_IDX 0
48#define SRAM_MAPPING_IDX 1
49#define PERIPHERAL_MAPPING_IDX 2
50#define DRAM_MAPPING_IDX 3
51
52/* initial memory mappings. parsed by start.S */
53struct mmu_initial_mapping mmu_initial_mappings[] = {
54 {
55 .phys = SRAM_BASE_PHYS,
56 .virt = SRAM_BASE_VIRT,
57 .size = SRAM_BASE_SIZE,
58 .flags = 0,
59 .name = "sram"
60 },
61 {
62 .phys = MEMORY_BASE_PHYS,
63 .virt = KERNEL_BASE,
64 .size = MEMORY_APERTURE_SIZE,
65 .flags = 0,
66 .name = "memory"
67 },
68 {
69 .phys = PERIPHERAL_BASE_PHYS,
70 .virt = PERIPHERAL_BASE_VIRT,
71 .size = PERIPHERAL_BASE_SIZE,
72 .flags = MMU_INITIAL_MAPPING_FLAG_DEVICE,
73 .name = "peripherals"
74 },
75 /* reserved for dram */
76 { 0 },
77
78 /* null entry to terminate the list */
79 { 0 }
80};
81
82static pmm_arena_t arena = {
83 .name = "sdram",
84 .base = SRAM_BASE_PHYS,
85 .size = (SRAM_BASE_SIZE - RSV_PAGE),
86 .flags = PMM_ARENA_FLAG_KMAP,
87};
88
89static void arch_enable_mmu(void)
90{
91 arm_write_sctlr(arm_read_sctlr() | (1<<0)); // mmu enable
92}
93
94static void smp_mode_enable(void)
95{
96 uint32_t actlr = arm_read_actlr();
97
98 actlr |= (1<<6);
99 arm_write_actlr(actlr);
100}
101
102void platform_early_init(void)
103{
104 uart_init_early();
105#ifdef WITH_KERNEL_VM
106 pmm_add_arena(&arena);
107#endif
108 /* initialize the interrupt controller */
109 arm_gic_init();
110 /* init GPT6 */
111 mtk_timer_init();
112 /* initialize the timer block */
113 arm_generic_timer_init(ARM_GENERIC_TIMER_PHYSICAL_INT, 13000000);
114
115 arch_disable_cache(DCACHE);
116 arch_disable_mmu();
117 /* init pll */
118 mt_pll_init();
119
120 /* init AP watchdog and set timeout to 10 secs */
121 mtk_wdt_init();
122
123 /* init memory */
124 mt_mem_init();
125
126#if WITH_KERNEL_VM
127 /* add DRAM to mmu_initial_mappings for physical-to-virtual translation */
128 mmu_initial_mappings[DRAM_MAPPING_IDX].phys = DRAM_BASE_PHY;
129 mmu_initial_mappings[DRAM_MAPPING_IDX].virt = DRAM_BASE_PHY;
130 mmu_initial_mappings[DRAM_MAPPING_IDX].size = memory_size();
131 mmu_initial_mappings[DRAM_MAPPING_IDX].flags = 0;
132 mmu_initial_mappings[DRAM_MAPPING_IDX].name = "dram";
133#endif
134
135 arch_enable_mmu();
136 arch_enable_cache(DCACHE);
137 smp_mode_enable();
138}
139
140void platform_init(void)
141{
142 int ret;
143 unsigned int dram_size = 0;
144
145 /* map for app */
146 dram_size = memory_size();
147 arch_mmu_map(DRAM_PHY_ADDR, DRAM_PHY_ADDR, dram_size / PAGE_SIZE, 0);
148
149 ret = mempool_init((void *)CACHED_MEMPOOL_ADDR, CACHED_MEMPOOL_SIZE,
150 MEMPOOL_CACHE);
151 if (ret != NO_ERROR)
152 platform_halt(HALT_ACTION_REBOOT, HALT_REASON_SW_PANIC);
153}