rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2009 Corey Tabaka |
| 3 | * Copyright (c) 2015 Intel Corporation |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining |
| 6 | * a copy of this software and associated documentation files |
| 7 | * (the "Software"), to deal in the Software without restriction, |
| 8 | * including without limitation the rights to use, copy, modify, merge, |
| 9 | * publish, distribute, sublicense, and/or sell copies of the Software, |
| 10 | * and to permit persons to whom the Software is furnished to do so, |
| 11 | * subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be |
| 14 | * included in all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 17 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 19 | * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
| 20 | * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 21 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 22 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 23 | */ |
| 24 | #include <sys/types.h> |
| 25 | #include <debug.h> |
| 26 | #include <trace.h> |
| 27 | #include <err.h> |
| 28 | #include <reg.h> |
| 29 | #include <kernel/thread.h> |
| 30 | #include <platform/interrupts.h> |
| 31 | #include <arch/ops.h> |
| 32 | #include <arch/mips.h> |
| 33 | #include <platform/qemu-mips.h> |
| 34 | |
| 35 | #define LOCAL_TRACE 0 |
| 36 | |
| 37 | static spin_lock_t lock; |
| 38 | |
| 39 | #define PIC1 0x20 |
| 40 | #define PIC2 0xA0 |
| 41 | |
| 42 | #define ICW1 0x11 |
| 43 | #define ICW4 0x01 |
| 44 | |
| 45 | #define PIC1_CMD 0x20 |
| 46 | #define PIC1_DATA 0x21 |
| 47 | #define PIC2_CMD 0xA0 |
| 48 | #define PIC2_DATA 0xA1 |
| 49 | #define PIC_READ_IRR 0x0a /* OCW3 irq ready next CMD read */ |
| 50 | #define PIC_READ_ISR 0x0b /* OCW3 irq service next CMD read */ |
| 51 | |
| 52 | #define ICW1_ICW4 0x01 /* ICW4 (not) needed */ |
| 53 | #define ICW1_SINGLE 0x02 /* Single (cascade) mode */ |
| 54 | #define ICW1_INTERVAL4 0x04 /* Call address interval 4 (8) */ |
| 55 | #define ICW1_LEVEL 0x08 /* Level triggered (edge) mode */ |
| 56 | #define ICW1_INIT 0x10 /* Initialization */ |
| 57 | |
| 58 | #define ICW4_8086 0x01 /* 8086/88 (MCS-80/85) mode */ |
| 59 | #define ICW4_AUTO 0x02 /* Auto (normal) EOI */ |
| 60 | #define ICW4_BUF_SLAVE 0x08 /* Buffered mode/slave */ |
| 61 | #define ICW4_BUF_MASTER 0x0C /* Buffered mode/master */ |
| 62 | #define ICW4_SFNM 0x10 /* Special fully nested (not) */ |
| 63 | |
| 64 | struct int_handler_struct { |
| 65 | int_handler handler; |
| 66 | void *arg; |
| 67 | }; |
| 68 | |
| 69 | #define INT_PIC2 2 |
| 70 | |
| 71 | static struct int_handler_struct int_handler_table[INT_VECTORS]; |
| 72 | |
| 73 | /* |
| 74 | * Cached IRQ mask (enabled/disabled) |
| 75 | */ |
| 76 | static uint8_t irqMask[2]; |
| 77 | |
| 78 | /* |
| 79 | * init the PICs and remap them |
| 80 | */ |
| 81 | static void map(uint32_t pic1, uint32_t pic2) |
| 82 | { |
| 83 | /* send ICW1 */ |
| 84 | isa_write_8(PIC1, ICW1); |
| 85 | isa_write_8(PIC2, ICW1); |
| 86 | |
| 87 | /* send ICW2 */ |
| 88 | isa_write_8(PIC1 + 1, pic1); /* remap */ |
| 89 | isa_write_8(PIC2 + 1, pic2); /* pics */ |
| 90 | |
| 91 | /* send ICW3 */ |
| 92 | isa_write_8(PIC1 + 1, 4); /* IRQ2 -> connection to slave */ |
| 93 | isa_write_8(PIC2 + 1, 2); |
| 94 | |
| 95 | /* send ICW4 */ |
| 96 | isa_write_8(PIC1 + 1, 2|5); |
| 97 | isa_write_8(PIC2 + 1, 2|1); |
| 98 | |
| 99 | /* disable all IRQs */ |
| 100 | isa_write_8(PIC1 + 1, 0xff); |
| 101 | isa_write_8(PIC2 + 1, 0xff); |
| 102 | |
| 103 | irqMask[0] = 0xff; |
| 104 | irqMask[1] = 0xff; |
| 105 | } |
| 106 | |
| 107 | static void enable(unsigned int vector, bool enable) |
| 108 | { |
| 109 | if (vector < 8) { |
| 110 | uint8_t bit = 1 << vector; |
| 111 | |
| 112 | if (enable && (irqMask[0] & bit)) { |
| 113 | irqMask[0] = isa_read_8(PIC1 + 1); |
| 114 | irqMask[0] &= ~bit; |
| 115 | isa_write_8(PIC1 + 1, irqMask[0]); |
| 116 | irqMask[0] = isa_read_8(PIC1 + 1); |
| 117 | } else if (!enable && !(irqMask[0] & bit)) { |
| 118 | irqMask[0] = isa_read_8(PIC1 + 1); |
| 119 | irqMask[0] |= bit; |
| 120 | isa_write_8(PIC1 + 1, irqMask[0]); |
| 121 | irqMask[0] = isa_read_8(PIC1 + 1); |
| 122 | } |
| 123 | } else if (vector < 16) { |
| 124 | vector -= 8; |
| 125 | |
| 126 | uint8_t bit = 1 << vector; |
| 127 | |
| 128 | if (enable && (irqMask[1] & bit)) { |
| 129 | irqMask[1] = isa_read_8(PIC2 + 1); |
| 130 | irqMask[1] &= ~bit; |
| 131 | isa_write_8(PIC2 + 1, irqMask[1]); |
| 132 | irqMask[1] = isa_read_8(PIC2 + 1); |
| 133 | } else if (!enable && !(irqMask[1] & bit)) { |
| 134 | irqMask[1] = isa_read_8(PIC2 + 1); |
| 135 | irqMask[1] |= bit; |
| 136 | isa_write_8(PIC2 + 1, irqMask[1]); |
| 137 | irqMask[1] = isa_read_8(PIC2 + 1); |
| 138 | } |
| 139 | |
| 140 | bit = 1 << INT_PIC2; |
| 141 | |
| 142 | if (irqMask[1] != 0xff && (irqMask[0] & bit)) { |
| 143 | irqMask[0] = isa_read_8(PIC1 + 1); |
| 144 | irqMask[0] &= ~bit; |
| 145 | isa_write_8(PIC1 + 1, irqMask[0]); |
| 146 | irqMask[0] = isa_read_8(PIC1 + 1); |
| 147 | } else if (irqMask[1] == 0 && !(irqMask[0] & bit)) { |
| 148 | irqMask[0] = isa_read_8(PIC1 + 1); |
| 149 | irqMask[0] |= bit; |
| 150 | isa_write_8(PIC1 + 1, irqMask[0]); |
| 151 | irqMask[0] = isa_read_8(PIC1 + 1); |
| 152 | } |
| 153 | } |
| 154 | } |
| 155 | |
| 156 | static void issueEOI(unsigned int vector) |
| 157 | { |
| 158 | if (vector < 8) { |
| 159 | isa_write_8(PIC1, 0x20); |
| 160 | } else if (vector < 16) { |
| 161 | isa_write_8(PIC2, 0x20); |
| 162 | isa_write_8(PIC1, 0x20); // must issue both for the second PIC |
| 163 | } |
| 164 | } |
| 165 | |
| 166 | /* Helper func */ |
| 167 | static uint16_t __pic_get_irq_reg(uint ocw3) |
| 168 | { |
| 169 | /* OCW3 to PIC CMD to get the register values. PIC2 is chained, and |
| 170 | * represents IRQs 8-15. PIC1 is IRQs 0-7, with 2 being the chain */ |
| 171 | isa_write_8(PIC1_CMD, ocw3); |
| 172 | isa_write_8(PIC2_CMD, ocw3); |
| 173 | return (isa_read_8(PIC2_CMD) << 8) | isa_read_8(PIC1_CMD); |
| 174 | } |
| 175 | |
| 176 | /* Returns the combined value of the cascaded PICs irq request register */ |
| 177 | static uint16_t pic_get_irr(void) |
| 178 | { |
| 179 | return __pic_get_irq_reg(PIC_READ_IRR); |
| 180 | } |
| 181 | |
| 182 | /* Returns the combined value of the cascaded PICs in-service register */ |
| 183 | static uint16_t pic_get_isr(void) |
| 184 | { |
| 185 | return __pic_get_irq_reg(PIC_READ_ISR); |
| 186 | } |
| 187 | |
| 188 | void platform_init_interrupts(void) |
| 189 | { |
| 190 | // rebase the PIC out of the way of processor exceptions |
| 191 | map(0, 8); |
| 192 | } |
| 193 | |
| 194 | status_t mask_interrupt(unsigned int vector) |
| 195 | { |
| 196 | if (vector >= INT_VECTORS) |
| 197 | return ERR_INVALID_ARGS; |
| 198 | |
| 199 | LTRACEF("vector %d\n", vector); |
| 200 | |
| 201 | spin_lock_saved_state_t state; |
| 202 | spin_lock_irqsave(&lock, state); |
| 203 | |
| 204 | enable(vector, false); |
| 205 | |
| 206 | spin_unlock_irqrestore(&lock, state); |
| 207 | |
| 208 | return NO_ERROR; |
| 209 | } |
| 210 | |
| 211 | void platform_mask_irqs(void) |
| 212 | { |
| 213 | irqMask[0] = isa_read_8(PIC1 + 1); |
| 214 | irqMask[1] = isa_read_8(PIC2 + 1); |
| 215 | |
| 216 | isa_write_8(PIC1 + 1, 0xff); |
| 217 | isa_write_8(PIC2 + 1, 0xff); |
| 218 | |
| 219 | irqMask[0] = isa_read_8(PIC1 + 1); |
| 220 | irqMask[1] = isa_read_8(PIC2 + 1); |
| 221 | } |
| 222 | |
| 223 | status_t unmask_interrupt(unsigned int vector) |
| 224 | { |
| 225 | if (vector >= INT_VECTORS) |
| 226 | return ERR_INVALID_ARGS; |
| 227 | |
| 228 | LTRACEF("vector %d\n", vector); |
| 229 | |
| 230 | spin_lock_saved_state_t state; |
| 231 | spin_lock_irqsave(&lock, state); |
| 232 | |
| 233 | enable(vector, true); |
| 234 | |
| 235 | spin_unlock_irqrestore(&lock, state); |
| 236 | |
| 237 | return NO_ERROR; |
| 238 | } |
| 239 | |
| 240 | enum handler_return platform_irq(struct mips_iframe *iframe, uint vector) |
| 241 | { |
| 242 | // figure out which irq is pending |
| 243 | // issue OCW3 poll commands to PIC1 and (potentially) PIC2 |
| 244 | isa_write_8(PIC1_CMD, (1<<3) | (1<<2)); |
| 245 | uint8_t val = isa_read_8(PIC1_CMD); |
| 246 | if ((val & 0x80) == 0) { |
| 247 | // spurious? |
| 248 | return INT_NO_RESCHEDULE; |
| 249 | } |
| 250 | val &= ~0x80; |
| 251 | if (val == INT_PIC2) { |
| 252 | isa_write_8(PIC2_CMD, (1<<3) | (1<<2)); |
| 253 | val = isa_read_8(PIC2_CMD); |
| 254 | if ((val & 0x80) == 0) { |
| 255 | // spurious? |
| 256 | return INT_NO_RESCHEDULE; |
| 257 | } |
| 258 | val &= ~0x80; |
| 259 | } |
| 260 | vector = val; |
| 261 | LTRACEF("poll vector 0x%x\n", vector); |
| 262 | |
| 263 | THREAD_STATS_INC(interrupts); |
| 264 | |
| 265 | // deliver the interrupt |
| 266 | enum handler_return ret = INT_NO_RESCHEDULE; |
| 267 | |
| 268 | if (int_handler_table[vector].handler) |
| 269 | ret = int_handler_table[vector].handler(int_handler_table[vector].arg); |
| 270 | |
| 271 | return ret; |
| 272 | } |
| 273 | |
| 274 | void register_int_handler(unsigned int vector, int_handler handler, void *arg) |
| 275 | { |
| 276 | if (vector >= INT_VECTORS) |
| 277 | panic("register_int_handler: vector out of range %d\n", vector); |
| 278 | |
| 279 | spin_lock_saved_state_t state; |
| 280 | spin_lock_irqsave(&lock, state); |
| 281 | |
| 282 | int_handler_table[vector].arg = arg; |
| 283 | int_handler_table[vector].handler = handler; |
| 284 | |
| 285 | spin_unlock_irqrestore(&lock, state); |
| 286 | } |
| 287 | |