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192.168.1.100 / T103 / 1f884588077ad3476b9c91cbb0ee9ee0332bbb68 / . / src / bsp / lk / platform / stm32f1xx / CMSIS / stm32f10x.h
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rjw1f884582022-01-06 17:20:42 +0800[diff] [blame^]1/**
2 ******************************************************************************
3 * @file stm32f10x.h
4 * @author MCD Application Team
5 * @version V3.4.0
6 * @date 10/15/2010
7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
8 * This file contains all the peripheral register's definitions, bits
9 * definitions and memory mapping for STM32F10x Connectivity line,
10 * High density, High density value line, Medium density,
11 * Medium density Value line, Low density, Low density Value line
12 * and XL-density devices.
13 ******************************************************************************
14 *
15 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
16 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
17 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
18 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
19 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
20 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
21 *
22 * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
23 ******************************************************************************
24 */
25
26/** @addtogroup CMSIS
27 * @{
28 */
29
30/** @addtogroup stm32f10x
31 * @{
32 */
33
34#ifndef __STM32F10x_H
35#define __STM32F10x_H
36
37#ifdef __cplusplus
38 extern "C" {
39#endif
40
41/** @addtogroup Library_configuration_section
42 * @{
43 */
44
45/* Uncomment the line below according to the target STM32 device used in your
46 application
47 */
48
49#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
50 /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */
51 /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */
52 /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */
53 /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */
54 /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */
55 /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */
56 /* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */
57 /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */
58#endif
59/* Tip: To avoid modifying this file each time you need to switch between these
60 devices, you can define the device in your toolchain compiler preprocessor.
61
62 - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
63 where the Flash memory density ranges between 16 and 32 Kbytes.
64 - Low-density value line devices are STM32F100xx microcontrollers where the Flash
65 memory density ranges between 16 and 32 Kbytes.
66 - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
67 where the Flash memory density ranges between 64 and 128 Kbytes.
68 - Medium-density value line devices are STM32F100xx microcontrollers where the
69 Flash memory density ranges between 64 and 128 Kbytes.
70 - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
71 the Flash memory density ranges between 256 and 512 Kbytes.
72 - High-density value line devices are STM32F100xx microcontrollers where the
73 Flash memory density ranges between 256 and 512 Kbytes.
74 - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
75 the Flash memory density ranges between 512 and 1024 Kbytes.
76 - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
77 */
78
79#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
80 #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)"
81#endif
82
83#if !defined USE_STDPERIPH_DRIVER
84/**
85 * @brief Comment the line below if you will not use the peripherals drivers.
86 In this case, these drivers will not be included and the application code will
87 be based on direct access to peripherals registers
88 */
89 /*#define USE_STDPERIPH_DRIVER*/
90#endif
91
92/**
93 * @brief In the following line adjust the value of External High Speed oscillator (HSE)
94 used in your application
95
96 Tip: To avoid modifying this file each time you need to use different HSE, you
97 can define the HSE value in your toolchain compiler preprocessor.
98 */
99#if !defined HSE_VALUE
100 #ifdef STM32F10X_CL
101 #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
102 #else
103 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
104 #endif /* STM32F10X_CL */
105#endif /* HSE_VALUE */
106
107
108/**
109 * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
110 Timeout value
111 */
112#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
113
114#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
115
116/**
117 * @brief STM32F10x Standard Peripheral Library version number
118 */
119#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */
120#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x04) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */
121#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */
122#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\
123 | (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\
124 | __STM32F10X_STDPERIPH_VERSION_SUB2)
125
126/**
127 * @}
128 */
129
130/** @addtogroup Configuration_section_for_CMSIS
131 * @{
132 */
133
134/**
135 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
136 */
137#ifdef STM32F10X_XL
138 #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */
139#else
140 #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
141#endif /* STM32F10X_XL */
142#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
143#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
144
145/**
146 * @brief STM32F10x Interrupt Number Definition, according to the selected device
147 * in @ref Library_configuration_section
148 */
149typedef enum IRQn
150{
151/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
152 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
153 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
154 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
155 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
156 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
157 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
158 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
159 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
160
161/****** STM32 specific Interrupt Numbers *********************************************************/
162 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
163 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
164 TAMPER_IRQn = 2, /*!< Tamper Interrupt */
165 RTC_IRQn = 3, /*!< RTC global Interrupt */
166 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
167 RCC_IRQn = 5, /*!< RCC global Interrupt */
168 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
169 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
170 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
171 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
172 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
173 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
174 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
175 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
176 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
177 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
178 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
179 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
180
181#ifdef STM32F10X_LD
182 ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
183 USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
184 USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
185 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
186 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
187 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
188 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
189 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
190 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
191 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
192 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
193 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
194 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
195 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
196 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
197 USART1_IRQn = 37, /*!< USART1 global Interrupt */
198 USART2_IRQn = 38, /*!< USART2 global Interrupt */
199 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
200 RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
201 USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
202#endif /* STM32F10X_LD */
203
204#ifdef STM32F10X_LD_VL
205 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
206 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
207 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
208 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
209 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
210 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
211 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
212 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
213 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
214 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
215 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
216 USART1_IRQn = 37, /*!< USART1 global Interrupt */
217 USART2_IRQn = 38, /*!< USART2 global Interrupt */
218 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
219 RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
220 CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
221 TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
222 TIM7_IRQn = 55, /*!< TIM7 Interrupt */
223#endif /* STM32F10X_LD_VL */
224
225#ifdef STM32F10X_MD
226 ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
227 USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
228 USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
229 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
230 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
231 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
232 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
233 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
234 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
235 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
236 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
237 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
238 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
239 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
240 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
241 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
242 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
243 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
244 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
245 USART1_IRQn = 37, /*!< USART1 global Interrupt */
246 USART2_IRQn = 38, /*!< USART2 global Interrupt */
247 USART3_IRQn = 39, /*!< USART3 global Interrupt */
248 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
249 RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
250 USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
251#endif /* STM32F10X_MD */
252
253#ifdef STM32F10X_MD_VL
254 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
255 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
256 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
257 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
258 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
259 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
260 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
261 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
262 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
263 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
264 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
265 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
266 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
267 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
268 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
269 USART1_IRQn = 37, /*!< USART1 global Interrupt */
270 USART2_IRQn = 38, /*!< USART2 global Interrupt */
271 USART3_IRQn = 39, /*!< USART3 global Interrupt */
272 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
273 RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
274 CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
275 TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
276 TIM7_IRQn = 55, /*!< TIM7 Interrupt */
277#endif /* STM32F10X_MD_VL */
278
279#ifdef STM32F10X_HD
280 ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
281 USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
282 USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
283 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
284 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
285 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
286 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
287 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
288 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
289 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
290 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
291 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
292 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
293 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
294 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
295 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
296 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
297 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
298 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
299 USART1_IRQn = 37, /*!< USART1 global Interrupt */
300 USART2_IRQn = 38, /*!< USART2 global Interrupt */
301 USART3_IRQn = 39, /*!< USART3 global Interrupt */
302 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
303 RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
304 USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
305 TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
306 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
307 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
308 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
309 ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
310 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
311 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
312 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
313 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
314 UART4_IRQn = 52, /*!< UART4 global Interrupt */
315 UART5_IRQn = 53, /*!< UART5 global Interrupt */
316 TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
317 TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
318 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
319 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
320 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
321 DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
322#endif /* STM32F10X_HD */
323
324#ifdef STM32F10X_HD_VL
325 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
326 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
327 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
328 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
329 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
330 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
331 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
332 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
333 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
334 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
335 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
336 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
337 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
338 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
339 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
340 USART1_IRQn = 37, /*!< USART1 global Interrupt */
341 USART2_IRQn = 38, /*!< USART2 global Interrupt */
342 USART3_IRQn = 39, /*!< USART3 global Interrupt */
343 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
344 RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
345 CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
346 TIM12_IRQn = 43, /*!< TIM12 global Interrupt */
347 TIM13_IRQn = 44, /*!< TIM13 global Interrupt */
348 TIM14_IRQn = 45, /*!< TIM14 global Interrupt */
349 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
350 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
351 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
352 UART4_IRQn = 52, /*!< UART4 global Interrupt */
353 UART5_IRQn = 53, /*!< UART5 global Interrupt */
354 TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
355 TIM7_IRQn = 55, /*!< TIM7 Interrupt */
356 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
357 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
358 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
359 DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
360 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is
361 mapped at postion 60 only if the MISC_REMAP bit in
362 the AFIO_MAPR2 register is set) */
363#endif /* STM32F10X_HD_VL */
364
365#ifdef STM32F10X_XL
366 ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
367 USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
368 USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
369 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
370 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
371 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
372 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */
373 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */
374 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
375 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
376 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
377 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
378 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
379 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
380 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
381 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
382 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
383 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
384 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
385 USART1_IRQn = 37, /*!< USART1 global Interrupt */
386 USART2_IRQn = 38, /*!< USART2 global Interrupt */
387 USART3_IRQn = 39, /*!< USART3 global Interrupt */
388 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
389 RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
390 USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
391 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */
392 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */
393 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
394 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
395 ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
396 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
397 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
398 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
399 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
400 UART4_IRQn = 52, /*!< UART4 global Interrupt */
401 UART5_IRQn = 53, /*!< UART5 global Interrupt */
402 TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
403 TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
404 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
405 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
406 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
407 DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
408#endif /* STM32F10X_XL */
409
410#ifdef STM32F10X_CL
411 ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
412 CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
413 CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
414 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
415 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
416 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
417 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
418 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
419 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
420 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
421 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
422 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
423 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
424 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
425 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
426 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
427 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
428 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
429 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
430 USART1_IRQn = 37, /*!< USART1 global Interrupt */
431 USART2_IRQn = 38, /*!< USART2 global Interrupt */
432 USART3_IRQn = 39, /*!< USART3 global Interrupt */
433 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
434 RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
435 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */
436 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
437 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
438 UART4_IRQn = 52, /*!< UART4 global Interrupt */
439 UART5_IRQn = 53, /*!< UART5 global Interrupt */
440 TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
441 TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
442 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
443 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
444 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
445 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
446 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
447 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
448 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
449 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
450 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
451 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
452 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
453 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
454#endif /* STM32F10X_CL */
455 NUM_IRQn,
456} IRQn_Type;
457
458/**
459 * @}
460 */
461
462#include "core_cm3.h"
463#include "system_stm32f10x.h"
464#include <stdint.h>
465
466 /* TKG - added to make code shut up */
467#define assert_param(x)
468
469/** @addtogroup Exported_types
470 * @{
471 */
472
473/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
474typedef int32_t s32;
475typedef int16_t s16;
476typedef int8_t s8;
477
478typedef const int32_t sc32; /*!< Read Only */
479typedef const int16_t sc16; /*!< Read Only */
480typedef const int8_t sc8; /*!< Read Only */
481
482typedef __IO int32_t vs32;
483typedef __IO int16_t vs16;
484typedef __IO int8_t vs8;
485
486typedef __I int32_t vsc32; /*!< Read Only */
487typedef __I int16_t vsc16; /*!< Read Only */
488typedef __I int8_t vsc8; /*!< Read Only */
489
490typedef uint32_t u32;
491typedef uint16_t u16;
492typedef uint8_t u8;
493
494typedef const uint32_t uc32; /*!< Read Only */
495typedef const uint16_t uc16; /*!< Read Only */
496typedef const uint8_t uc8; /*!< Read Only */
497
498typedef __IO uint32_t vu32;
499typedef __IO uint16_t vu16;
500typedef __IO uint8_t vu8;
501
502typedef __I uint32_t vuc32; /*!< Read Only */
503typedef __I uint16_t vuc16; /*!< Read Only */
504typedef __I uint8_t vuc8; /*!< Read Only */
505
506typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
507
508typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
509#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
510
511typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
512
513/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */
514#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT
515#define HSE_Value HSE_VALUE
516#define HSI_Value HSI_VALUE
517/**
518 * @}
519 */
520
521/** @addtogroup Peripheral_registers_structures
522 * @{
523 */
524
525/**
526 * @brief Analog to Digital Converter
527 */
528
529typedef struct
530{
531 __IO uint32_t SR;
532 __IO uint32_t CR1;
533 __IO uint32_t CR2;
534 __IO uint32_t SMPR1;
535 __IO uint32_t SMPR2;
536 __IO uint32_t JOFR1;
537 __IO uint32_t JOFR2;
538 __IO uint32_t JOFR3;
539 __IO uint32_t JOFR4;
540 __IO uint32_t HTR;
541 __IO uint32_t LTR;
542 __IO uint32_t SQR1;
543 __IO uint32_t SQR2;
544 __IO uint32_t SQR3;
545 __IO uint32_t JSQR;
546 __IO uint32_t JDR1;
547 __IO uint32_t JDR2;
548 __IO uint32_t JDR3;
549 __IO uint32_t JDR4;
550 __IO uint32_t DR;
551} ADC_TypeDef;
552
553/**
554 * @brief Backup Registers
555 */
556
557typedef struct
558{
559 uint32_t RESERVED0;
560 __IO uint16_t DR1;
561 uint16_t RESERVED1;
562 __IO uint16_t DR2;
563 uint16_t RESERVED2;
564 __IO uint16_t DR3;
565 uint16_t RESERVED3;
566 __IO uint16_t DR4;
567 uint16_t RESERVED4;
568 __IO uint16_t DR5;
569 uint16_t RESERVED5;
570 __IO uint16_t DR6;
571 uint16_t RESERVED6;
572 __IO uint16_t DR7;
573 uint16_t RESERVED7;
574 __IO uint16_t DR8;
575 uint16_t RESERVED8;
576 __IO uint16_t DR9;
577 uint16_t RESERVED9;
578 __IO uint16_t DR10;
579 uint16_t RESERVED10;
580 __IO uint16_t RTCCR;
581 uint16_t RESERVED11;
582 __IO uint16_t CR;
583 uint16_t RESERVED12;
584 __IO uint16_t CSR;
585 uint16_t RESERVED13[5];
586 __IO uint16_t DR11;
587 uint16_t RESERVED14;
588 __IO uint16_t DR12;
589 uint16_t RESERVED15;
590 __IO uint16_t DR13;
591 uint16_t RESERVED16;
592 __IO uint16_t DR14;
593 uint16_t RESERVED17;
594 __IO uint16_t DR15;
595 uint16_t RESERVED18;
596 __IO uint16_t DR16;
597 uint16_t RESERVED19;
598 __IO uint16_t DR17;
599 uint16_t RESERVED20;
600 __IO uint16_t DR18;
601 uint16_t RESERVED21;
602 __IO uint16_t DR19;
603 uint16_t RESERVED22;
604 __IO uint16_t DR20;
605 uint16_t RESERVED23;
606 __IO uint16_t DR21;
607 uint16_t RESERVED24;
608 __IO uint16_t DR22;
609 uint16_t RESERVED25;
610 __IO uint16_t DR23;
611 uint16_t RESERVED26;
612 __IO uint16_t DR24;
613 uint16_t RESERVED27;
614 __IO uint16_t DR25;
615 uint16_t RESERVED28;
616 __IO uint16_t DR26;
617 uint16_t RESERVED29;
618 __IO uint16_t DR27;
619 uint16_t RESERVED30;
620 __IO uint16_t DR28;
621 uint16_t RESERVED31;
622 __IO uint16_t DR29;
623 uint16_t RESERVED32;
624 __IO uint16_t DR30;
625 uint16_t RESERVED33;
626 __IO uint16_t DR31;
627 uint16_t RESERVED34;
628 __IO uint16_t DR32;
629 uint16_t RESERVED35;
630 __IO uint16_t DR33;
631 uint16_t RESERVED36;
632 __IO uint16_t DR34;
633 uint16_t RESERVED37;
634 __IO uint16_t DR35;
635 uint16_t RESERVED38;
636 __IO uint16_t DR36;
637 uint16_t RESERVED39;
638 __IO uint16_t DR37;
639 uint16_t RESERVED40;
640 __IO uint16_t DR38;
641 uint16_t RESERVED41;
642 __IO uint16_t DR39;
643 uint16_t RESERVED42;
644 __IO uint16_t DR40;
645 uint16_t RESERVED43;
646 __IO uint16_t DR41;
647 uint16_t RESERVED44;
648 __IO uint16_t DR42;
649 uint16_t RESERVED45;
650} BKP_TypeDef;
651
652/**
653 * @brief Controller Area Network TxMailBox
654 */
655
656typedef struct
657{
658 __IO uint32_t TIR;
659 __IO uint32_t TDTR;
660 __IO uint32_t TDLR;
661 __IO uint32_t TDHR;
662} CAN_TxMailBox_TypeDef;
663
664/**
665 * @brief Controller Area Network FIFOMailBox
666 */
667
668typedef struct
669{
670 __IO uint32_t RIR;
671 __IO uint32_t RDTR;
672 __IO uint32_t RDLR;
673 __IO uint32_t RDHR;
674} CAN_FIFOMailBox_TypeDef;
675
676/**
677 * @brief Controller Area Network FilterRegister
678 */
679
680typedef struct
681{
682 __IO uint32_t FR1;
683 __IO uint32_t FR2;
684} CAN_FilterRegister_TypeDef;
685
686/**
687 * @brief Controller Area Network
688 */
689
690typedef struct
691{
692 __IO uint32_t MCR;
693 __IO uint32_t MSR;
694 __IO uint32_t TSR;
695 __IO uint32_t RF0R;
696 __IO uint32_t RF1R;
697 __IO uint32_t IER;
698 __IO uint32_t ESR;
699 __IO uint32_t BTR;
700 uint32_t RESERVED0[88];
701 CAN_TxMailBox_TypeDef sTxMailBox[3];
702 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
703 uint32_t RESERVED1[12];
704 __IO uint32_t FMR;
705 __IO uint32_t FM1R;
706 uint32_t RESERVED2;
707 __IO uint32_t FS1R;
708 uint32_t RESERVED3;
709 __IO uint32_t FFA1R;
710 uint32_t RESERVED4;
711 __IO uint32_t FA1R;
712 uint32_t RESERVED5[8];
713#ifndef STM32F10X_CL
714 CAN_FilterRegister_TypeDef sFilterRegister[14];
715#else
716 CAN_FilterRegister_TypeDef sFilterRegister[28];
717#endif /* STM32F10X_CL */
718} CAN_TypeDef;
719
720/**
721 * @brief Consumer Electronics Control (CEC)
722 */
723typedef struct
724{
725 __IO uint32_t CFGR;
726 __IO uint32_t OAR;
727 __IO uint32_t PRES;
728 __IO uint32_t ESR;
729 __IO uint32_t CSR;
730 __IO uint32_t TXD;
731 __IO uint32_t RXD;
732} CEC_TypeDef;
733
734/**
735 * @brief CRC calculation unit
736 */
737
738typedef struct
739{
740 __IO uint32_t DR;
741 __IO uint8_t IDR;
742 uint8_t RESERVED0;
743 uint16_t RESERVED1;
744 __IO uint32_t CR;
745} CRC_TypeDef;
746
747/**
748 * @brief Digital to Analog Converter
749 */
750
751typedef struct
752{
753 __IO uint32_t CR;
754 __IO uint32_t SWTRIGR;
755 __IO uint32_t DHR12R1;
756 __IO uint32_t DHR12L1;
757 __IO uint32_t DHR8R1;
758 __IO uint32_t DHR12R2;
759 __IO uint32_t DHR12L2;
760 __IO uint32_t DHR8R2;
761 __IO uint32_t DHR12RD;
762 __IO uint32_t DHR12LD;
763 __IO uint32_t DHR8RD;
764 __IO uint32_t DOR1;
765 __IO uint32_t DOR2;
766#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
767 __IO uint32_t SR;
768#endif
769} DAC_TypeDef;
770
771/**
772 * @brief Debug MCU
773 */
774
775typedef struct
776{
777 __IO uint32_t IDCODE;
778 __IO uint32_t CR;
779}DBGMCU_TypeDef;
780
781/**
782 * @brief DMA Controller
783 */
784
785typedef struct
786{
787 __IO uint32_t CCR;
788 __IO uint32_t CNDTR;
789 __IO uint32_t CPAR;
790 __IO uint32_t CMAR;
791} DMA_Channel_TypeDef;
792
793typedef struct
794{
795 __IO uint32_t ISR;
796 __IO uint32_t IFCR;
797} DMA_TypeDef;
798
799/**
800 * @brief Ethernet MAC
801 */
802
803typedef struct
804{
805 __IO uint32_t MACCR;
806 __IO uint32_t MACFFR;
807 __IO uint32_t MACHTHR;
808 __IO uint32_t MACHTLR;
809 __IO uint32_t MACMIIAR;
810 __IO uint32_t MACMIIDR;
811 __IO uint32_t MACFCR;
812 __IO uint32_t MACVLANTR; /* 8 */
813 uint32_t RESERVED0[2];
814 __IO uint32_t MACRWUFFR; /* 11 */
815 __IO uint32_t MACPMTCSR;
816 uint32_t RESERVED1[2];
817 __IO uint32_t MACSR; /* 15 */
818 __IO uint32_t MACIMR;
819 __IO uint32_t MACA0HR;
820 __IO uint32_t MACA0LR;
821 __IO uint32_t MACA1HR;
822 __IO uint32_t MACA1LR;
823 __IO uint32_t MACA2HR;
824 __IO uint32_t MACA2LR;
825 __IO uint32_t MACA3HR;
826 __IO uint32_t MACA3LR; /* 24 */
827 uint32_t RESERVED2[40];
828 __IO uint32_t MMCCR; /* 65 */
829 __IO uint32_t MMCRIR;
830 __IO uint32_t MMCTIR;
831 __IO uint32_t MMCRIMR;
832 __IO uint32_t MMCTIMR; /* 69 */
833 uint32_t RESERVED3[14];
834 __IO uint32_t MMCTGFSCCR; /* 84 */
835 __IO uint32_t MMCTGFMSCCR;
836 uint32_t RESERVED4[5];
837 __IO uint32_t MMCTGFCR;
838 uint32_t RESERVED5[10];
839 __IO uint32_t MMCRFCECR;
840 __IO uint32_t MMCRFAECR;
841 uint32_t RESERVED6[10];
842 __IO uint32_t MMCRGUFCR;
843 uint32_t RESERVED7[334];
844 __IO uint32_t PTPTSCR;
845 __IO uint32_t PTPSSIR;
846 __IO uint32_t PTPTSHR;
847 __IO uint32_t PTPTSLR;
848 __IO uint32_t PTPTSHUR;
849 __IO uint32_t PTPTSLUR;
850 __IO uint32_t PTPTSAR;
851 __IO uint32_t PTPTTHR;
852 __IO uint32_t PTPTTLR;
853 uint32_t RESERVED8[567];
854 __IO uint32_t DMABMR;
855 __IO uint32_t DMATPDR;
856 __IO uint32_t DMARPDR;
857 __IO uint32_t DMARDLAR;
858 __IO uint32_t DMATDLAR;
859 __IO uint32_t DMASR;
860 __IO uint32_t DMAOMR;
861 __IO uint32_t DMAIER;
862 __IO uint32_t DMAMFBOCR;
863 uint32_t RESERVED9[9];
864 __IO uint32_t DMACHTDR;
865 __IO uint32_t DMACHRDR;
866 __IO uint32_t DMACHTBAR;
867 __IO uint32_t DMACHRBAR;
868} ETH_TypeDef;
869
870/**
871 * @brief External Interrupt/Event Controller
872 */
873
874typedef struct
875{
876 __IO uint32_t IMR;
877 __IO uint32_t EMR;
878 __IO uint32_t RTSR;
879 __IO uint32_t FTSR;
880 __IO uint32_t SWIER;
881 __IO uint32_t PR;
882} EXTI_TypeDef;
883
884/**
885 * @brief FLASH Registers
886 */
887
888typedef struct
889{
890 __IO uint32_t ACR;
891 __IO uint32_t KEYR;
892 __IO uint32_t OPTKEYR;
893 __IO uint32_t SR;
894 __IO uint32_t CR;
895 __IO uint32_t AR;
896 __IO uint32_t RESERVED;
897 __IO uint32_t OBR;
898 __IO uint32_t WRPR;
899#ifdef STM32F10X_XL
900 uint32_t RESERVED1[8];
901 __IO uint32_t KEYR2;
902 uint32_t RESERVED2;
903 __IO uint32_t SR2;
904 __IO uint32_t CR2;
905 __IO uint32_t AR2;
906#endif /* STM32F10X_XL */
907} FLASH_TypeDef;
908
909/**
910 * @brief Option Bytes Registers
911 */
912
913typedef struct
914{
915 __IO uint16_t RDP;
916 __IO uint16_t USER;
917 __IO uint16_t Data0;
918 __IO uint16_t Data1;
919 __IO uint16_t WRP0;
920 __IO uint16_t WRP1;
921 __IO uint16_t WRP2;
922 __IO uint16_t WRP3;
923} OB_TypeDef;
924
925/**
926 * @brief Flexible Static Memory Controller
927 */
928
929typedef struct
930{
931 __IO uint32_t BTCR[8];
932} FSMC_Bank1_TypeDef;
933
934/**
935 * @brief Flexible Static Memory Controller Bank1E
936 */
937
938typedef struct
939{
940 __IO uint32_t BWTR[7];
941} FSMC_Bank1E_TypeDef;
942
943/**
944 * @brief Flexible Static Memory Controller Bank2
945 */
946
947typedef struct
948{
949 __IO uint32_t PCR2;
950 __IO uint32_t SR2;
951 __IO uint32_t PMEM2;
952 __IO uint32_t PATT2;
953 uint32_t RESERVED0;
954 __IO uint32_t ECCR2;
955} FSMC_Bank2_TypeDef;
956
957/**
958 * @brief Flexible Static Memory Controller Bank3
959 */
960
961typedef struct
962{
963 __IO uint32_t PCR3;
964 __IO uint32_t SR3;
965 __IO uint32_t PMEM3;
966 __IO uint32_t PATT3;
967 uint32_t RESERVED0;
968 __IO uint32_t ECCR3;
969} FSMC_Bank3_TypeDef;
970
971/**
972 * @brief Flexible Static Memory Controller Bank4
973 */
974
975typedef struct
976{
977 __IO uint32_t PCR4;
978 __IO uint32_t SR4;
979 __IO uint32_t PMEM4;
980 __IO uint32_t PATT4;
981 __IO uint32_t PIO4;
982} FSMC_Bank4_TypeDef;
983
984/**
985 * @brief General Purpose I/O
986 */
987
988typedef struct
989{
990 __IO uint32_t CRL;
991 __IO uint32_t CRH;
992 __IO uint32_t IDR;
993 __IO uint32_t ODR;
994 __IO uint32_t BSRR;
995 __IO uint32_t BRR;
996 __IO uint32_t LCKR;
997} GPIO_TypeDef;
998
999/**
1000 * @brief Alternate Function I/O
1001 */
1002
1003typedef struct
1004{
1005 __IO uint32_t EVCR;
1006 __IO uint32_t MAPR;
1007 __IO uint32_t EXTICR[4];
1008 uint32_t RESERVED0;
1009 __IO uint32_t MAPR2;
1010} AFIO_TypeDef;
1011/**
1012 * @brief Inter-integrated Circuit Interface
1013 */
1014
1015typedef struct
1016{
1017 __IO uint16_t CR1;
1018 uint16_t RESERVED0;
1019 __IO uint16_t CR2;
1020 uint16_t RESERVED1;
1021 __IO uint16_t OAR1;
1022 uint16_t RESERVED2;
1023 __IO uint16_t OAR2;
1024 uint16_t RESERVED3;
1025 __IO uint16_t DR;
1026 uint16_t RESERVED4;
1027 __IO uint16_t SR1;
1028 uint16_t RESERVED5;
1029 __IO uint16_t SR2;
1030 uint16_t RESERVED6;
1031 __IO uint16_t CCR;
1032 uint16_t RESERVED7;
1033 __IO uint16_t TRISE;
1034 uint16_t RESERVED8;
1035} I2C_TypeDef;
1036
1037/**
1038 * @brief Independent WATCHDOG
1039 */
1040
1041typedef struct
1042{
1043 __IO uint32_t KR;
1044 __IO uint32_t PR;
1045 __IO uint32_t RLR;
1046 __IO uint32_t SR;
1047} IWDG_TypeDef;
1048
1049/**
1050 * @brief Power Control
1051 */
1052
1053typedef struct
1054{
1055 __IO uint32_t CR;
1056 __IO uint32_t CSR;
1057} PWR_TypeDef;
1058
1059/**
1060 * @brief Reset and Clock Control
1061 */
1062
1063typedef struct
1064{
1065 __IO uint32_t CR;
1066 __IO uint32_t CFGR;
1067 __IO uint32_t CIR;
1068 __IO uint32_t APB2RSTR;
1069 __IO uint32_t APB1RSTR;
1070 __IO uint32_t AHBENR;
1071 __IO uint32_t APB2ENR;
1072 __IO uint32_t APB1ENR;
1073 __IO uint32_t BDCR;
1074 __IO uint32_t CSR;
1075
1076#ifdef STM32F10X_CL
1077 __IO uint32_t AHBRSTR;
1078 __IO uint32_t CFGR2;
1079#endif /* STM32F10X_CL */
1080
1081#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
1082 uint32_t RESERVED0;
1083 __IO uint32_t CFGR2;
1084#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */
1085} RCC_TypeDef;
1086
1087/**
1088 * @brief Real-Time Clock
1089 */
1090
1091typedef struct
1092{
1093 __IO uint16_t CRH;
1094 uint16_t RESERVED0;
1095 __IO uint16_t CRL;
1096 uint16_t RESERVED1;
1097 __IO uint16_t PRLH;
1098 uint16_t RESERVED2;
1099 __IO uint16_t PRLL;
1100 uint16_t RESERVED3;
1101 __IO uint16_t DIVH;
1102 uint16_t RESERVED4;
1103 __IO uint16_t DIVL;
1104 uint16_t RESERVED5;
1105 __IO uint16_t CNTH;
1106 uint16_t RESERVED6;
1107 __IO uint16_t CNTL;
1108 uint16_t RESERVED7;
1109 __IO uint16_t ALRH;
1110 uint16_t RESERVED8;
1111 __IO uint16_t ALRL;
1112 uint16_t RESERVED9;
1113} RTC_TypeDef;
1114
1115/**
1116 * @brief SD host Interface
1117 */
1118
1119typedef struct
1120{
1121 __IO uint32_t POWER;
1122 __IO uint32_t CLKCR;
1123 __IO uint32_t ARG;
1124 __IO uint32_t CMD;
1125 __I uint32_t RESPCMD;
1126 __I uint32_t RESP1;
1127 __I uint32_t RESP2;
1128 __I uint32_t RESP3;
1129 __I uint32_t RESP4;
1130 __IO uint32_t DTIMER;
1131 __IO uint32_t DLEN;
1132 __IO uint32_t DCTRL;
1133 __I uint32_t DCOUNT;
1134 __I uint32_t STA;
1135 __IO uint32_t ICR;
1136 __IO uint32_t MASK;
1137 uint32_t RESERVED0[2];
1138 __I uint32_t FIFOCNT;
1139 uint32_t RESERVED1[13];
1140 __IO uint32_t FIFO;
1141} SDIO_TypeDef;
1142
1143/**
1144 * @brief Serial Peripheral Interface
1145 */
1146
1147typedef struct
1148{
1149 __IO uint16_t CR1;
1150 uint16_t RESERVED0;
1151 __IO uint16_t CR2;
1152 uint16_t RESERVED1;
1153 __IO uint16_t SR;
1154 uint16_t RESERVED2;
1155 __IO uint16_t DR;
1156 uint16_t RESERVED3;
1157 __IO uint16_t CRCPR;
1158 uint16_t RESERVED4;
1159 __IO uint16_t RXCRCR;
1160 uint16_t RESERVED5;
1161 __IO uint16_t TXCRCR;
1162 uint16_t RESERVED6;
1163 __IO uint16_t I2SCFGR;
1164 uint16_t RESERVED7;
1165 __IO uint16_t I2SPR;
1166 uint16_t RESERVED8;
1167} SPI_TypeDef;
1168
1169/**
1170 * @brief TIM
1171 */
1172
1173typedef struct
1174{
1175 __IO uint16_t CR1;
1176 uint16_t RESERVED0;
1177 __IO uint16_t CR2;
1178 uint16_t RESERVED1;
1179 __IO uint16_t SMCR;
1180 uint16_t RESERVED2;
1181 __IO uint16_t DIER;
1182 uint16_t RESERVED3;
1183 __IO uint16_t SR;
1184 uint16_t RESERVED4;
1185 __IO uint16_t EGR;
1186 uint16_t RESERVED5;
1187 __IO uint16_t CCMR1;
1188 uint16_t RESERVED6;
1189 __IO uint16_t CCMR2;
1190 uint16_t RESERVED7;
1191 __IO uint16_t CCER;
1192 uint16_t RESERVED8;
1193 __IO uint16_t CNT;
1194 uint16_t RESERVED9;
1195 __IO uint16_t PSC;
1196 uint16_t RESERVED10;
1197 __IO uint16_t ARR;
1198 uint16_t RESERVED11;
1199 __IO uint16_t RCR;
1200 uint16_t RESERVED12;
1201 __IO uint16_t CCR1;
1202 uint16_t RESERVED13;
1203 __IO uint16_t CCR2;
1204 uint16_t RESERVED14;
1205 __IO uint16_t CCR3;
1206 uint16_t RESERVED15;
1207 __IO uint16_t CCR4;
1208 uint16_t RESERVED16;
1209 __IO uint16_t BDTR;
1210 uint16_t RESERVED17;
1211 __IO uint16_t DCR;
1212 uint16_t RESERVED18;
1213 __IO uint16_t DMAR;
1214 uint16_t RESERVED19;
1215} TIM_TypeDef;
1216
1217/**
1218 * @brief Universal Synchronous Asynchronous Receiver Transmitter
1219 */
1220
1221typedef struct
1222{
1223 __IO uint16_t SR;
1224 uint16_t RESERVED0;
1225 __IO uint16_t DR;
1226 uint16_t RESERVED1;
1227 __IO uint16_t BRR;
1228 uint16_t RESERVED2;
1229 __IO uint16_t CR1;
1230 uint16_t RESERVED3;
1231 __IO uint16_t CR2;
1232 uint16_t RESERVED4;
1233 __IO uint16_t CR3;
1234 uint16_t RESERVED5;
1235 __IO uint16_t GTPR;
1236 uint16_t RESERVED6;
1237} USART_TypeDef;
1238
1239/**
1240 * @brief Window WATCHDOG
1241 */
1242
1243typedef struct
1244{
1245 __IO uint32_t CR;
1246 __IO uint32_t CFR;
1247 __IO uint32_t SR;
1248} WWDG_TypeDef;
1249
1250/**
1251 * @}
1252 */
1253
1254/** @addtogroup Peripheral_memory_map
1255 * @{
1256 */
1257
1258
1259#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
1260#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
1261#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
1262
1263#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
1264#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
1265
1266#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
1267
1268/*!< Peripheral memory map */
1269#define APB1PERIPH_BASE PERIPH_BASE
1270#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
1271#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
1272
1273#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
1274#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
1275#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
1276#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
1277#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
1278#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
1279#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
1280#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
1281#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
1282#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
1283#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
1284#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
1285#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
1286#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
1287#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
1288#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
1289#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
1290#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
1291#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
1292#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
1293#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
1294#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
1295#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
1296#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
1297#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
1298#define CEC_BASE (APB1PERIPH_BASE + 0x7800)
1299
1300#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
1301#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
1302#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
1303#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
1304#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
1305#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
1306#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
1307#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
1308#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
1309#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
1310#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
1311#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
1312#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
1313#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
1314#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
1315#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
1316#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
1317#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
1318#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
1319#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00)
1320#define TIM10_BASE (APB2PERIPH_BASE + 0x5000)
1321#define TIM11_BASE (APB2PERIPH_BASE + 0x5400)
1322
1323#define SDIO_BASE (PERIPH_BASE + 0x18000)
1324
1325#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
1326#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
1327#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
1328#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
1329#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
1330#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
1331#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
1332#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
1333#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
1334#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
1335#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
1336#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
1337#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
1338#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
1339#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
1340#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
1341
1342#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
1343#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
1344
1345#define ETH_BASE (AHBPERIPH_BASE + 0x8000)
1346#define ETH_MAC_BASE (ETH_BASE)
1347#define ETH_MMC_BASE (ETH_BASE + 0x0100)
1348#define ETH_PTP_BASE (ETH_BASE + 0x0700)
1349#define ETH_DMA_BASE (ETH_BASE + 0x1000)
1350
1351#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
1352#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
1353#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */
1354#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */
1355#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
1356
1357#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
1358
1359/**
1360 * @}
1361 */
1362
1363/** @addtogroup Peripheral_declaration
1364 * @{
1365 */
1366
1367#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1368#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1369#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1370#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1371#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1372#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1373#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1374#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1375#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1376#define RTC ((RTC_TypeDef *) RTC_BASE)
1377#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1378#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1379#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1380#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1381#define USART2 ((USART_TypeDef *) USART2_BASE)
1382#define USART3 ((USART_TypeDef *) USART3_BASE)
1383#define UART4 ((USART_TypeDef *) UART4_BASE)
1384#define UART5 ((USART_TypeDef *) UART5_BASE)
1385#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1386#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1387#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1388#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1389#define BKP ((BKP_TypeDef *) BKP_BASE)
1390#define PWR ((PWR_TypeDef *) PWR_BASE)
1391#define DAC ((DAC_TypeDef *) DAC_BASE)
1392#define CEC ((CEC_TypeDef *) CEC_BASE)
1393#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
1394#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1395#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1396#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1397#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1398#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1399#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1400#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1401#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1402#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1403#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1404#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1405#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1406#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1407#define USART1 ((USART_TypeDef *) USART1_BASE)
1408#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1409#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
1410#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
1411#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
1412#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1413#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1414#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1415#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1416#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1417#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1418#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1419#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1420#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1421#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1422#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1423#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1424#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1425#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1426#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1427#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1428#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1429#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1430#define RCC ((RCC_TypeDef *) RCC_BASE)
1431#define CRC ((CRC_TypeDef *) CRC_BASE)
1432#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1433#define OB ((OB_TypeDef *) OB_BASE)
1434#define ETH ((ETH_TypeDef *) ETH_BASE)
1435#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1436#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1437#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
1438#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
1439#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
1440#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1441
1442/**
1443 * @}
1444 */
1445
1446/** @addtogroup Exported_constants
1447 * @{
1448 */
1449
1450 /** @addtogroup Peripheral_Registers_Bits_Definition
1451 * @{
1452 */
1453
1454/******************************************************************************/
1455/* Peripheral Registers_Bits_Definition */
1456/******************************************************************************/
1457
1458/******************************************************************************/
1459/* */
1460/* CRC calculation unit */
1461/* */
1462/******************************************************************************/
1463
1464/******************* Bit definition for CRC_DR register *********************/
1465#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
1466
1467
1468/******************* Bit definition for CRC_IDR register ********************/
1469#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
1470
1471
1472/******************** Bit definition for CRC_CR register ********************/
1473#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */
1474
1475/******************************************************************************/
1476/* */
1477/* Power Control */
1478/* */
1479/******************************************************************************/
1480
1481/******************** Bit definition for PWR_CR register ********************/
1482#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */
1483#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
1484#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
1485#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
1486#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
1487
1488#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
1489#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
1490#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
1491#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
1492
1493/*!< PVD level configuration */
1494#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */
1495#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */
1496#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */
1497#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */
1498#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */
1499#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */
1500#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */
1501#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */
1502
1503#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
1504
1505
1506/******************* Bit definition for PWR_CSR register ********************/
1507#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
1508#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
1509#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
1510#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */
1511
1512/******************************************************************************/
1513/* */
1514/* Backup registers */
1515/* */
1516/******************************************************************************/
1517
1518/******************* Bit definition for BKP_DR1 register ********************/
1519#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */
1520
1521/******************* Bit definition for BKP_DR2 register ********************/
1522#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */
1523
1524/******************* Bit definition for BKP_DR3 register ********************/
1525#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */
1526
1527/******************* Bit definition for BKP_DR4 register ********************/
1528#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */
1529
1530/******************* Bit definition for BKP_DR5 register ********************/
1531#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */
1532
1533/******************* Bit definition for BKP_DR6 register ********************/
1534#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */
1535
1536/******************* Bit definition for BKP_DR7 register ********************/
1537#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */
1538
1539/******************* Bit definition for BKP_DR8 register ********************/
1540#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */
1541
1542/******************* Bit definition for BKP_DR9 register ********************/
1543#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */
1544
1545/******************* Bit definition for BKP_DR10 register *******************/
1546#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */
1547
1548/******************* Bit definition for BKP_DR11 register *******************/
1549#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */
1550
1551/******************* Bit definition for BKP_DR12 register *******************/
1552#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */
1553
1554/******************* Bit definition for BKP_DR13 register *******************/
1555#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */
1556
1557/******************* Bit definition for BKP_DR14 register *******************/
1558#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */
1559
1560/******************* Bit definition for BKP_DR15 register *******************/
1561#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */
1562
1563/******************* Bit definition for BKP_DR16 register *******************/
1564#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */
1565
1566/******************* Bit definition for BKP_DR17 register *******************/
1567#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */
1568
1569/****************** Bit definition for BKP_DR18 register ********************/
1570#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */
1571
1572/******************* Bit definition for BKP_DR19 register *******************/
1573#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */
1574
1575/******************* Bit definition for BKP_DR20 register *******************/
1576#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */
1577
1578/******************* Bit definition for BKP_DR21 register *******************/
1579#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */
1580
1581/******************* Bit definition for BKP_DR22 register *******************/
1582#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */
1583
1584/******************* Bit definition for BKP_DR23 register *******************/
1585#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */
1586
1587/******************* Bit definition for BKP_DR24 register *******************/
1588#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */
1589
1590/******************* Bit definition for BKP_DR25 register *******************/
1591#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */
1592
1593/******************* Bit definition for BKP_DR26 register *******************/
1594#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */
1595
1596/******************* Bit definition for BKP_DR27 register *******************/
1597#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */
1598
1599/******************* Bit definition for BKP_DR28 register *******************/
1600#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */
1601
1602/******************* Bit definition for BKP_DR29 register *******************/
1603#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */
1604
1605/******************* Bit definition for BKP_DR30 register *******************/
1606#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */
1607
1608/******************* Bit definition for BKP_DR31 register *******************/
1609#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */
1610
1611/******************* Bit definition for BKP_DR32 register *******************/
1612#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */
1613
1614/******************* Bit definition for BKP_DR33 register *******************/
1615#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */
1616
1617/******************* Bit definition for BKP_DR34 register *******************/
1618#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */
1619
1620/******************* Bit definition for BKP_DR35 register *******************/
1621#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */
1622
1623/******************* Bit definition for BKP_DR36 register *******************/
1624#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */
1625
1626/******************* Bit definition for BKP_DR37 register *******************/
1627#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */
1628
1629/******************* Bit definition for BKP_DR38 register *******************/
1630#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */
1631
1632/******************* Bit definition for BKP_DR39 register *******************/
1633#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */
1634
1635/******************* Bit definition for BKP_DR40 register *******************/
1636#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */
1637
1638/******************* Bit definition for BKP_DR41 register *******************/
1639#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */
1640
1641/******************* Bit definition for BKP_DR42 register *******************/
1642#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */
1643
1644/****************** Bit definition for BKP_RTCCR register *******************/
1645#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */
1646#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */
1647#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */
1648#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */
1649
1650/******************** Bit definition for BKP_CR register ********************/
1651#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */
1652#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */
1653
1654/******************* Bit definition for BKP_CSR register ********************/
1655#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */
1656#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */
1657#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */
1658#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */
1659#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */
1660
1661/******************************************************************************/
1662/* */
1663/* Reset and Clock Control */
1664/* */
1665/******************************************************************************/
1666
1667/******************** Bit definition for RCC_CR register ********************/
1668#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
1669#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
1670#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
1671#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
1672#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
1673#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
1674#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
1675#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
1676#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
1677#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
1678
1679#ifdef STM32F10X_CL
1680 #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */
1681 #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */
1682 #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */
1683 #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */
1684#endif /* STM32F10X_CL */
1685
1686/******************* Bit definition for RCC_CFGR register *******************/
1687/*!< SW configuration */
1688#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
1689#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
1690#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
1691
1692#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
1693#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
1694#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
1695
1696/*!< SWS configuration */
1697#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
1698#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
1699#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
1700
1701#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
1702#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
1703#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
1704
1705/*!< HPRE configuration */
1706#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
1707#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
1708#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
1709#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
1710#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
1711
1712#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
1713#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
1714#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
1715#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
1716#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
1717#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
1718#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
1719#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
1720#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
1721
1722/*!< PPRE1 configuration */
1723#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
1724#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
1725#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
1726#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
1727
1728#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
1729#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
1730#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
1731#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
1732#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
1733
1734/*!< PPRE2 configuration */
1735#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
1736#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
1737#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
1738#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
1739
1740#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
1741#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
1742#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
1743#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
1744#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
1745
1746/*!< ADCPPRE configuration */
1747#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */
1748#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
1749#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
1750
1751#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
1752#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
1753#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
1754#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
1755
1756#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
1757
1758#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
1759
1760/*!< PLLMUL configuration */
1761#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
1762#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
1763#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
1764#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
1765#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
1766
1767#ifdef STM32F10X_CL
1768 #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
1769 #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */
1770
1771 #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
1772 #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
1773
1774 #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */
1775 #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */
1776 #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */
1777 #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */
1778 #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */
1779 #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */
1780 #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */
1781
1782 #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */
1783
1784/*!< MCO configuration */
1785 #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
1786 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
1787 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
1788 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
1789 #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
1790
1791 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
1792 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
1793 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
1794 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
1795 #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
1796 #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/
1797 #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/
1798 #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
1799 #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */
1800#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
1801 #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
1802 #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */
1803
1804 #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
1805 #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
1806
1807 #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
1808 #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
1809 #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
1810 #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
1811 #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
1812 #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
1813 #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
1814 #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
1815 #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
1816 #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
1817 #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
1818 #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
1819 #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
1820 #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
1821 #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
1822
1823/*!< MCO configuration */
1824 #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
1825 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
1826 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
1827 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
1828
1829 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
1830 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
1831 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
1832 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
1833 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
1834#else
1835 #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
1836 #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */
1837
1838 #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
1839 #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
1840
1841 #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
1842 #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
1843 #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
1844 #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
1845 #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
1846 #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
1847 #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
1848 #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
1849 #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
1850 #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
1851 #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
1852 #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
1853 #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
1854 #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
1855 #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
1856 #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */
1857
1858/*!< MCO configuration */
1859 #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
1860 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
1861 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
1862 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
1863
1864 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
1865 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
1866 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
1867 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
1868 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
1869#endif /* STM32F10X_CL */
1870
1871/*!<****************** Bit definition for RCC_CIR register ********************/
1872#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
1873#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
1874#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
1875#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
1876#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
1877#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
1878#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
1879#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
1880#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
1881#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
1882#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
1883#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
1884#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
1885#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
1886#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
1887#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
1888#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
1889
1890#ifdef STM32F10X_CL
1891 #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */
1892 #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */
1893 #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */
1894 #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */
1895 #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */
1896 #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */
1897#endif /* STM32F10X_CL */
1898
1899/***************** Bit definition for RCC_APB2RSTR register *****************/
1900#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */
1901#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */
1902#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */
1903#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */
1904#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */
1905#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */
1906
1907#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
1908#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */
1909#endif
1910
1911#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */
1912#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */
1913#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
1914
1915#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
1916#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */
1917#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */
1918#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */
1919#endif
1920
1921#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
1922 #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */
1923#endif /* STM32F10X_LD && STM32F10X_LD_VL */
1924
1925#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
1926 #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */
1927 #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */
1928 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */
1929 #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */
1930#endif
1931
1932#if defined (STM32F10X_HD_VL)
1933 #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */
1934 #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */
1935#endif
1936
1937#ifdef STM32F10X_XL
1938 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */
1939 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */
1940 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */
1941#endif /* STM32F10X_XL */
1942
1943/***************** Bit definition for RCC_APB1RSTR register *****************/
1944#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
1945#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
1946#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
1947#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
1948#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
1949
1950#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
1951#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */
1952#endif
1953
1954#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */
1955#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
1956
1957#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
1958 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
1959 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
1960 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */
1961 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
1962#endif /* STM32F10X_LD && STM32F10X_LD_VL */
1963
1964#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL)
1965 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */
1966#endif
1967
1968#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL)
1969 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
1970 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
1971 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
1972 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
1973 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
1974 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
1975 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
1976#endif
1977
1978#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
1979 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
1980 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
1981 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
1982 #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */
1983#endif
1984
1985#if defined (STM32F10X_HD_VL)
1986 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
1987 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */
1988 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */
1989 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */
1990 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
1991 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
1992 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
1993#endif
1994
1995#ifdef STM32F10X_CL
1996 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */
1997#endif /* STM32F10X_CL */
1998
1999#ifdef STM32F10X_XL
2000 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */
2001 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */
2002 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */
2003#endif /* STM32F10X_XL */
2004
2005/****************** Bit definition for RCC_AHBENR register ******************/
2006#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */
2007#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */
2008#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */
2009#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */
2010
2011#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL)
2012 #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */
2013#endif
2014
2015#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
2016 #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */
2017 #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */
2018#endif
2019
2020#if defined (STM32F10X_HD_VL)
2021 #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */
2022#endif
2023
2024#ifdef STM32F10X_CL
2025 #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */
2026 #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */
2027 #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */
2028 #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */
2029#endif /* STM32F10X_CL */
2030
2031/****************** Bit definition for RCC_APB2ENR register *****************/
2032#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */
2033#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */
2034#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */
2035#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */
2036#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */
2037#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */
2038
2039#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
2040#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */
2041#endif
2042
2043#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */
2044#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */
2045#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
2046
2047#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
2048#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */
2049#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */
2050#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */
2051#endif
2052
2053#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
2054 #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */
2055#endif /* STM32F10X_LD && STM32F10X_LD_VL */
2056
2057#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
2058 #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */
2059 #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */
2060 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */
2061 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */
2062#endif
2063
2064#if defined (STM32F10X_HD_VL)
2065 #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */
2066 #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */
2067#endif
2068
2069#ifdef STM32F10X_XL
2070 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */
2071 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */
2072 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */
2073#endif
2074
2075/***************** Bit definition for RCC_APB1ENR register ******************/
2076#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
2077#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
2078#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
2079#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
2080#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
2081
2082#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
2083#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */
2084#endif
2085
2086#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */
2087#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
2088
2089#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
2090 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
2091 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
2092 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
2093 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
2094#endif /* STM32F10X_LD && STM32F10X_LD_VL */
2095
2096#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)
2097 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */
2098#endif
2099
2100#if defined (STM32F10X_HD) || defined (STM32F10X_CL)
2101 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
2102 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
2103 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
2104 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
2105 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
2106 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
2107 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
2108#endif
2109
2110#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
2111 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
2112 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
2113 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
2114 #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */
2115#endif
2116
2117#ifdef STM32F10X_HD_VL
2118 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
2119 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */
2120 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */
2121 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */
2122 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
2123 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
2124 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
2125#endif /* STM32F10X_HD_VL */
2126
2127#ifdef STM32F10X_CL
2128 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */
2129#endif /* STM32F10X_CL */
2130
2131#ifdef STM32F10X_XL
2132 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */
2133 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */
2134 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */
2135#endif /* STM32F10X_XL */
2136
2137/******************* Bit definition for RCC_BDCR register *******************/
2138#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
2139#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
2140#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
2141
2142#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
2143#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
2144#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
2145
2146/*!< RTC congiguration */
2147#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
2148#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
2149#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
2150#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
2151
2152#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
2153#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
2154
2155/******************* Bit definition for RCC_CSR register ********************/
2156#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
2157#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
2158#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
2159#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
2160#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
2161#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
2162#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
2163#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
2164#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
2165
2166#ifdef STM32F10X_CL
2167/******************* Bit definition for RCC_AHBRSTR register ****************/
2168 #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */
2169 #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */
2170
2171/******************* Bit definition for RCC_CFGR2 register ******************/
2172/*!< PREDIV1 configuration */
2173 #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
2174 #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
2175 #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
2176 #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
2177 #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
2178
2179 #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
2180 #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
2181 #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
2182 #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
2183 #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
2184 #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
2185 #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
2186 #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
2187 #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
2188 #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
2189 #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
2190 #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
2191 #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
2192 #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
2193 #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
2194 #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
2195
2196/*!< PREDIV2 configuration */
2197 #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */
2198 #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */
2199 #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */
2200 #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */
2201 #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */
2202
2203 #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */
2204 #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */
2205 #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */
2206 #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */
2207 #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */
2208 #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */
2209 #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */
2210 #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */
2211 #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */
2212 #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */
2213 #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */
2214 #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */
2215 #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */
2216 #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */
2217 #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */
2218 #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */
2219
2220/*!< PLL2MUL configuration */
2221 #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */
2222 #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
2223 #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
2224 #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
2225 #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
2226
2227 #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */
2228 #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */
2229 #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */
2230 #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */
2231 #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */
2232 #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */
2233 #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */
2234 #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */
2235 #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */
2236
2237/*!< PLL3MUL configuration */
2238 #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */
2239 #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
2240 #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
2241 #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */
2242 #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */
2243
2244 #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */
2245 #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */
2246 #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */
2247 #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */
2248 #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */
2249 #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */
2250 #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */
2251 #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */
2252 #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */
2253
2254 #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */
2255 #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */
2256 #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */
2257 #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */
2258 #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */
2259#endif /* STM32F10X_CL */
2260
2261#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
2262/******************* Bit definition for RCC_CFGR2 register ******************/
2263/*!< PREDIV1 configuration */
2264 #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
2265 #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
2266 #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
2267 #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
2268 #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
2269
2270 #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
2271 #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
2272 #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
2273 #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
2274 #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
2275 #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
2276 #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
2277 #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
2278 #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
2279 #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
2280 #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
2281 #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
2282 #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
2283 #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
2284 #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
2285 #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
2286#endif
2287
2288/******************************************************************************/
2289/* */
2290/* General Purpose and Alternate Function I/O */
2291/* */
2292/******************************************************************************/
2293
2294/******************* Bit definition for GPIO_CRL register *******************/
2295#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
2296
2297#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
2298#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
2299#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
2300
2301#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
2302#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */
2303#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */
2304
2305#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
2306#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
2307#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
2308
2309#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
2310#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */
2311#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */
2312
2313#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
2314#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
2315#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
2316
2317#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
2318#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
2319#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
2320
2321#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
2322#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */
2323#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */
2324
2325#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
2326#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */
2327#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */
2328
2329#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
2330
2331#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
2332#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */
2333#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */
2334
2335#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
2336#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
2337#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
2338
2339#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
2340#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */
2341#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */
2342
2343#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
2344#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */
2345#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */
2346
2347#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
2348#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */
2349#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */
2350
2351#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
2352#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */
2353#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */
2354
2355#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
2356#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */
2357#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */
2358
2359#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
2360#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */
2361#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */
2362
2363/******************* Bit definition for GPIO_CRH register *******************/
2364#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
2365
2366#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
2367#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */
2368#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */
2369
2370#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
2371#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */
2372#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */
2373
2374#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
2375#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */
2376#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */
2377
2378#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
2379#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */
2380#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */
2381
2382#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
2383#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */
2384#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */
2385
2386#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
2387#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */
2388#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */
2389
2390#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
2391#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */
2392#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */
2393
2394#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
2395#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */
2396#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */
2397
2398#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
2399
2400#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
2401#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */
2402#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */
2403
2404#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
2405#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */
2406#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */
2407
2408#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
2409#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */
2410#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */
2411
2412#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
2413#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */
2414#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */
2415
2416#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
2417#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */
2418#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */
2419
2420#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
2421#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */
2422#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */
2423
2424#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
2425#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */
2426#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */
2427
2428#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
2429#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */
2430#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */
2431
2432/*!<****************** Bit definition for GPIO_IDR register *******************/
2433#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */
2434#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */
2435#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */
2436#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */
2437#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */
2438#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */
2439#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */
2440#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */
2441#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */
2442#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */
2443#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */
2444#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */
2445#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */
2446#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */
2447#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */
2448#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */
2449
2450/******************* Bit definition for GPIO_ODR register *******************/
2451#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */
2452#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */
2453#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */
2454#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */
2455#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */
2456#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */
2457#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */
2458#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */
2459#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */
2460#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */
2461#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */
2462#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */
2463#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */
2464#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */
2465#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */
2466#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */
2467
2468/****************** Bit definition for GPIO_BSRR register *******************/
2469#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */
2470#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */
2471#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */
2472#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */
2473#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */
2474#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */
2475#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */
2476#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */
2477#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */
2478#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */
2479#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */
2480#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */
2481#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */
2482#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */
2483#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */
2484#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */
2485
2486#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */
2487#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */
2488#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */
2489#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */
2490#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */
2491#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */
2492#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */
2493#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */
2494#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */
2495#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */
2496#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */
2497#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */
2498#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */
2499#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */
2500#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */
2501#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */
2502
2503/******************* Bit definition for GPIO_BRR register *******************/
2504#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */
2505#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */
2506#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */
2507#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */
2508#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */
2509#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */
2510#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */
2511#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */
2512#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */
2513#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */
2514#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */
2515#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */
2516#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */
2517#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */
2518#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */
2519#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */
2520
2521/****************** Bit definition for GPIO_LCKR register *******************/
2522#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */
2523#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */
2524#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */
2525#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */
2526#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */
2527#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */
2528#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */
2529#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */
2530#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */
2531#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */
2532#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */
2533#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */
2534#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */
2535#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */
2536#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */
2537#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */
2538#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */
2539
2540/*----------------------------------------------------------------------------*/
2541
2542/****************** Bit definition for AFIO_EVCR register *******************/
2543#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */
2544#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */
2545#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */
2546#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */
2547#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */
2548
2549/*!< PIN configuration */
2550#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */
2551#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */
2552#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */
2553#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */
2554#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */
2555#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */
2556#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */
2557#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */
2558#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */
2559#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */
2560#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */
2561#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */
2562#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */
2563#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */
2564#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */
2565#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */
2566
2567#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */
2568#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */
2569#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */
2570#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */
2571
2572/*!< PORT configuration */
2573#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */
2574#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */
2575#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */
2576#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */
2577#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */
2578
2579#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */
2580
2581/****************** Bit definition for AFIO_MAPR register *******************/
2582#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */
2583#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */
2584#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */
2585#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */
2586
2587#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
2588#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */
2589#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */
2590
2591/* USART3_REMAP configuration */
2592#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
2593#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
2594#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
2595
2596#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
2597#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */
2598#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */
2599
2600/*!< TIM1_REMAP configuration */
2601#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
2602#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
2603#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
2604
2605#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
2606#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
2607#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
2608
2609/*!< TIM2_REMAP configuration */
2610#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
2611#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
2612#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
2613#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
2614
2615#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
2616#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */
2617#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */
2618
2619/*!< TIM3_REMAP configuration */
2620#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
2621#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
2622#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
2623
2624#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */
2625
2626#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
2627#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */
2628#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */
2629
2630/*!< CAN_REMAP configuration */
2631#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
2632#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
2633#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
2634
2635#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
2636#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */
2637#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */
2638#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */
2639#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */
2640#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */
2641
2642/*!< SWJ_CFG configuration */
2643#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
2644#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */
2645#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */
2646#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */
2647
2648#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
2649#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
2650#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */
2651#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */
2652
2653#ifdef STM32F10X_CL
2654/*!< ETH_REMAP configuration */
2655 #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */
2656
2657/*!< CAN2_REMAP configuration */
2658 #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */
2659
2660/*!< MII_RMII_SEL configuration */
2661 #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */
2662
2663/*!< SPI3_REMAP configuration */
2664 #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */
2665
2666/*!< TIM2ITR1_IREMAP configuration */
2667 #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */
2668
2669/*!< PTP_PPS_REMAP configuration */
2670 #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x20000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */
2671#endif
2672
2673/***************** Bit definition for AFIO_EXTICR1 register *****************/
2674#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
2675#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
2676#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
2677#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
2678
2679/*!< EXTI0 configuration */
2680#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
2681#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
2682#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
2683#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
2684#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
2685#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
2686#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */
2687
2688/*!< EXTI1 configuration */
2689#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
2690#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
2691#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
2692#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
2693#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
2694#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
2695#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */
2696
2697/*!< EXTI2 configuration */
2698#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
2699#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
2700#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
2701#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
2702#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
2703#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
2704#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */
2705
2706/*!< EXTI3 configuration */
2707#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
2708#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
2709#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
2710#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
2711#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
2712#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
2713#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */
2714
2715/***************** Bit definition for AFIO_EXTICR2 register *****************/
2716#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
2717#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
2718#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
2719#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
2720
2721/*!< EXTI4 configuration */
2722#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
2723#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
2724#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
2725#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
2726#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
2727#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
2728#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */
2729
2730/* EXTI5 configuration */
2731#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
2732#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
2733#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
2734#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
2735#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
2736#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
2737#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */
2738
2739/*!< EXTI6 configuration */
2740#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
2741#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
2742#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
2743#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
2744#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
2745#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
2746#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */
2747
2748/*!< EXTI7 configuration */
2749#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
2750#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
2751#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
2752#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
2753#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
2754#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
2755#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */
2756
2757/***************** Bit definition for AFIO_EXTICR3 register *****************/
2758#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
2759#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
2760#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
2761#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
2762
2763/*!< EXTI8 configuration */
2764#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
2765#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
2766#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
2767#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
2768#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
2769#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
2770#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */
2771
2772/*!< EXTI9 configuration */
2773#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
2774#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
2775#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
2776#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
2777#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
2778#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
2779#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */
2780
2781/*!< EXTI10 configuration */
2782#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
2783#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
2784#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
2785#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
2786#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */
2787#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
2788#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */
2789
2790/*!< EXTI11 configuration */
2791#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
2792#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
2793#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
2794#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
2795#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
2796#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
2797#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */
2798
2799/***************** Bit definition for AFIO_EXTICR4 register *****************/
2800#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
2801#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
2802#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
2803#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
2804
2805/* EXTI12 configuration */
2806#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
2807#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
2808#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
2809#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
2810#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
2811#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
2812#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */
2813
2814/* EXTI13 configuration */
2815#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
2816#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
2817#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
2818#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
2819#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
2820#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
2821#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */
2822
2823/*!< EXTI14 configuration */
2824#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
2825#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
2826#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
2827#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
2828#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
2829#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
2830#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */
2831
2832/*!< EXTI15 configuration */
2833#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
2834#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
2835#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
2836#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
2837#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
2838#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
2839#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */
2840
2841#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
2842/****************** Bit definition for AFIO_MAPR2 register ******************/
2843#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */
2844#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */
2845#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */
2846#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */
2847#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */
2848#endif
2849
2850#ifdef STM32F10X_HD_VL
2851#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */
2852#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */
2853#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */
2854#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */
2855#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */
2856#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */
2857#endif
2858
2859#ifdef STM32F10X_XL
2860/****************** Bit definition for AFIO_MAPR2 register ******************/
2861#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */
2862#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */
2863#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */
2864#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */
2865#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */
2866#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */
2867#endif
2868
2869/******************************************************************************/
2870/* */
2871/* SystemTick */
2872/* */
2873/******************************************************************************/
2874
2875/***************** Bit definition for SysTick_CTRL register *****************/
2876#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
2877#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
2878#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
2879#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
2880
2881/***************** Bit definition for SysTick_LOAD register *****************/
2882#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
2883
2884/***************** Bit definition for SysTick_VAL register ******************/
2885#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
2886
2887/***************** Bit definition for SysTick_CALIB register ****************/
2888#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
2889#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
2890#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
2891
2892/******************************************************************************/
2893/* */
2894/* Nested Vectored Interrupt Controller */
2895/* */
2896/******************************************************************************/
2897
2898/****************** Bit definition for NVIC_ISER register *******************/
2899#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
2900#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
2901#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
2902#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
2903#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
2904#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
2905#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
2906#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
2907#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
2908#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
2909#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
2910#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
2911#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
2912#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
2913#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
2914#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
2915#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
2916#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
2917#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
2918#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
2919#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
2920#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
2921#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
2922#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
2923#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
2924#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
2925#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
2926#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
2927#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
2928#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
2929#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
2930#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
2931#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
2932
2933/****************** Bit definition for NVIC_ICER register *******************/
2934#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
2935#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
2936#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
2937#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
2938#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
2939#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
2940#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
2941#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
2942#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
2943#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
2944#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
2945#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
2946#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
2947#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
2948#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
2949#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
2950#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
2951#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
2952#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
2953#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
2954#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
2955#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
2956#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
2957#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
2958#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
2959#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
2960#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
2961#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
2962#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
2963#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
2964#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
2965#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
2966#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
2967
2968/****************** Bit definition for NVIC_ISPR register *******************/
2969#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
2970#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
2971#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
2972#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
2973#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
2974#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
2975#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
2976#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
2977#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
2978#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
2979#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
2980#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
2981#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
2982#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
2983#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
2984#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
2985#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
2986#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
2987#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
2988#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
2989#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
2990#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
2991#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
2992#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
2993#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
2994#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
2995#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
2996#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
2997#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
2998#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
2999#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
3000#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
3001#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
3002
3003/****************** Bit definition for NVIC_ICPR register *******************/
3004#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
3005#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
3006#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
3007#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
3008#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
3009#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
3010#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
3011#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
3012#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
3013#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
3014#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
3015#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
3016#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
3017#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
3018#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
3019#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
3020#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
3021#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
3022#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
3023#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
3024#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
3025#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
3026#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
3027#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
3028#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
3029#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
3030#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
3031#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
3032#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
3033#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
3034#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
3035#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
3036#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
3037
3038/****************** Bit definition for NVIC_IABR register *******************/
3039#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
3040#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
3041#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
3042#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
3043#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
3044#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
3045#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
3046#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
3047#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
3048#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
3049#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
3050#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
3051#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
3052#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
3053#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
3054#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
3055#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
3056#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
3057#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
3058#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
3059#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
3060#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
3061#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
3062#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
3063#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
3064#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
3065#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
3066#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
3067#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
3068#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
3069#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
3070#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
3071#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
3072
3073/****************** Bit definition for NVIC_PRI0 register *******************/
3074#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
3075#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
3076#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
3077#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
3078
3079/****************** Bit definition for NVIC_PRI1 register *******************/
3080#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
3081#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
3082#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
3083#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
3084
3085/****************** Bit definition for NVIC_PRI2 register *******************/
3086#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
3087#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
3088#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
3089#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
3090
3091/****************** Bit definition for NVIC_PRI3 register *******************/
3092#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
3093#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
3094#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
3095#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
3096
3097/****************** Bit definition for NVIC_PRI4 register *******************/
3098#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
3099#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
3100#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
3101#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
3102
3103/****************** Bit definition for NVIC_PRI5 register *******************/
3104#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
3105#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
3106#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
3107#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
3108
3109/****************** Bit definition for NVIC_PRI6 register *******************/
3110#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
3111#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
3112#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
3113#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
3114
3115/****************** Bit definition for NVIC_PRI7 register *******************/
3116#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
3117#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
3118#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
3119#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
3120
3121/****************** Bit definition for SCB_CPUID register *******************/
3122#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
3123#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
3124#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
3125#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
3126#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
3127
3128/******************* Bit definition for SCB_ICSR register *******************/
3129#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
3130#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
3131#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
3132#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
3133#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
3134#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
3135#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
3136#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
3137#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
3138#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
3139
3140/******************* Bit definition for SCB_VTOR register *******************/
3141#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
3142#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
3143
3144/*!<***************** Bit definition for SCB_AIRCR register *******************/
3145#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
3146#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
3147#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
3148
3149#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
3150#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
3151#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
3152#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
3153
3154/* prority group configuration */
3155#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
3156#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
3157#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
3158#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
3159#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
3160#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
3161#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
3162#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
3163
3164#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
3165#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
3166
3167/******************* Bit definition for SCB_SCR register ********************/
3168#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */
3169#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */
3170#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */
3171
3172/******************** Bit definition for SCB_CCR register *******************/
3173#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
3174#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
3175#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */
3176#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */
3177#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */
3178#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
3179
3180/******************* Bit definition for SCB_SHPR register ********************/
3181#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
3182#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
3183#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
3184#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
3185
3186/****************** Bit definition for SCB_SHCSR register *******************/
3187#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
3188#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
3189#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
3190#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
3191#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
3192#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
3193#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
3194#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
3195#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
3196#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
3197#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
3198#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
3199#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
3200#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
3201
3202/******************* Bit definition for SCB_CFSR register *******************/
3203/*!< MFSR */
3204#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
3205#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
3206#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
3207#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
3208#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
3209/*!< BFSR */
3210#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
3211#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
3212#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
3213#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
3214#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
3215#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
3216/*!< UFSR */
3217#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */
3218#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
3219#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
3220#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
3221#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
3222#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
3223
3224/******************* Bit definition for SCB_HFSR register *******************/
3225#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */
3226#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
3227#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
3228
3229/******************* Bit definition for SCB_DFSR register *******************/
3230#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */
3231#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */
3232#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */
3233#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */
3234#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */
3235
3236/******************* Bit definition for SCB_MMFAR register ******************/
3237#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
3238
3239/******************* Bit definition for SCB_BFAR register *******************/
3240#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
3241
3242/******************* Bit definition for SCB_afsr register *******************/
3243#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
3244
3245/******************************************************************************/
3246/* */
3247/* External Interrupt/Event Controller */
3248/* */
3249/******************************************************************************/
3250
3251/******************* Bit definition for EXTI_IMR register *******************/
3252#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
3253#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
3254#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
3255#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
3256#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
3257#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
3258#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
3259#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
3260#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
3261#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
3262#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
3263#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
3264#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
3265#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
3266#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
3267#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
3268#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
3269#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
3270#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
3271#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
3272
3273/******************* Bit definition for EXTI_EMR register *******************/
3274#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
3275#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
3276#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
3277#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
3278#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
3279#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
3280#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
3281#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
3282#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
3283#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
3284#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
3285#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
3286#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
3287#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
3288#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
3289#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
3290#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
3291#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
3292#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
3293#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
3294
3295/****************** Bit definition for EXTI_RTSR register *******************/
3296#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
3297#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
3298#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
3299#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
3300#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
3301#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
3302#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
3303#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
3304#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
3305#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
3306#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
3307#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
3308#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
3309#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
3310#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
3311#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
3312#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
3313#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
3314#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
3315#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
3316
3317/****************** Bit definition for EXTI_FTSR register *******************/
3318#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
3319#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
3320#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
3321#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
3322#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
3323#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
3324#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
3325#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
3326#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
3327#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
3328#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
3329#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
3330#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
3331#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
3332#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
3333#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
3334#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
3335#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
3336#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
3337#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
3338
3339/****************** Bit definition for EXTI_SWIER register ******************/
3340#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
3341#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
3342#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
3343#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
3344#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
3345#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
3346#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
3347#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
3348#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
3349#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
3350#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
3351#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
3352#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
3353#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
3354#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
3355#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
3356#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
3357#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
3358#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
3359#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
3360
3361/******************* Bit definition for EXTI_PR register ********************/
3362#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
3363#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
3364#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
3365#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
3366#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
3367#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
3368#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
3369#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
3370#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
3371#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
3372#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
3373#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
3374#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
3375#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
3376#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
3377#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
3378#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
3379#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
3380#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
3381#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
3382
3383/******************************************************************************/
3384/* */
3385/* DMA Controller */
3386/* */
3387/******************************************************************************/
3388
3389/******************* Bit definition for DMA_ISR register ********************/
3390#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
3391#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
3392#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
3393#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
3394#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
3395#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
3396#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
3397#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
3398#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
3399#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
3400#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
3401#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
3402#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
3403#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
3404#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
3405#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
3406#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
3407#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
3408#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
3409#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
3410#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
3411#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
3412#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
3413#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
3414#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
3415#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
3416#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
3417#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
3418
3419/******************* Bit definition for DMA_IFCR register *******************/
3420#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */
3421#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
3422#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
3423#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
3424#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
3425#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
3426#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
3427#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
3428#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
3429#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
3430#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
3431#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
3432#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
3433#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
3434#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
3435#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
3436#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
3437#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
3438#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
3439#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
3440#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
3441#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
3442#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
3443#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
3444#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
3445#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
3446#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
3447#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
3448
3449/******************* Bit definition for DMA_CCR1 register *******************/
3450#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/
3451#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
3452#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
3453#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
3454#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
3455#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */
3456#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
3457#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
3458
3459#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
3460#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
3461#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
3462
3463#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
3464#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
3465#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
3466
3467#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */
3468#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
3469#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
3470
3471#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
3472
3473/******************* Bit definition for DMA_CCR2 register *******************/
3474#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */
3475#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */
3476#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
3477#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
3478#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
3479#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */
3480#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
3481#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
3482
3483#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
3484#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
3485#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
3486
3487#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
3488#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
3489#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
3490
3491#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
3492#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
3493#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
3494
3495#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
3496
3497/******************* Bit definition for DMA_CCR3 register *******************/
3498#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */
3499#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
3500#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
3501#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
3502#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
3503#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */
3504#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
3505#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
3506
3507#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
3508#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
3509#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
3510
3511#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
3512#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
3513#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
3514
3515#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
3516#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
3517#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
3518
3519#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
3520
3521/*!<****************** Bit definition for DMA_CCR4 register *******************/
3522#define DMA_CCR4_EN ((uint16_t)0x0001) /*!<Channel enable */
3523#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
3524#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
3525#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
3526#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
3527#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!<Circular mode */
3528#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
3529#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
3530
3531#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
3532#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
3533#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
3534
3535#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
3536#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
3537#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
3538
3539#define DMA_CCR4_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
3540#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
3541#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
3542
3543#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode */
3544
3545/****************** Bit definition for DMA_CCR5 register *******************/
3546#define DMA_CCR5_EN ((uint16_t)0x0001) /*!<Channel enable */
3547#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
3548#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
3549#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
3550#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
3551#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!<Circular mode */
3552#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
3553#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
3554
3555#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
3556#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
3557#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
3558
3559#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
3560#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
3561#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
3562
3563#define DMA_CCR5_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
3564#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
3565#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
3566
3567#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode enable */
3568
3569/******************* Bit definition for DMA_CCR6 register *******************/
3570#define DMA_CCR6_EN ((uint16_t)0x0001) /*!<Channel enable */
3571#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
3572#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
3573#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
3574#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
3575#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!<Circular mode */
3576#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
3577#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
3578
3579#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
3580#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
3581#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
3582
3583#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
3584#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
3585#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
3586
3587#define DMA_CCR6_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
3588#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
3589#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
3590
3591#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode */
3592
3593/******************* Bit definition for DMA_CCR7 register *******************/
3594#define DMA_CCR7_EN ((uint16_t)0x0001) /*!<Channel enable */
3595#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!<Transfer complete interrupt enable */
3596#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!<Half Transfer interrupt enable */
3597#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!<Transfer error interrupt enable */
3598#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!<Data transfer direction */
3599#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!<Circular mode */
3600#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!<Peripheral increment mode */
3601#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!<Memory increment mode */
3602
3603#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!<PSIZE[1:0] bits (Peripheral size) */
3604#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!<Bit 0 */
3605#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!<Bit 1 */
3606
3607#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!<MSIZE[1:0] bits (Memory size) */
3608#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!<Bit 0 */
3609#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!<Bit 1 */
3610
3611#define DMA_CCR7_PL ((uint16_t)0x3000) /*!<PL[1:0] bits (Channel Priority level) */
3612#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!<Bit 0 */
3613#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!<Bit 1 */
3614
3615#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!<Memory to memory mode enable */
3616
3617/****************** Bit definition for DMA_CNDTR1 register ******************/
3618#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
3619
3620/****************** Bit definition for DMA_CNDTR2 register ******************/
3621#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
3622
3623/****************** Bit definition for DMA_CNDTR3 register ******************/
3624#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
3625
3626/****************** Bit definition for DMA_CNDTR4 register ******************/
3627#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
3628
3629/****************** Bit definition for DMA_CNDTR5 register ******************/
3630#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
3631
3632/****************** Bit definition for DMA_CNDTR6 register ******************/
3633#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
3634
3635/****************** Bit definition for DMA_CNDTR7 register ******************/
3636#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!<Number of data to Transfer */
3637
3638/****************** Bit definition for DMA_CPAR1 register *******************/
3639#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
3640
3641/****************** Bit definition for DMA_CPAR2 register *******************/
3642#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
3643
3644/****************** Bit definition for DMA_CPAR3 register *******************/
3645#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
3646
3647
3648/****************** Bit definition for DMA_CPAR4 register *******************/
3649#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
3650
3651/****************** Bit definition for DMA_CPAR5 register *******************/
3652#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
3653
3654/****************** Bit definition for DMA_CPAR6 register *******************/
3655#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
3656
3657
3658/****************** Bit definition for DMA_CPAR7 register *******************/
3659#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!<Peripheral Address */
3660
3661/****************** Bit definition for DMA_CMAR1 register *******************/
3662#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
3663
3664/****************** Bit definition for DMA_CMAR2 register *******************/
3665#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
3666
3667/****************** Bit definition for DMA_CMAR3 register *******************/
3668#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
3669
3670
3671/****************** Bit definition for DMA_CMAR4 register *******************/
3672#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
3673
3674/****************** Bit definition for DMA_CMAR5 register *******************/
3675#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
3676
3677/****************** Bit definition for DMA_CMAR6 register *******************/
3678#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
3679
3680/****************** Bit definition for DMA_CMAR7 register *******************/
3681#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!<Memory Address */
3682
3683/******************************************************************************/
3684/* */
3685/* Analog to Digital Converter */
3686/* */
3687/******************************************************************************/
3688
3689/******************** Bit definition for ADC_SR register ********************/
3690#define ADC_SR_AWD ((uint8_t)0x01) /*!<Analog watchdog flag */
3691#define ADC_SR_EOC ((uint8_t)0x02) /*!<End of conversion */
3692#define ADC_SR_JEOC ((uint8_t)0x04) /*!<Injected channel end of conversion */
3693#define ADC_SR_JSTRT ((uint8_t)0x08) /*!<Injected channel Start flag */
3694#define ADC_SR_STRT ((uint8_t)0x10) /*!<Regular channel Start flag */
3695
3696/******************* Bit definition for ADC_CR1 register ********************/
3697#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
3698#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3699#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3700#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3701#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3702#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3703
3704#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
3705#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
3706#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
3707#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
3708#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
3709#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
3710#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
3711#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
3712
3713#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
3714#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
3715#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
3716#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
3717
3718#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!<DUALMOD[3:0] bits (Dual mode selection) */
3719#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3720#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3721#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3722#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3723
3724#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
3725#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
3726
3727
3728/******************* Bit definition for ADC_CR2 register ********************/
3729#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
3730#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
3731#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!<A/D Calibration */
3732#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!<Reset Calibration */
3733#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
3734#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
3735
3736#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!<JEXTSEL[2:0] bits (External event select for injected group) */
3737#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!<Bit 0 */
3738#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!<Bit 1 */
3739#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!<Bit 2 */
3740
3741#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!<External Trigger Conversion mode for injected channels */
3742
3743#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!<EXTSEL[2:0] bits (External Event Select for regular group) */
3744#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!<Bit 0 */
3745#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!<Bit 1 */
3746#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!<Bit 2 */
3747
3748#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!<External Trigger Conversion mode for regular channels */
3749#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!<Start Conversion of injected channels */
3750#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!<Start Conversion of regular channels */
3751#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
3752
3753/****************** Bit definition for ADC_SMPR1 register *******************/
3754#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
3755#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3756#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3757#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3758
3759#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
3760#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
3761#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
3762#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
3763
3764#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
3765#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
3766#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
3767#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
3768
3769#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
3770#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
3771#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
3772#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
3773
3774#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
3775#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
3776#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
3777#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
3778
3779#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
3780#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
3781#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
3782#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
3783
3784#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
3785#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
3786#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
3787#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
3788
3789#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
3790#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
3791#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
3792#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
3793
3794/****************** Bit definition for ADC_SMPR2 register *******************/
3795#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
3796#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3797#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3798#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3799
3800#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
3801#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
3802#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
3803#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
3804
3805#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
3806#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
3807#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
3808#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
3809
3810#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
3811#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
3812#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
3813#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
3814
3815#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
3816#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
3817#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
3818#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
3819
3820#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
3821#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
3822#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
3823#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
3824
3825#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
3826#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
3827#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
3828#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
3829
3830#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
3831#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
3832#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
3833#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
3834
3835#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
3836#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3837#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3838#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3839
3840#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
3841#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
3842#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
3843#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
3844
3845/****************** Bit definition for ADC_JOFR1 register *******************/
3846#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */
3847
3848/****************** Bit definition for ADC_JOFR2 register *******************/
3849#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */
3850
3851/****************** Bit definition for ADC_JOFR3 register *******************/
3852#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */
3853
3854/****************** Bit definition for ADC_JOFR4 register *******************/
3855#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */
3856
3857/******************* Bit definition for ADC_HTR register ********************/
3858#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */
3859
3860/******************* Bit definition for ADC_LTR register ********************/
3861#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */
3862
3863/******************* Bit definition for ADC_SQR1 register *******************/
3864#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
3865#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3866#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3867#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3868#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3869#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3870
3871#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
3872#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
3873#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
3874#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
3875#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
3876#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
3877
3878#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
3879#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
3880#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
3881#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
3882#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
3883#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
3884
3885#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
3886#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
3887#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
3888#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
3889#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
3890#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
3891
3892#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
3893#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3894#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3895#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3896#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3897
3898/******************* Bit definition for ADC_SQR2 register *******************/
3899#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
3900#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3901#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3902#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3903#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3904#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3905
3906#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
3907#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
3908#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
3909#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
3910#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
3911#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
3912
3913#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
3914#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
3915#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
3916#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
3917#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
3918#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
3919
3920#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
3921#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
3922#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
3923#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
3924#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
3925#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
3926
3927#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
3928#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3929#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3930#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3931#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3932#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
3933
3934#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
3935#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
3936#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
3937#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
3938#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
3939#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
3940
3941/******************* Bit definition for ADC_SQR3 register *******************/
3942#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
3943#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3944#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3945#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3946#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3947#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3948
3949#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
3950#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
3951#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
3952#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
3953#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
3954#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
3955
3956#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
3957#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
3958#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
3959#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
3960#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
3961#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
3962
3963#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
3964#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
3965#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
3966#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
3967#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
3968#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
3969
3970#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
3971#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3972#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3973#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3974#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3975#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
3976
3977#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
3978#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
3979#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
3980#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
3981#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
3982#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
3983
3984/******************* Bit definition for ADC_JSQR register *******************/
3985#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
3986#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3987#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3988#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3989#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3990#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3991
3992#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
3993#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
3994#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
3995#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
3996#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
3997#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
3998
3999#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
4000#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
4001#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
4002#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
4003#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
4004#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
4005
4006#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
4007#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
4008#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
4009#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
4010#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
4011#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
4012
4013#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
4014#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4015#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4016
4017/******************* Bit definition for ADC_JDR1 register *******************/
4018#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
4019
4020/******************* Bit definition for ADC_JDR2 register *******************/
4021#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
4022
4023/******************* Bit definition for ADC_JDR3 register *******************/
4024#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
4025
4026/******************* Bit definition for ADC_JDR4 register *******************/
4027#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
4028
4029/******************** Bit definition for ADC_DR register ********************/
4030#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
4031#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
4032
4033/******************************************************************************/
4034/* */
4035/* Digital to Analog Converter */
4036/* */
4037/******************************************************************************/
4038
4039/******************** Bit definition for DAC_CR register ********************/
4040#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
4041#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
4042#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
4043
4044#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
4045#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
4046#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
4047#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
4048
4049#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
4050#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
4051#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
4052
4053#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
4054#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4055#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4056#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4057#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4058
4059#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
4060#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
4061#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
4062#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
4063
4064#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
4065#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
4066#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
4067#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
4068
4069#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
4070#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
4071#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
4072
4073#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
4074#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4075#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4076#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4077#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4078
4079#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
4080
4081/***************** Bit definition for DAC_SWTRIGR register ******************/
4082#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */
4083#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */
4084
4085/***************** Bit definition for DAC_DHR12R1 register ******************/
4086#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
4087
4088/***************** Bit definition for DAC_DHR12L1 register ******************/
4089#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
4090
4091/****************** Bit definition for DAC_DHR8R1 register ******************/
4092#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
4093
4094/***************** Bit definition for DAC_DHR12R2 register ******************/
4095#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
4096
4097/***************** Bit definition for DAC_DHR12L2 register ******************/
4098#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
4099
4100/****************** Bit definition for DAC_DHR8R2 register ******************/
4101#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
4102
4103/***************** Bit definition for DAC_DHR12RD register ******************/
4104#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
4105#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
4106
4107/***************** Bit definition for DAC_DHR12LD register ******************/
4108#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
4109#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
4110
4111/****************** Bit definition for DAC_DHR8RD register ******************/
4112#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
4113#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
4114
4115/******************* Bit definition for DAC_DOR1 register *******************/
4116#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */
4117
4118/******************* Bit definition for DAC_DOR2 register *******************/
4119#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
4120
4121/******************** Bit definition for DAC_SR register ********************/
4122#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
4123#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
4124
4125/******************************************************************************/
4126/* */
4127/* CEC */
4128/* */
4129/******************************************************************************/
4130/******************** Bit definition for CEC_CFGR register ******************/
4131#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */
4132#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */
4133#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */
4134#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */
4135
4136/******************** Bit definition for CEC_OAR register ******************/
4137#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */
4138#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */
4139#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */
4140#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */
4141#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */
4142
4143/******************** Bit definition for CEC_PRES register ******************/
4144#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */
4145
4146/******************** Bit definition for CEC_ESR register ******************/
4147#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */
4148#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */
4149#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */
4150#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */
4151#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */
4152#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */
4153#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finsihed Error */
4154
4155/******************** Bit definition for CEC_CSR register ******************/
4156#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */
4157#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */
4158#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */
4159#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */
4160#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */
4161#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */
4162#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */
4163#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */
4164
4165/******************** Bit definition for CEC_TXD register ******************/
4166#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */
4167
4168/******************** Bit definition for CEC_RXD register ******************/
4169#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */
4170
4171/******************************************************************************/
4172/* */
4173/* TIM */
4174/* */
4175/******************************************************************************/
4176
4177/******************* Bit definition for TIM_CR1 register ********************/
4178#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
4179#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
4180#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
4181#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
4182#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
4183
4184#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
4185#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
4186#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
4187
4188#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
4189
4190#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
4191#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
4192#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
4193
4194/******************* Bit definition for TIM_CR2 register ********************/
4195#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */
4196#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */
4197#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
4198
4199#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
4200#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
4201#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
4202#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
4203
4204#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
4205#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
4206#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
4207#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
4208#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
4209#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
4210#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
4211#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
4212
4213/******************* Bit definition for TIM_SMCR register *******************/
4214#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
4215#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
4216#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
4217#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
4218
4219#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
4220#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
4221#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
4222#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
4223
4224#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
4225
4226#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
4227#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
4228#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
4229#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
4230#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
4231
4232#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
4233#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
4234#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
4235
4236#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
4237#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
4238
4239/******************* Bit definition for TIM_DIER register *******************/
4240#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
4241#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
4242#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
4243#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
4244#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
4245#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
4246#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
4247#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
4248#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
4249#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
4250#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
4251#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
4252#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
4253#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
4254#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
4255
4256/******************** Bit definition for TIM_SR register ********************/
4257#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
4258#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
4259#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
4260#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
4261#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
4262#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */
4263#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
4264#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */
4265#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
4266#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
4267#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
4268#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
4269
4270/******************* Bit definition for TIM_EGR register ********************/
4271#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
4272#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
4273#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
4274#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
4275#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
4276#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */
4277#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
4278#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */
4279
4280/****************** Bit definition for TIM_CCMR1 register *******************/
4281#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
4282#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
4283#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
4284
4285#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
4286#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
4287
4288#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
4289#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
4290#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
4291#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
4292
4293#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
4294
4295#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
4296#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
4297#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
4298
4299#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
4300#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
4301
4302#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
4303#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
4304#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
4305#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
4306
4307#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
4308
4309/*----------------------------------------------------------------------------*/
4310
4311#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
4312#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
4313#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
4314
4315#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
4316#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
4317#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
4318#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
4319#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
4320
4321#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
4322#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
4323#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
4324
4325#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
4326#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
4327#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
4328#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
4329#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
4330
4331/****************** Bit definition for TIM_CCMR2 register *******************/
4332#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
4333#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
4334#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
4335
4336#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
4337#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
4338
4339#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
4340#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
4341#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
4342#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
4343
4344#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
4345
4346#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
4347#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
4348#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
4349
4350#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
4351#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
4352
4353#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
4354#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
4355#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
4356#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
4357
4358#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
4359
4360/*----------------------------------------------------------------------------*/
4361
4362#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
4363#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
4364#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
4365
4366#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
4367#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
4368#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
4369#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
4370#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
4371
4372#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
4373#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
4374#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
4375
4376#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
4377#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
4378#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
4379#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
4380#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
4381
4382/******************* Bit definition for TIM_CCER register *******************/
4383#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
4384#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
4385#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
4386#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
4387#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
4388#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
4389#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
4390#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
4391#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
4392#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
4393#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
4394#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
4395#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
4396#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
4397#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
4398
4399/******************* Bit definition for TIM_CNT register ********************/
4400#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
4401
4402/******************* Bit definition for TIM_PSC register ********************/
4403#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
4404
4405/******************* Bit definition for TIM_ARR register ********************/
4406#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
4407
4408/******************* Bit definition for TIM_RCR register ********************/
4409#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
4410
4411/******************* Bit definition for TIM_CCR1 register *******************/
4412#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
4413
4414/******************* Bit definition for TIM_CCR2 register *******************/
4415#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
4416
4417/******************* Bit definition for TIM_CCR3 register *******************/
4418#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
4419
4420/******************* Bit definition for TIM_CCR4 register *******************/
4421#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
4422
4423/******************* Bit definition for TIM_BDTR register *******************/
4424#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
4425#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */
4426#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */
4427#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */
4428#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */
4429#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */
4430#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */
4431#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */
4432#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */
4433
4434#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
4435#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */
4436#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */
4437
4438#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */
4439#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */
4440#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */
4441#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */
4442#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */
4443#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */
4444
4445/******************* Bit definition for TIM_DCR register ********************/
4446#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
4447#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
4448#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
4449#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
4450#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
4451#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
4452
4453#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
4454#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
4455#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
4456#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
4457#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
4458#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
4459
4460/******************* Bit definition for TIM_DMAR register *******************/
4461#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
4462
4463/******************************************************************************/
4464/* */
4465/* Real-Time Clock */
4466/* */
4467/******************************************************************************/
4468
4469/******************* Bit definition for RTC_CRH register ********************/
4470#define RTC_CRH_SECIE ((uint8_t)0x01) /*!<Second Interrupt Enable */
4471#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!<Alarm Interrupt Enable */
4472#define RTC_CRH_OWIE ((uint8_t)0x04) /*!<OverfloW Interrupt Enable */
4473
4474/******************* Bit definition for RTC_CRL register ********************/
4475#define RTC_CRL_SECF ((uint8_t)0x01) /*!<Second Flag */
4476#define RTC_CRL_ALRF ((uint8_t)0x02) /*!<Alarm Flag */
4477#define RTC_CRL_OWF ((uint8_t)0x04) /*!<OverfloW Flag */
4478#define RTC_CRL_RSF ((uint8_t)0x08) /*!<Registers Synchronized Flag */
4479#define RTC_CRL_CNF ((uint8_t)0x10) /*!<Configuration Flag */
4480#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!<RTC operation OFF */
4481
4482/******************* Bit definition for RTC_PRLH register *******************/
4483#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!<RTC Prescaler Reload Value High */
4484
4485/******************* Bit definition for RTC_PRLL register *******************/
4486#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!<RTC Prescaler Reload Value Low */
4487
4488/******************* Bit definition for RTC_DIVH register *******************/
4489#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!<RTC Clock Divider High */
4490
4491/******************* Bit definition for RTC_DIVL register *******************/
4492#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!<RTC Clock Divider Low */
4493
4494/******************* Bit definition for RTC_CNTH register *******************/
4495#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!<RTC Counter High */
4496
4497/******************* Bit definition for RTC_CNTL register *******************/
4498#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!<RTC Counter Low */
4499
4500/******************* Bit definition for RTC_ALRH register *******************/
4501#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!<RTC Alarm High */
4502
4503/******************* Bit definition for RTC_ALRL register *******************/
4504#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!<RTC Alarm Low */
4505
4506/******************************************************************************/
4507/* */
4508/* Independent WATCHDOG */
4509/* */
4510/******************************************************************************/
4511
4512/******************* Bit definition for IWDG_KR register ********************/
4513#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */
4514
4515/******************* Bit definition for IWDG_PR register ********************/
4516#define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */
4517#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */
4518#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */
4519#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */
4520
4521/******************* Bit definition for IWDG_RLR register *******************/
4522#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */
4523
4524/******************* Bit definition for IWDG_SR register ********************/
4525#define IWDG_SR_PVU ((uint8_t)0x01) /*!<Watchdog prescaler value update */
4526#define IWDG_SR_RVU ((uint8_t)0x02) /*!<Watchdog counter reload value update */
4527
4528/******************************************************************************/
4529/* */
4530/* Window WATCHDOG */
4531/* */
4532/******************************************************************************/
4533
4534/******************* Bit definition for WWDG_CR register ********************/
4535#define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
4536#define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */
4537#define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */
4538#define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */
4539#define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */
4540#define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */
4541#define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */
4542#define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */
4543
4544#define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */
4545
4546/******************* Bit definition for WWDG_CFR register *******************/
4547#define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
4548#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */
4549#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */
4550#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */
4551#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */
4552#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */
4553#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */
4554#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */
4555
4556#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
4557#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */
4558#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */
4559
4560#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */
4561
4562/******************* Bit definition for WWDG_SR register ********************/
4563#define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */
4564
4565/******************************************************************************/
4566/* */
4567/* Flexible Static Memory Controller */
4568/* */
4569/******************************************************************************/
4570
4571/****************** Bit definition for FSMC_BCR1 register *******************/
4572#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
4573#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
4574
4575#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
4576#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4577#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4578
4579#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
4580#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4581#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4582
4583#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
4584#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
4585#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
4586#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
4587#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
4588#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
4589#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
4590#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
4591#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
4592#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
4593
4594/****************** Bit definition for FSMC_BCR2 register *******************/
4595#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
4596#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
4597
4598#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
4599#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4600#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4601
4602#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
4603#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4604#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4605
4606#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
4607#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
4608#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
4609#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
4610#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
4611#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
4612#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
4613#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
4614#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
4615#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
4616
4617/****************** Bit definition for FSMC_BCR3 register *******************/
4618#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
4619#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
4620
4621#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
4622#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4623#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4624
4625#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
4626#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4627#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4628
4629#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
4630#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
4631#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit. */
4632#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
4633#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
4634#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
4635#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
4636#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
4637#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
4638#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
4639
4640/****************** Bit definition for FSMC_BCR4 register *******************/
4641#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
4642#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
4643
4644#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
4645#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4646#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4647
4648#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
4649#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4650#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4651
4652#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
4653#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
4654#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
4655#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
4656#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
4657#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
4658#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
4659#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
4660#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
4661#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
4662
4663/****************** Bit definition for FSMC_BTR1 register ******************/
4664#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4665#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4666#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4667#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4668#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4669
4670#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4671#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4672#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4673#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4674#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4675
4676#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4677#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4678#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4679#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4680#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4681
4682#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4683#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4684#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4685#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4686#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4687
4688#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4689#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4690#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4691#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4692#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4693
4694#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4695#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4696#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4697#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4698#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4699
4700#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4701#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4702#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4703
4704/****************** Bit definition for FSMC_BTR2 register *******************/
4705#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4706#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4707#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4708#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4709#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4710
4711#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4712#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4713#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4714#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4715#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4716
4717#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4718#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4719#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4720#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4721#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4722
4723#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4724#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4725#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4726#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4727#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4728
4729#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4730#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4731#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4732#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4733#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4734
4735#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4736#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4737#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4738#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4739#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4740
4741#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4742#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4743#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4744
4745/******************* Bit definition for FSMC_BTR3 register *******************/
4746#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4747#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4748#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4749#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4750#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4751
4752#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4753#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4754#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4755#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4756#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4757
4758#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4759#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4760#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4761#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4762#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4763
4764#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4765#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4766#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4767#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4768#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4769
4770#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4771#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4772#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4773#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4774#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4775
4776#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4777#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4778#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4779#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4780#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4781
4782#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4783#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4784#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4785
4786/****************** Bit definition for FSMC_BTR4 register *******************/
4787#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4788#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4789#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4790#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4791#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4792
4793#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4794#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4795#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4796#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4797#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4798
4799#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4800#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4801#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4802#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4803#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4804
4805#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4806#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4807#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4808#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4809#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4810
4811#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4812#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4813#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4814#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4815#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4816
4817#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4818#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4819#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4820#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4821#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4822
4823#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4824#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4825#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4826
4827/****************** Bit definition for FSMC_BWTR1 register ******************/
4828#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4829#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4830#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4831#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4832#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4833
4834#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4835#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4836#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4837#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4838#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4839
4840#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4841#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4842#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4843#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4844#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4845
4846#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4847#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4848#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4849#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4850#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4851
4852#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4853#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4854#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4855#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4856#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4857
4858#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4859#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4860#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4861
4862/****************** Bit definition for FSMC_BWTR2 register ******************/
4863#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4864#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4865#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4866#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4867#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4868
4869#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4870#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4871#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4872#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4873#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4874
4875#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4876#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4877#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4878#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4879#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4880
4881#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4882#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4883#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
4884#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4885#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4886
4887#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4888#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4889#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4890#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4891#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4892
4893#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4894#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4895#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4896
4897/****************** Bit definition for FSMC_BWTR3 register ******************/
4898#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4899#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4900#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4901#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4902#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4903
4904#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4905#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4906#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4907#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4908#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4909
4910#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4911#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4912#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4913#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4914#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4915
4916#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4917#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4918#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4919#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4920#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4921
4922#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4923#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4924#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4925#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4926#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4927
4928#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4929#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4930#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4931
4932/****************** Bit definition for FSMC_BWTR4 register ******************/
4933#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4934#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4935#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4936#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4937#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4938
4939#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4940#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4941#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4942#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4943#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4944
4945#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4946#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4947#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4948#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4949#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4950
4951#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4952#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4953#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4954#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4955#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4956
4957#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4958#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4959#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4960#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4961#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4962
4963#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4964#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4965#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4966
4967/****************** Bit definition for FSMC_PCR2 register *******************/
4968#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
4969#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
4970#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
4971
4972#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
4973#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4974#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4975
4976#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
4977
4978#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
4979#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4980#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4981#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
4982#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
4983
4984#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
4985#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
4986#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
4987#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
4988#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
4989
4990#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
4991#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
4992#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
4993#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
4994
4995/****************** Bit definition for FSMC_PCR3 register *******************/
4996#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
4997#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
4998#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
4999
5000#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
5001#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5002#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5003
5004#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
5005
5006#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
5007#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
5008#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
5009#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
5010#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
5011
5012#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
5013#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
5014#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
5015#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
5016#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
5017
5018#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
5019#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
5020#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
5021#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
5022
5023/****************** Bit definition for FSMC_PCR4 register *******************/
5024#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
5025#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
5026#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
5027
5028#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
5029#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5030#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5031
5032#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
5033
5034#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
5035#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
5036#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
5037#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
5038#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
5039
5040#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
5041#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
5042#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
5043#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
5044#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
5045
5046#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
5047#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
5048#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
5049#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
5050
5051/******************* Bit definition for FSMC_SR2 register *******************/
5052#define FSMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
5053#define FSMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
5054#define FSMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
5055#define FSMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
5056#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
5057#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
5058#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
5059
5060/******************* Bit definition for FSMC_SR3 register *******************/
5061#define FSMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
5062#define FSMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
5063#define FSMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
5064#define FSMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
5065#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
5066#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
5067#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
5068
5069/******************* Bit definition for FSMC_SR4 register *******************/
5070#define FSMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
5071#define FSMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
5072#define FSMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
5073#define FSMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
5074#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
5075#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
5076#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
5077
5078/****************** Bit definition for FSMC_PMEM2 register ******************/
5079#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
5080#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5081#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5082#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5083#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5084#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5085#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
5086#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
5087#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
5088
5089#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
5090#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5091#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5092#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5093#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5094#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5095#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5096#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5097#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5098
5099#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
5100#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5101#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5102#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5103#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5104#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
5105#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
5106#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
5107#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
5108
5109#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
5110#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5111#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5112#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5113#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5114#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
5115#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
5116#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
5117#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
5118
5119/****************** Bit definition for FSMC_PMEM3 register ******************/
5120#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
5121#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5122#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5123#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5124#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5125#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5126#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
5127#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
5128#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
5129
5130#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
5131#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5132#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5133#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5134#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5135#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5136#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5137#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5138#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5139
5140#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
5141#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5142#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5143#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5144#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5145#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
5146#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
5147#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
5148#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
5149
5150#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
5151#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5152#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5153#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5154#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5155#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
5156#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
5157#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
5158#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
5159
5160/****************** Bit definition for FSMC_PMEM4 register ******************/
5161#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
5162#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5163#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5164#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5165#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5166#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5167#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
5168#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
5169#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
5170
5171#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
5172#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5173#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5174#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5175#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5176#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5177#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5178#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5179#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5180
5181#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
5182#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5183#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5184#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5185#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5186#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
5187#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
5188#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
5189#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
5190
5191#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
5192#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5193#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5194#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5195#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5196#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
5197#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
5198#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
5199#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
5200
5201/****************** Bit definition for FSMC_PATT2 register ******************/
5202#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
5203#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5204#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5205#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5206#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5207#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5208#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
5209#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
5210#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
5211
5212#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
5213#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5214#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5215#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5216#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5217#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5218#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5219#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5220#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5221
5222#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
5223#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5224#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5225#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5226#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5227#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
5228#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
5229#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
5230#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
5231
5232#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
5233#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5234#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5235#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5236#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5237#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
5238#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
5239#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
5240#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
5241
5242/****************** Bit definition for FSMC_PATT3 register ******************/
5243#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
5244#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5245#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5246#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5247#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5248#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5249#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
5250#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
5251#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
5252
5253#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
5254#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5255#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5256#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5257#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5258#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5259#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5260#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5261#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5262
5263#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
5264#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5265#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5266#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5267#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5268#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
5269#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
5270#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
5271#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
5272
5273#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
5274#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5275#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5276#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5277#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5278#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
5279#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
5280#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
5281#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
5282
5283/****************** Bit definition for FSMC_PATT4 register ******************/
5284#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
5285#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5286#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5287#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5288#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5289#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5290#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
5291#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
5292#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
5293
5294#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
5295#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5296#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5297#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5298#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5299#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5300#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5301#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5302#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5303
5304#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
5305#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5306#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5307#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5308#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5309#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
5310#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
5311#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
5312#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
5313
5314#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
5315#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5316#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5317#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5318#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5319#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
5320#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
5321#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
5322#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
5323
5324/****************** Bit definition for FSMC_PIO4 register *******************/
5325#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
5326#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5327#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5328#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5329#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5330#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5331#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
5332#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
5333#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
5334
5335#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
5336#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5337#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5338#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5339#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5340#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5341#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5342#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5343#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5344
5345#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
5346#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5347#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5348#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5349#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5350#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
5351#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
5352#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
5353#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
5354
5355#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
5356#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5357#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5358#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5359#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5360#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
5361#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
5362#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
5363#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
5364
5365/****************** Bit definition for FSMC_ECCR2 register ******************/
5366#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
5367
5368/****************** Bit definition for FSMC_ECCR3 register ******************/
5369#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
5370
5371/******************************************************************************/
5372/* */
5373/* SD host Interface */
5374/* */
5375/******************************************************************************/
5376
5377/****************** Bit definition for SDIO_POWER register ******************/
5378#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
5379#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!<Bit 0 */
5380#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!<Bit 1 */
5381
5382/****************** Bit definition for SDIO_CLKCR register ******************/
5383#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!<Clock divide factor */
5384#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!<Clock enable bit */
5385#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!<Power saving configuration bit */
5386#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!<Clock divider bypass enable bit */
5387
5388#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
5389#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!<Bit 0 */
5390#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!<Bit 1 */
5391
5392#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!<SDIO_CK dephasing selection bit */
5393#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!<HW Flow Control enable */
5394
5395/******************* Bit definition for SDIO_ARG register *******************/
5396#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
5397
5398/******************* Bit definition for SDIO_CMD register *******************/
5399#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!<Command Index */
5400
5401#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
5402#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */
5403#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */
5404
5405#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!<CPSM Waits for Interrupt Request */
5406#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
5407#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
5408#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!<SD I/O suspend command */
5409#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!<Enable CMD completion */
5410#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!<Not Interrupt Enable */
5411#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!<CE-ATA command */
5412
5413/***************** Bit definition for SDIO_RESPCMD register *****************/
5414#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!<Response command index */
5415
5416/****************** Bit definition for SDIO_RESP0 register ******************/
5417#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5418
5419/****************** Bit definition for SDIO_RESP1 register ******************/
5420#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5421
5422/****************** Bit definition for SDIO_RESP2 register ******************/
5423#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5424
5425/****************** Bit definition for SDIO_RESP3 register ******************/
5426#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5427
5428/****************** Bit definition for SDIO_RESP4 register ******************/
5429#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5430
5431/****************** Bit definition for SDIO_DTIMER register *****************/
5432#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
5433
5434/****************** Bit definition for SDIO_DLEN register *******************/
5435#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
5436
5437/****************** Bit definition for SDIO_DCTRL register ******************/
5438#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!<Data transfer enabled bit */
5439#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!<Data transfer direction selection */
5440#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!<Data transfer mode selection */
5441#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!<DMA enabled bit */
5442
5443#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
5444#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!<Bit 0 */
5445#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!<Bit 1 */
5446#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!<Bit 2 */
5447#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!<Bit 3 */
5448
5449#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!<Read wait start */
5450#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!<Read wait stop */
5451#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!<Read wait mode */
5452#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!<SD I/O enable functions */
5453
5454/****************** Bit definition for SDIO_DCOUNT register *****************/
5455#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
5456
5457/****************** Bit definition for SDIO_STA register ********************/
5458#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
5459#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
5460#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
5461#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
5462#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
5463#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
5464#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
5465#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
5466#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
5467#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
5468#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
5469#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
5470#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
5471#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
5472#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
5473#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
5474#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
5475#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
5476#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
5477#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
5478#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
5479#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
5480#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
5481#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
5482
5483/******************* Bit definition for SDIO_ICR register *******************/
5484#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
5485#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
5486#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
5487#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
5488#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
5489#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
5490#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
5491#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
5492#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
5493#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
5494#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
5495#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
5496#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
5497
5498/****************** Bit definition for SDIO_MASK register *******************/
5499#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
5500#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
5501#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
5502#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
5503#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
5504#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
5505#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
5506#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
5507#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
5508#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
5509#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
5510#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
5511#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
5512#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
5513#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
5514#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
5515#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
5516#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
5517#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
5518#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
5519#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
5520#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
5521#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
5522#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
5523
5524/***************** Bit definition for SDIO_FIFOCNT register *****************/
5525#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
5526
5527/****************** Bit definition for SDIO_FIFO register *******************/
5528#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
5529
5530/******************************************************************************/
5531/* */
5532/* USB Device FS */
5533/* */
5534/******************************************************************************/
5535
5536/*!<Endpoint-specific registers */
5537/******************* Bit definition for USB_EP0R register *******************/
5538#define USB_EP0R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
5539
5540#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5541#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
5542#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
5543
5544#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
5545#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
5546#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
5547
5548#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
5549#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
5550#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
5551
5552#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
5553
5554#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
5555#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
5556#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
5557
5558#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
5559#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
5560
5561/******************* Bit definition for USB_EP1R register *******************/
5562#define USB_EP1R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
5563
5564#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5565#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
5566#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
5567
5568#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
5569#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
5570#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
5571
5572#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
5573#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
5574#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
5575
5576#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
5577
5578#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
5579#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
5580#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
5581
5582#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
5583#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
5584
5585/******************* Bit definition for USB_EP2R register *******************/
5586#define USB_EP2R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
5587
5588#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5589#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
5590#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
5591
5592#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
5593#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
5594#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
5595
5596#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
5597#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
5598#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
5599
5600#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
5601
5602#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
5603#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
5604#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
5605
5606#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
5607#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
5608
5609/******************* Bit definition for USB_EP3R register *******************/
5610#define USB_EP3R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
5611
5612#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5613#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
5614#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
5615
5616#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
5617#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
5618#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
5619
5620#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
5621#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
5622#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
5623
5624#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
5625
5626#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
5627#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
5628#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
5629
5630#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
5631#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
5632
5633/******************* Bit definition for USB_EP4R register *******************/
5634#define USB_EP4R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
5635
5636#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5637#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
5638#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
5639
5640#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
5641#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
5642#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
5643
5644#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
5645#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
5646#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
5647
5648#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
5649
5650#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
5651#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
5652#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
5653
5654#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
5655#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
5656
5657/******************* Bit definition for USB_EP5R register *******************/
5658#define USB_EP5R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
5659
5660#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5661#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
5662#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
5663
5664#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
5665#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
5666#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
5667
5668#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
5669#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
5670#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
5671
5672#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
5673
5674#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
5675#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
5676#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
5677
5678#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
5679#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
5680
5681/******************* Bit definition for USB_EP6R register *******************/
5682#define USB_EP6R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
5683
5684#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5685#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
5686#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
5687
5688#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
5689#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
5690#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
5691
5692#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
5693#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
5694#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
5695
5696#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
5697
5698#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
5699#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
5700#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
5701
5702#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
5703#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
5704
5705/******************* Bit definition for USB_EP7R register *******************/
5706#define USB_EP7R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
5707
5708#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5709#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
5710#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
5711
5712#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
5713#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
5714#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
5715
5716#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
5717#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
5718#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
5719
5720#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
5721
5722#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
5723#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
5724#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
5725
5726#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
5727#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
5728
5729/*!<Common registers */
5730/******************* Bit definition for USB_CNTR register *******************/
5731#define USB_CNTR_FRES ((uint16_t)0x0001) /*!<Force USB Reset */
5732#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!<Power down */
5733#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!<Low-power mode */
5734#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!<Force suspend */
5735#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!<Resume request */
5736#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!<Expected Start Of Frame Interrupt Mask */
5737#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!<Start Of Frame Interrupt Mask */
5738#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!<RESET Interrupt Mask */
5739#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!<Suspend mode Interrupt Mask */
5740#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!<Wakeup Interrupt Mask */
5741#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!<Error Interrupt Mask */
5742#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun Interrupt Mask */
5743#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!<Correct Transfer Interrupt Mask */
5744
5745/******************* Bit definition for USB_ISTR register *******************/
5746#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!<Endpoint Identifier */
5747#define USB_ISTR_DIR ((uint16_t)0x0010) /*!<Direction of transaction */
5748#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!<Expected Start Of Frame */
5749#define USB_ISTR_SOF ((uint16_t)0x0200) /*!<Start Of Frame */
5750#define USB_ISTR_RESET ((uint16_t)0x0400) /*!<USB RESET request */
5751#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!<Suspend mode request */
5752#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!<Wake up */
5753#define USB_ISTR_ERR ((uint16_t)0x2000) /*!<Error */
5754#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun */
5755#define USB_ISTR_CTR ((uint16_t)0x8000) /*!<Correct Transfer */
5756
5757/******************* Bit definition for USB_FNR register ********************/
5758#define USB_FNR_FN ((uint16_t)0x07FF) /*!<Frame Number */
5759#define USB_FNR_LSOF ((uint16_t)0x1800) /*!<Lost SOF */
5760#define USB_FNR_LCK ((uint16_t)0x2000) /*!<Locked */
5761#define USB_FNR_RXDM ((uint16_t)0x4000) /*!<Receive Data - Line Status */
5762#define USB_FNR_RXDP ((uint16_t)0x8000) /*!<Receive Data + Line Status */
5763
5764/****************** Bit definition for USB_DADDR register *******************/
5765#define USB_DADDR_ADD ((uint8_t)0x7F) /*!<ADD[6:0] bits (Device Address) */
5766#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!<Bit 0 */
5767#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!<Bit 1 */
5768#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!<Bit 2 */
5769#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!<Bit 3 */
5770#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!<Bit 4 */
5771#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!<Bit 5 */
5772#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!<Bit 6 */
5773
5774#define USB_DADDR_EF ((uint8_t)0x80) /*!<Enable Function */
5775
5776/****************** Bit definition for USB_BTABLE register ******************/
5777#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!<Buffer Table */
5778
5779/*!<Buffer descriptor table */
5780/***************** Bit definition for USB_ADDR0_TX register *****************/
5781#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 0 */
5782
5783/***************** Bit definition for USB_ADDR1_TX register *****************/
5784#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 1 */
5785
5786/***************** Bit definition for USB_ADDR2_TX register *****************/
5787#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 2 */
5788
5789/***************** Bit definition for USB_ADDR3_TX register *****************/
5790#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 3 */
5791
5792/***************** Bit definition for USB_ADDR4_TX register *****************/
5793#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 4 */
5794
5795/***************** Bit definition for USB_ADDR5_TX register *****************/
5796#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 5 */
5797
5798/***************** Bit definition for USB_ADDR6_TX register *****************/
5799#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 6 */
5800
5801/***************** Bit definition for USB_ADDR7_TX register *****************/
5802#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!<Transmission Buffer Address 7 */
5803
5804/*----------------------------------------------------------------------------*/
5805
5806/***************** Bit definition for USB_COUNT0_TX register ****************/
5807#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 0 */
5808
5809/***************** Bit definition for USB_COUNT1_TX register ****************/
5810#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 1 */
5811
5812/***************** Bit definition for USB_COUNT2_TX register ****************/
5813#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 2 */
5814
5815/***************** Bit definition for USB_COUNT3_TX register ****************/
5816#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 3 */
5817
5818/***************** Bit definition for USB_COUNT4_TX register ****************/
5819#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 4 */
5820
5821/***************** Bit definition for USB_COUNT5_TX register ****************/
5822#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 5 */
5823
5824/***************** Bit definition for USB_COUNT6_TX register ****************/
5825#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 6 */
5826
5827/***************** Bit definition for USB_COUNT7_TX register ****************/
5828#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!<Transmission Byte Count 7 */
5829
5830/*----------------------------------------------------------------------------*/
5831
5832/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
5833#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 0 (low) */
5834
5835/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
5836#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 0 (high) */
5837
5838/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
5839#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 1 (low) */
5840
5841/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
5842#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 1 (high) */
5843
5844/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
5845#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 2 (low) */
5846
5847/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
5848#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 2 (high) */
5849
5850/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
5851#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!<Transmission Byte Count 3 (low) */
5852
5853/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
5854#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!<Transmission Byte Count 3 (high) */
5855
5856/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
5857#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 4 (low) */
5858
5859/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
5860#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 4 (high) */
5861
5862/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
5863#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 5 (low) */
5864
5865/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
5866#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 5 (high) */
5867
5868/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
5869#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 6 (low) */
5870
5871/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
5872#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 6 (high) */
5873
5874/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
5875#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!<Transmission Byte Count 7 (low) */
5876
5877/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
5878#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!<Transmission Byte Count 7 (high) */
5879
5880/*----------------------------------------------------------------------------*/
5881
5882/***************** Bit definition for USB_ADDR0_RX register *****************/
5883#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 0 */
5884
5885/***************** Bit definition for USB_ADDR1_RX register *****************/
5886#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 1 */
5887
5888/***************** Bit definition for USB_ADDR2_RX register *****************/
5889#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 2 */
5890
5891/***************** Bit definition for USB_ADDR3_RX register *****************/
5892#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 3 */
5893
5894/***************** Bit definition for USB_ADDR4_RX register *****************/
5895#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 4 */
5896
5897/***************** Bit definition for USB_ADDR5_RX register *****************/
5898#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 5 */
5899
5900/***************** Bit definition for USB_ADDR6_RX register *****************/
5901#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 6 */
5902
5903/***************** Bit definition for USB_ADDR7_RX register *****************/
5904#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!<Reception Buffer Address 7 */
5905
5906/*----------------------------------------------------------------------------*/
5907
5908/***************** Bit definition for USB_COUNT0_RX register ****************/
5909#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
5910
5911#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
5912#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
5913#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
5914#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
5915#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
5916#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
5917
5918#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
5919
5920/***************** Bit definition for USB_COUNT1_RX register ****************/
5921#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
5922
5923#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
5924#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
5925#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
5926#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
5927#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
5928#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
5929
5930#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
5931
5932/***************** Bit definition for USB_COUNT2_RX register ****************/
5933#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
5934
5935#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
5936#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
5937#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
5938#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
5939#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
5940#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
5941
5942#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
5943
5944/***************** Bit definition for USB_COUNT3_RX register ****************/
5945#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
5946
5947#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
5948#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
5949#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
5950#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
5951#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
5952#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
5953
5954#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
5955
5956/***************** Bit definition for USB_COUNT4_RX register ****************/
5957#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
5958
5959#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
5960#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
5961#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
5962#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
5963#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
5964#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
5965
5966#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
5967
5968/***************** Bit definition for USB_COUNT5_RX register ****************/
5969#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
5970
5971#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
5972#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
5973#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
5974#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
5975#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
5976#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
5977
5978#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
5979
5980/***************** Bit definition for USB_COUNT6_RX register ****************/
5981#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
5982
5983#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
5984#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
5985#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
5986#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
5987#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
5988#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
5989
5990#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
5991
5992/***************** Bit definition for USB_COUNT7_RX register ****************/
5993#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!<Reception Byte Count */
5994
5995#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!<NUM_BLOCK[4:0] bits (Number of blocks) */
5996#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!<Bit 0 */
5997#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!<Bit 1 */
5998#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!<Bit 2 */
5999#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!<Bit 3 */
6000#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!<Bit 4 */
6001
6002#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!<BLock SIZE */
6003
6004/*----------------------------------------------------------------------------*/
6005
6006/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
6007#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
6008
6009#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6010#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
6011#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
6012#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
6013#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
6014#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
6015
6016#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
6017
6018/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
6019#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
6020
6021#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6022#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 1 */
6023#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
6024#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
6025#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
6026#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
6027
6028#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
6029
6030/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
6031#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
6032
6033#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6034#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
6035#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
6036#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
6037#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
6038#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
6039
6040#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
6041
6042/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
6043#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
6044
6045#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6046#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
6047#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
6048#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
6049#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
6050#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
6051
6052#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
6053
6054/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
6055#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
6056
6057#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6058#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
6059#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
6060#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
6061#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
6062#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
6063
6064#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
6065
6066/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
6067#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
6068
6069#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6070#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
6071#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
6072#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
6073#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
6074#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
6075
6076#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
6077
6078/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
6079#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
6080
6081#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6082#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
6083#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
6084#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
6085#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
6086#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
6087
6088#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
6089
6090/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
6091#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
6092
6093#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6094#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
6095#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
6096#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
6097#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
6098#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
6099
6100#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
6101
6102/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
6103#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
6104
6105#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6106#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
6107#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
6108#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
6109#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
6110#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
6111
6112#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
6113
6114/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
6115#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
6116
6117#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6118#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
6119#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
6120#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
6121#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
6122#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
6123
6124#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
6125
6126/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
6127#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
6128
6129#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6130#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
6131#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
6132#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
6133#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
6134#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
6135
6136#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
6137
6138/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
6139#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
6140
6141#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6142#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
6143#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
6144#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
6145#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
6146#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
6147
6148#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
6149
6150/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
6151#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
6152
6153#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6154#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
6155#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
6156#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
6157#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
6158#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
6159
6160#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
6161
6162/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
6163#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
6164
6165#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6166#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
6167#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
6168#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
6169#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
6170#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
6171
6172#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
6173
6174/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
6175#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!<Reception Byte Count (low) */
6176
6177#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!<NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
6178#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!<Bit 0 */
6179#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!<Bit 1 */
6180#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!<Bit 2 */
6181#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!<Bit 3 */
6182#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!<Bit 4 */
6183
6184#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!<BLock SIZE (low) */
6185
6186/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
6187#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!<Reception Byte Count (high) */
6188
6189#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!<NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
6190#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!<Bit 0 */
6191#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!<Bit 1 */
6192#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!<Bit 2 */
6193#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!<Bit 3 */
6194#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!<Bit 4 */
6195
6196#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!<BLock SIZE (high) */
6197
6198/******************************************************************************/
6199/* */
6200/* Controller Area Network */
6201/* */
6202/******************************************************************************/
6203
6204/*!<CAN control and status registers */
6205/******************* Bit definition for CAN_MCR register ********************/
6206#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */
6207#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */
6208#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */
6209#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */
6210#define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */
6211#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */
6212#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */
6213#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */
6214#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */
6215
6216/******************* Bit definition for CAN_MSR register ********************/
6217#define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */
6218#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */
6219#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */
6220#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */
6221#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */
6222#define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */
6223#define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */
6224#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */
6225#define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */
6226
6227/******************* Bit definition for CAN_TSR register ********************/
6228#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
6229#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
6230#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
6231#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
6232#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
6233#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
6234#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
6235#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
6236#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
6237#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
6238#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
6239#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
6240#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
6241#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
6242#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
6243#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
6244
6245#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
6246#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
6247#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
6248#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
6249
6250#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
6251#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
6252#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
6253#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
6254
6255/******************* Bit definition for CAN_RF0R register *******************/
6256#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */
6257#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */
6258#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */
6259#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */
6260
6261/******************* Bit definition for CAN_RF1R register *******************/
6262#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */
6263#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */
6264#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */
6265#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */
6266
6267/******************** Bit definition for CAN_IER register *******************/
6268#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
6269#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
6270#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
6271#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
6272#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
6273#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
6274#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
6275#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
6276#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
6277#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
6278#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
6279#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
6280#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
6281#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
6282
6283/******************** Bit definition for CAN_ESR register *******************/
6284#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
6285#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
6286#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
6287
6288#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
6289#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
6290#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
6291#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
6292
6293#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
6294#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
6295
6296/******************* Bit definition for CAN_BTR register ********************/
6297#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
6298#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
6299#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
6300#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
6301#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
6302#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
6303
6304/*!<Mailbox registers */
6305/****************** Bit definition for CAN_TI0R register ********************/
6306#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
6307#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
6308#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
6309#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
6310#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
6311
6312/****************** Bit definition for CAN_TDT0R register *******************/
6313#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
6314#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
6315#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
6316
6317/****************** Bit definition for CAN_TDL0R register *******************/
6318#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
6319#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
6320#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
6321#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
6322
6323/****************** Bit definition for CAN_TDH0R register *******************/
6324#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
6325#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
6326#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
6327#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
6328
6329/******************* Bit definition for CAN_TI1R register *******************/
6330#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
6331#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
6332#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
6333#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
6334#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
6335
6336/******************* Bit definition for CAN_TDT1R register ******************/
6337#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
6338#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
6339#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
6340
6341/******************* Bit definition for CAN_TDL1R register ******************/
6342#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
6343#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
6344#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
6345#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
6346
6347/******************* Bit definition for CAN_TDH1R register ******************/
6348#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
6349#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
6350#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
6351#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
6352
6353/******************* Bit definition for CAN_TI2R register *******************/
6354#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
6355#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
6356#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
6357#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
6358#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
6359
6360/******************* Bit definition for CAN_TDT2R register ******************/
6361#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
6362#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
6363#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
6364
6365/******************* Bit definition for CAN_TDL2R register ******************/
6366#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
6367#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
6368#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
6369#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
6370
6371/******************* Bit definition for CAN_TDH2R register ******************/
6372#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
6373#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
6374#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
6375#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
6376
6377/******************* Bit definition for CAN_RI0R register *******************/
6378#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
6379#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
6380#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
6381#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
6382
6383/******************* Bit definition for CAN_RDT0R register ******************/
6384#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
6385#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
6386#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
6387
6388/******************* Bit definition for CAN_RDL0R register ******************/
6389#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
6390#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
6391#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
6392#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
6393
6394/******************* Bit definition for CAN_RDH0R register ******************/
6395#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
6396#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
6397#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
6398#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
6399
6400/******************* Bit definition for CAN_RI1R register *******************/
6401#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
6402#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
6403#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
6404#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
6405
6406/******************* Bit definition for CAN_RDT1R register ******************/
6407#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
6408#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
6409#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
6410
6411/******************* Bit definition for CAN_RDL1R register ******************/
6412#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
6413#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
6414#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
6415#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
6416
6417/******************* Bit definition for CAN_RDH1R register ******************/
6418#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
6419#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
6420#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
6421#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
6422
6423/*!<CAN filter registers */
6424/******************* Bit definition for CAN_FMR register ********************/
6425#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
6426
6427/******************* Bit definition for CAN_FM1R register *******************/
6428#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */
6429#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */
6430#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */
6431#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */
6432#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */
6433#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */
6434#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */
6435#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */
6436#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */
6437#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */
6438#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */
6439#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */
6440#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */
6441#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */
6442#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */
6443
6444/******************* Bit definition for CAN_FS1R register *******************/
6445#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */
6446#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */
6447#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */
6448#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */
6449#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */
6450#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */
6451#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */
6452#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */
6453#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */
6454#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */
6455#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */
6456#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */
6457#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */
6458#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */
6459#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */
6460
6461/****************** Bit definition for CAN_FFA1R register *******************/
6462#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */
6463#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
6464#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
6465#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
6466#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
6467#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
6468#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
6469#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
6470#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
6471#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
6472#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
6473#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
6474#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
6475#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
6476#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
6477
6478/******************* Bit definition for CAN_FA1R register *******************/
6479#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */
6480#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */
6481#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */
6482#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */
6483#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */
6484#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */
6485#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */
6486#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */
6487#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */
6488#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */
6489#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */
6490#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */
6491#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */
6492#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */
6493#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */
6494
6495/******************* Bit definition for CAN_F0R1 register *******************/
6496#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6497#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6498#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6499#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6500#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6501#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6502#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6503#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6504#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6505#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6506#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6507#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6508#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6509#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6510#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6511#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6512#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6513#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6514#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6515#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6516#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6517#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6518#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6519#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6520#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6521#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6522#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6523#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6524#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6525#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6526#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6527#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6528
6529/******************* Bit definition for CAN_F1R1 register *******************/
6530#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6531#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6532#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6533#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6534#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6535#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6536#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6537#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6538#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6539#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6540#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6541#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6542#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6543#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6544#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6545#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6546#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6547#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6548#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6549#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6550#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6551#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6552#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6553#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6554#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6555#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6556#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6557#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6558#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6559#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6560#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6561#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6562
6563/******************* Bit definition for CAN_F2R1 register *******************/
6564#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6565#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6566#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6567#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6568#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6569#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6570#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6571#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6572#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6573#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6574#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6575#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6576#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6577#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6578#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6579#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6580#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6581#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6582#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6583#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6584#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6585#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6586#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6587#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6588#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6589#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6590#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6591#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6592#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6593#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6594#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6595#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6596
6597/******************* Bit definition for CAN_F3R1 register *******************/
6598#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6599#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6600#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6601#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6602#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6603#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6604#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6605#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6606#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6607#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6608#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6609#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6610#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6611#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6612#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6613#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6614#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6615#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6616#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6617#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6618#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6619#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6620#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6621#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6622#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6623#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6624#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6625#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6626#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6627#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6628#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6629#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6630
6631/******************* Bit definition for CAN_F4R1 register *******************/
6632#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6633#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6634#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6635#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6636#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6637#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6638#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6639#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6640#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6641#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6642#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6643#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6644#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6645#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6646#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6647#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6648#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6649#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6650#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6651#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6652#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6653#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6654#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6655#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6656#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6657#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6658#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6659#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6660#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6661#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6662#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6663#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6664
6665/******************* Bit definition for CAN_F5R1 register *******************/
6666#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6667#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6668#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6669#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6670#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6671#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6672#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6673#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6674#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6675#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6676#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6677#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6678#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6679#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6680#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6681#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6682#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6683#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6684#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6685#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6686#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6687#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6688#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6689#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6690#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6691#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6692#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6693#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6694#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6695#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6696#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6697#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6698
6699/******************* Bit definition for CAN_F6R1 register *******************/
6700#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6701#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6702#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6703#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6704#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6705#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6706#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6707#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6708#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6709#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6710#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6711#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6712#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6713#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6714#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6715#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6716#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6717#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6718#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6719#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6720#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6721#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6722#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6723#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6724#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6725#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6726#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6727#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6728#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6729#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6730#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6731#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6732
6733/******************* Bit definition for CAN_F7R1 register *******************/
6734#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6735#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6736#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6737#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6738#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6739#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6740#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6741#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6742#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6743#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6744#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6745#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6746#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6747#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6748#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6749#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6750#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6751#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6752#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6753#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6754#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6755#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6756#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6757#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6758#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6759#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6760#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6761#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6762#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6763#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6764#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6765#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6766
6767/******************* Bit definition for CAN_F8R1 register *******************/
6768#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6769#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6770#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6771#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6772#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6773#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6774#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6775#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6776#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6777#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6778#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6779#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6780#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6781#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6782#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6783#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6784#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6785#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6786#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6787#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6788#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6789#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6790#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6791#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6792#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6793#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6794#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6795#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6796#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6797#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6798#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6799#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6800
6801/******************* Bit definition for CAN_F9R1 register *******************/
6802#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6803#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6804#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6805#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6806#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6807#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6808#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6809#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6810#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6811#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6812#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6813#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6814#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6815#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6816#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6817#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6818#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6819#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6820#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6821#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6822#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6823#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6824#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6825#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6826#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6827#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6828#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6829#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6830#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6831#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6832#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6833#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6834
6835/******************* Bit definition for CAN_F10R1 register ******************/
6836#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6837#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6838#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6839#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6840#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6841#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6842#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6843#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6844#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6845#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6846#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6847#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6848#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6849#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6850#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6851#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6852#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6853#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6854#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6855#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6856#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6857#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6858#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6859#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6860#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6861#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6862#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6863#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6864#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6865#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6866#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6867#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6868
6869/******************* Bit definition for CAN_F11R1 register ******************/
6870#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6871#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6872#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6873#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6874#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6875#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6876#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6877#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6878#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6879#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6880#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6881#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6882#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6883#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6884#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6885#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6886#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6887#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6888#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6889#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6890#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6891#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6892#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6893#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6894#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6895#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6896#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6897#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6898#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6899#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6900#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6901#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6902
6903/******************* Bit definition for CAN_F12R1 register ******************/
6904#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6905#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6906#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6907#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6908#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6909#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6910#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6911#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6912#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6913#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6914#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6915#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6916#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6917#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6918#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6919#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6920#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6921#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6922#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6923#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6924#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6925#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6926#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6927#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6928#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6929#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6930#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6931#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6932#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6933#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6934#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6935#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6936
6937/******************* Bit definition for CAN_F13R1 register ******************/
6938#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6939#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6940#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6941#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6942#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6943#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6944#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6945#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6946#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6947#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6948#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6949#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6950#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6951#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6952#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6953#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6954#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6955#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6956#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6957#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6958#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6959#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6960#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6961#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6962#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6963#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6964#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6965#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
6966#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
6967#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
6968#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
6969#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
6970
6971/******************* Bit definition for CAN_F0R2 register *******************/
6972#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
6973#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
6974#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
6975#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
6976#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
6977#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
6978#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
6979#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
6980#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
6981#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
6982#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
6983#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
6984#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
6985#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
6986#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
6987#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
6988#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
6989#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
6990#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
6991#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
6992#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
6993#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
6994#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
6995#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
6996#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
6997#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
6998#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
6999#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
7000#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
7001#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
7002#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
7003#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
7004
7005/******************* Bit definition for CAN_F1R2 register *******************/
7006#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
7007#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
7008#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
7009#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
7010#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
7011#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
7012#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
7013#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
7014#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
7015#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
7016#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
7017#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
7018#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
7019#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
7020#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
7021#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
7022#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
7023#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
7024#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
7025#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
7026#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
7027#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
7028#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
7029#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
7030#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
7031#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
7032#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
7033#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
7034#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
7035#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
7036#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
7037#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
7038
7039/******************* Bit definition for CAN_F2R2 register *******************/
7040#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
7041#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
7042#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
7043#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
7044#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
7045#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
7046#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
7047#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
7048#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
7049#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
7050#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
7051#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
7052#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
7053#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
7054#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
7055#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
7056#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
7057#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
7058#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
7059#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
7060#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
7061#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
7062#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
7063#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
7064#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
7065#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
7066#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
7067#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
7068#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
7069#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
7070#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
7071#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
7072
7073/******************* Bit definition for CAN_F3R2 register *******************/
7074#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
7075#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
7076#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
7077#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
7078#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
7079#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
7080#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
7081#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
7082#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
7083#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
7084#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
7085#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
7086#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
7087#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
7088#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
7089#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
7090#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
7091#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
7092#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
7093#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
7094#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
7095#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
7096#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
7097#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
7098#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
7099#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
7100#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
7101#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
7102#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
7103#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
7104#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
7105#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
7106
7107/******************* Bit definition for CAN_F4R2 register *******************/
7108#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
7109#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
7110#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
7111#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
7112#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
7113#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
7114#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
7115#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
7116#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
7117#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
7118#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
7119#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
7120#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
7121#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
7122#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
7123#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
7124#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
7125#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
7126#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
7127#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
7128#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
7129#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
7130#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
7131#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
7132#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
7133#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
7134#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
7135#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
7136#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
7137#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
7138#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
7139#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
7140
7141/******************* Bit definition for CAN_F5R2 register *******************/
7142#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
7143#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
7144#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
7145#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
7146#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
7147#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
7148#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
7149#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
7150#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
7151#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
7152#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
7153#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
7154#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
7155#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
7156#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
7157#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
7158#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
7159#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
7160#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
7161#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
7162#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
7163#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
7164#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
7165#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
7166#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
7167#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
7168#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
7169#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
7170#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
7171#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
7172#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
7173#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
7174
7175/******************* Bit definition for CAN_F6R2 register *******************/
7176#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
7177#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
7178#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
7179#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
7180#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
7181#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
7182#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
7183#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
7184#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
7185#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
7186#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
7187#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
7188#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
7189#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
7190#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
7191#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
7192#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
7193#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
7194#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
7195#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
7196#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
7197#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
7198#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
7199#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
7200#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
7201#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
7202#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
7203#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
7204#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
7205#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
7206#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
7207#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
7208
7209/******************* Bit definition for CAN_F7R2 register *******************/
7210#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
7211#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
7212#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
7213#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
7214#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
7215#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
7216#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
7217#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
7218#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
7219#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
7220#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
7221#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
7222#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
7223#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
7224#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
7225#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
7226#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
7227#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
7228#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
7229#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
7230#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
7231#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
7232#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
7233#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
7234#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
7235#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
7236#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
7237#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
7238#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
7239#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
7240#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
7241#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
7242
7243/******************* Bit definition for CAN_F8R2 register *******************/
7244#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
7245#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
7246#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
7247#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
7248#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
7249#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
7250#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
7251#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
7252#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
7253#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
7254#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
7255#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
7256#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
7257#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
7258#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
7259#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
7260#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
7261#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
7262#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
7263#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
7264#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
7265#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
7266#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
7267#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
7268#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
7269#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
7270#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
7271#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
7272#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
7273#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
7274#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
7275#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
7276
7277/******************* Bit definition for CAN_F9R2 register *******************/
7278#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
7279#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
7280#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
7281#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
7282#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
7283#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
7284#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
7285#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
7286#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
7287#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
7288#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
7289#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
7290#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
7291#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
7292#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
7293#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
7294#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
7295#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
7296#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
7297#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
7298#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
7299#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
7300#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
7301#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
7302#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
7303#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
7304#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
7305#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
7306#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
7307#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
7308#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
7309#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
7310
7311/******************* Bit definition for CAN_F10R2 register ******************/
7312#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
7313#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
7314#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
7315#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
7316#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
7317#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
7318#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
7319#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
7320#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
7321#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
7322#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
7323#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
7324#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
7325#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
7326#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
7327#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
7328#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
7329#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
7330#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
7331#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
7332#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
7333#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
7334#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
7335#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
7336#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
7337#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
7338#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
7339#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
7340#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
7341#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
7342#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
7343#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
7344
7345/******************* Bit definition for CAN_F11R2 register ******************/
7346#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
7347#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
7348#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
7349#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
7350#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
7351#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
7352#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
7353#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
7354#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
7355#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
7356#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
7357#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
7358#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
7359#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
7360#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
7361#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
7362#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
7363#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
7364#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
7365#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
7366#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
7367#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
7368#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
7369#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
7370#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
7371#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
7372#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
7373#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
7374#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
7375#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
7376#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
7377#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
7378
7379/******************* Bit definition for CAN_F12R2 register ******************/
7380#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
7381#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
7382#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
7383#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
7384#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
7385#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
7386#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
7387#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
7388#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
7389#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
7390#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
7391#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
7392#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
7393#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
7394#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
7395#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
7396#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
7397#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
7398#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
7399#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
7400#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
7401#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
7402#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
7403#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
7404#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
7405#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
7406#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
7407#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
7408#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
7409#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
7410#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
7411#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
7412
7413/******************* Bit definition for CAN_F13R2 register ******************/
7414#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
7415#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
7416#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
7417#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
7418#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
7419#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
7420#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
7421#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
7422#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
7423#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
7424#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
7425#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
7426#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
7427#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
7428#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
7429#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
7430#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
7431#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
7432#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
7433#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
7434#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
7435#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
7436#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
7437#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
7438#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
7439#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
7440#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
7441#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
7442#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
7443#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
7444#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
7445#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
7446
7447/******************************************************************************/
7448/* */
7449/* Serial Peripheral Interface */
7450/* */
7451/******************************************************************************/
7452
7453/******************* Bit definition for SPI_CR1 register ********************/
7454#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!<Clock Phase */
7455#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!<Clock Polarity */
7456#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!<Master Selection */
7457
7458#define SPI_CR1_BR ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */
7459#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!<Bit 0 */
7460#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!<Bit 1 */
7461#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!<Bit 2 */
7462
7463#define SPI_CR1_SPE ((uint16_t)0x0040) /*!<SPI Enable */
7464#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!<Frame Format */
7465#define SPI_CR1_SSI ((uint16_t)0x0100) /*!<Internal slave select */
7466#define SPI_CR1_SSM ((uint16_t)0x0200) /*!<Software slave management */
7467#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!<Receive only */
7468#define SPI_CR1_DFF ((uint16_t)0x0800) /*!<Data Frame Format */
7469#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!<Transmit CRC next */
7470#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!<Hardware CRC calculation enable */
7471#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */
7472#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!<Bidirectional data mode enable */
7473
7474/******************* Bit definition for SPI_CR2 register ********************/
7475#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */
7476#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */
7477#define SPI_CR2_SSOE ((uint8_t)0x04) /*!<SS Output Enable */
7478#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!<Error Interrupt Enable */
7479#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */
7480#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */
7481
7482/******************** Bit definition for SPI_SR register ********************/
7483#define SPI_SR_RXNE ((uint8_t)0x01) /*!<Receive buffer Not Empty */
7484#define SPI_SR_TXE ((uint8_t)0x02) /*!<Transmit buffer Empty */
7485#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!<Channel side */
7486#define SPI_SR_UDR ((uint8_t)0x08) /*!<Underrun flag */
7487#define SPI_SR_CRCERR ((uint8_t)0x10) /*!<CRC Error flag */
7488#define SPI_SR_MODF ((uint8_t)0x20) /*!<Mode fault */
7489#define SPI_SR_OVR ((uint8_t)0x40) /*!<Overrun flag */
7490#define SPI_SR_BSY ((uint8_t)0x80) /*!<Busy flag */
7491
7492/******************** Bit definition for SPI_DR register ********************/
7493#define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */
7494
7495/******************* Bit definition for SPI_CRCPR register ******************/
7496#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!<CRC polynomial register */
7497
7498/****************** Bit definition for SPI_RXCRCR register ******************/
7499#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!<Rx CRC Register */
7500
7501/****************** Bit definition for SPI_TXCRCR register ******************/
7502#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!<Tx CRC Register */
7503
7504/****************** Bit definition for SPI_I2SCFGR register *****************/
7505#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
7506
7507#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
7508#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
7509#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
7510
7511#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
7512
7513#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
7514#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
7515#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
7516
7517#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
7518
7519#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
7520#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
7521#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
7522
7523#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
7524#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
7525
7526/****************** Bit definition for SPI_I2SPR register *******************/
7527#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
7528#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
7529#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
7530
7531/******************************************************************************/
7532/* */
7533/* Inter-integrated Circuit Interface */
7534/* */
7535/******************************************************************************/
7536
7537/******************* Bit definition for I2C_CR1 register ********************/
7538#define I2C_CR1_PE ((uint16_t)0x0001) /*!<Peripheral Enable */
7539#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!<SMBus Mode */
7540#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!<SMBus Type */
7541#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!<ARP Enable */
7542#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!<PEC Enable */
7543#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!<General Call Enable */
7544#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!<Clock Stretching Disable (Slave mode) */
7545#define I2C_CR1_START ((uint16_t)0x0100) /*!<Start Generation */
7546#define I2C_CR1_STOP ((uint16_t)0x0200) /*!<Stop Generation */
7547#define I2C_CR1_ACK ((uint16_t)0x0400) /*!<Acknowledge Enable */
7548#define I2C_CR1_POS ((uint16_t)0x0800) /*!<Acknowledge/PEC Position (for data reception) */
7549#define I2C_CR1_PEC ((uint16_t)0x1000) /*!<Packet Error Checking */
7550#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!<SMBus Alert */
7551#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!<Software Reset */
7552
7553/******************* Bit definition for I2C_CR2 register ********************/
7554#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
7555#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!<Bit 0 */
7556#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!<Bit 1 */
7557#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!<Bit 2 */
7558#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!<Bit 3 */
7559#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!<Bit 4 */
7560#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!<Bit 5 */
7561
7562#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!<Error Interrupt Enable */
7563#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!<Event Interrupt Enable */
7564#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!<Buffer Interrupt Enable */
7565#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!<DMA Requests Enable */
7566#define I2C_CR2_LAST ((uint16_t)0x1000) /*!<DMA Last Transfer */
7567
7568/******************* Bit definition for I2C_OAR1 register *******************/
7569#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!<Interface Address */
7570#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!<Interface Address */
7571
7572#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!<Bit 0 */
7573#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!<Bit 1 */
7574#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!<Bit 2 */
7575#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!<Bit 3 */
7576#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!<Bit 4 */
7577#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!<Bit 5 */
7578#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!<Bit 6 */
7579#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!<Bit 7 */
7580#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!<Bit 8 */
7581#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!<Bit 9 */
7582
7583#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!<Addressing Mode (Slave mode) */
7584
7585/******************* Bit definition for I2C_OAR2 register *******************/
7586#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!<Dual addressing mode enable */
7587#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!<Interface address */
7588
7589/******************** Bit definition for I2C_DR register ********************/
7590#define I2C_DR_DR ((uint8_t)0xFF) /*!<8-bit Data Register */
7591
7592/******************* Bit definition for I2C_SR1 register ********************/
7593#define I2C_SR1_SB ((uint16_t)0x0001) /*!<Start Bit (Master mode) */
7594#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!<Address sent (master mode)/matched (slave mode) */
7595#define I2C_SR1_BTF ((uint16_t)0x0004) /*!<Byte Transfer Finished */
7596#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!<10-bit header sent (Master mode) */
7597#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!<Stop detection (Slave mode) */
7598#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!<Data Register not Empty (receivers) */
7599#define I2C_SR1_TXE ((uint16_t)0x0080) /*!<Data Register Empty (transmitters) */
7600#define I2C_SR1_BERR ((uint16_t)0x0100) /*!<Bus Error */
7601#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!<Arbitration Lost (master mode) */
7602#define I2C_SR1_AF ((uint16_t)0x0400) /*!<Acknowledge Failure */
7603#define I2C_SR1_OVR ((uint16_t)0x0800) /*!<Overrun/Underrun */
7604#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!<PEC Error in reception */
7605#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!<Timeout or Tlow Error */
7606#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!<SMBus Alert */
7607
7608/******************* Bit definition for I2C_SR2 register ********************/
7609#define I2C_SR2_MSL ((uint16_t)0x0001) /*!<Master/Slave */
7610#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!<Bus Busy */
7611#define I2C_SR2_TRA ((uint16_t)0x0004) /*!<Transmitter/Receiver */
7612#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!<General Call Address (Slave mode) */
7613#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!<SMBus Device Default Address (Slave mode) */
7614#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!<SMBus Host Header (Slave mode) */
7615#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!<Dual Flag (Slave mode) */
7616#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!<Packet Error Checking Register */
7617
7618/******************* Bit definition for I2C_CCR register ********************/
7619#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
7620#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!<Fast Mode Duty Cycle */
7621#define I2C_CCR_FS ((uint16_t)0x8000) /*!<I2C Master Mode Selection */
7622
7623/****************** Bit definition for I2C_TRISE register *******************/
7624#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
7625
7626/******************************************************************************/
7627/* */
7628/* Universal Synchronous Asynchronous Receiver Transmitter */
7629/* */
7630/******************************************************************************/
7631
7632/******************* Bit definition for USART_SR register *******************/
7633#define USART_SR_PE ((uint16_t)0x0001) /*!<Parity Error */
7634#define USART_SR_FE ((uint16_t)0x0002) /*!<Framing Error */
7635#define USART_SR_NE ((uint16_t)0x0004) /*!<Noise Error Flag */
7636#define USART_SR_ORE ((uint16_t)0x0008) /*!<OverRun Error */
7637#define USART_SR_IDLE ((uint16_t)0x0010) /*!<IDLE line detected */
7638#define USART_SR_RXNE ((uint16_t)0x0020) /*!<Read Data Register Not Empty */
7639#define USART_SR_TC ((uint16_t)0x0040) /*!<Transmission Complete */
7640#define USART_SR_TXE ((uint16_t)0x0080) /*!<Transmit Data Register Empty */
7641#define USART_SR_LBD ((uint16_t)0x0100) /*!<LIN Break Detection Flag */
7642#define USART_SR_CTS ((uint16_t)0x0200) /*!<CTS Flag */
7643
7644/******************* Bit definition for USART_DR register *******************/
7645#define USART_DR_DR ((uint16_t)0x01FF) /*!<Data value */
7646
7647/****************** Bit definition for USART_BRR register *******************/
7648#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!<Fraction of USARTDIV */
7649#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!<Mantissa of USARTDIV */
7650
7651/****************** Bit definition for USART_CR1 register *******************/
7652#define USART_CR1_SBK ((uint16_t)0x0001) /*!<Send Break */
7653#define USART_CR1_RWU ((uint16_t)0x0002) /*!<Receiver wakeup */
7654#define USART_CR1_RE ((uint16_t)0x0004) /*!<Receiver Enable */
7655#define USART_CR1_TE ((uint16_t)0x0008) /*!<Transmitter Enable */
7656#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!<IDLE Interrupt Enable */
7657#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!<RXNE Interrupt Enable */
7658#define USART_CR1_TCIE ((uint16_t)0x0040) /*!<Transmission Complete Interrupt Enable */
7659#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!<PE Interrupt Enable */
7660#define USART_CR1_PEIE ((uint16_t)0x0100) /*!<PE Interrupt Enable */
7661#define USART_CR1_PS ((uint16_t)0x0200) /*!<Parity Selection */
7662#define USART_CR1_PCE ((uint16_t)0x0400) /*!<Parity Control Enable */
7663#define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */
7664#define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */
7665#define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */
7666#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!<USART Oversmapling 8-bits */
7667
7668/****************** Bit definition for USART_CR2 register *******************/
7669#define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */
7670#define USART_CR2_LBDL ((uint16_t)0x0020) /*!<LIN Break Detection Length */
7671#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
7672#define USART_CR2_LBCL ((uint16_t)0x0100) /*!<Last Bit Clock pulse */
7673#define USART_CR2_CPHA ((uint16_t)0x0200) /*!<Clock Phase */
7674#define USART_CR2_CPOL ((uint16_t)0x0400) /*!<Clock Polarity */
7675#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!<Clock Enable */
7676
7677#define USART_CR2_STOP ((uint16_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
7678#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!<Bit 0 */
7679#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!<Bit 1 */
7680
7681#define USART_CR2_LINEN ((uint16_t)0x4000) /*!<LIN mode enable */
7682
7683/****************** Bit definition for USART_CR3 register *******************/
7684#define USART_CR3_EIE ((uint16_t)0x0001) /*!<Error Interrupt Enable */
7685#define USART_CR3_IREN ((uint16_t)0x0002) /*!<IrDA mode Enable */
7686#define USART_CR3_IRLP ((uint16_t)0x0004) /*!<IrDA Low-Power */
7687#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!<Half-Duplex Selection */
7688#define USART_CR3_NACK ((uint16_t)0x0010) /*!<Smartcard NACK enable */
7689#define USART_CR3_SCEN ((uint16_t)0x0020) /*!<Smartcard mode enable */
7690#define USART_CR3_DMAR ((uint16_t)0x0040) /*!<DMA Enable Receiver */
7691#define USART_CR3_DMAT ((uint16_t)0x0080) /*!<DMA Enable Transmitter */
7692#define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */
7693#define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */
7694#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */
7695#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!<One Bit method */
7696
7697/****************** Bit definition for USART_GTPR register ******************/
7698#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
7699#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!<Bit 0 */
7700#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!<Bit 1 */
7701#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!<Bit 2 */
7702#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!<Bit 3 */
7703#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!<Bit 4 */
7704#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!<Bit 5 */
7705#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!<Bit 6 */
7706#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!<Bit 7 */
7707
7708#define USART_GTPR_GT ((uint16_t)0xFF00) /*!<Guard time value */
7709
7710/******************************************************************************/
7711/* */
7712/* Debug MCU */
7713/* */
7714/******************************************************************************/
7715
7716/**************** Bit definition for DBGMCU_IDCODE register *****************/
7717#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!<Device Identifier */
7718
7719#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!<REV_ID[15:0] bits (Revision Identifier) */
7720#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!<Bit 0 */
7721#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!<Bit 1 */
7722#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!<Bit 2 */
7723#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!<Bit 3 */
7724#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!<Bit 4 */
7725#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!<Bit 5 */
7726#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!<Bit 6 */
7727#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!<Bit 7 */
7728#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!<Bit 8 */
7729#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!<Bit 9 */
7730#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!<Bit 10 */
7731#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!<Bit 11 */
7732#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!<Bit 12 */
7733#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!<Bit 13 */
7734#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!<Bit 14 */
7735#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!<Bit 15 */
7736
7737/****************** Bit definition for DBGMCU_CR register *******************/
7738#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!<Debug Sleep Mode */
7739#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!<Debug Stop Mode */
7740#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!<Debug Standby mode */
7741#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!<Trace Pin Assignment Control */
7742
7743#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!<TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
7744#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!<Bit 0 */
7745#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!<Bit 1 */
7746
7747#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!<Debug Independent Watchdog stopped when Core is halted */
7748#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!<Debug Window Watchdog stopped when Core is halted */
7749#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!<TIM1 counter stopped when core is halted */
7750#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!<TIM2 counter stopped when core is halted */
7751#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!<TIM3 counter stopped when core is halted */
7752#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!<TIM4 counter stopped when core is halted */
7753#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!<Debug CAN1 stopped when Core is halted */
7754#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!<SMBUS timeout mode stopped when Core is halted */
7755#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!<SMBUS timeout mode stopped when Core is halted */
7756#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!<TIM8 counter stopped when core is halted */
7757#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!<TIM5 counter stopped when core is halted */
7758#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!<TIM6 counter stopped when core is halted */
7759#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!<TIM7 counter stopped when core is halted */
7760#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!<Debug CAN2 stopped when Core is halted */
7761#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!<Debug TIM15 stopped when Core is halted */
7762#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!<Debug TIM16 stopped when Core is halted */
7763#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!<Debug TIM17 stopped when Core is halted */
7764#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!<Debug TIM12 stopped when Core is halted */
7765#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!<Debug TIM13 stopped when Core is halted */
7766#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!<Debug TIM14 stopped when Core is halted */
7767#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!<Debug TIM9 stopped when Core is halted */
7768#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!<Debug TIM10 stopped when Core is halted */
7769#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!<Debug TIM11 stopped when Core is halted */
7770
7771/******************************************************************************/
7772/* */
7773/* FLASH and Option Bytes Registers */
7774/* */
7775/******************************************************************************/
7776
7777/******************* Bit definition for FLASH_ACR register ******************/
7778#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!<LATENCY[2:0] bits (Latency) */
7779#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!<Bit 0 */
7780#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!<Bit 0 */
7781#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!<Bit 1 */
7782
7783#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!<Flash Half Cycle Access Enable */
7784#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!<Prefetch Buffer Enable */
7785#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!<Prefetch Buffer Status */
7786
7787/****************** Bit definition for FLASH_KEYR register ******************/
7788#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!<FPEC Key */
7789
7790/***************** Bit definition for FLASH_OPTKEYR register ****************/
7791#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!<Option Byte Key */
7792
7793/****************** Bit definition for FLASH_SR register *******************/
7794#define FLASH_SR_BSY ((uint8_t)0x01) /*!<Busy */
7795#define FLASH_SR_PGERR ((uint8_t)0x04) /*!<Programming Error */
7796#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!<Write Protection Error */
7797#define FLASH_SR_EOP ((uint8_t)0x20) /*!<End of operation */
7798
7799/******************* Bit definition for FLASH_CR register *******************/
7800#define FLASH_CR_PG ((uint16_t)0x0001) /*!<Programming */
7801#define FLASH_CR_PER ((uint16_t)0x0002) /*!<Page Erase */
7802#define FLASH_CR_MER ((uint16_t)0x0004) /*!<Mass Erase */
7803#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!<Option Byte Programming */
7804#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!<Option Byte Erase */
7805#define FLASH_CR_STRT ((uint16_t)0x0040) /*!<Start */
7806#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!<Lock */
7807#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!<Option Bytes Write Enable */
7808#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!<Error Interrupt Enable */
7809#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!<End of operation interrupt enable */
7810
7811/******************* Bit definition for FLASH_AR register *******************/
7812#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!<Flash Address */
7813
7814/****************** Bit definition for FLASH_OBR register *******************/
7815#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!<Option Byte Error */
7816#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!<Read protection */
7817
7818#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!<User Option Bytes */
7819#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!<WDG_SW */
7820#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!<nRST_STOP */
7821#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!<nRST_STDBY */
7822#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!<BFB2 */
7823
7824/****************** Bit definition for FLASH_WRPR register ******************/
7825#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!<Write Protect */
7826
7827/*----------------------------------------------------------------------------*/
7828
7829/****************** Bit definition for FLASH_RDP register *******************/
7830#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!<Read protection option byte */
7831#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!<Read protection complemented option byte */
7832
7833/****************** Bit definition for FLASH_USER register ******************/
7834#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!<User option byte */
7835#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!<User complemented option byte */
7836
7837/****************** Bit definition for FLASH_Data0 register *****************/
7838#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!<User data storage option byte */
7839#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!<User data storage complemented option byte */
7840
7841/****************** Bit definition for FLASH_Data1 register *****************/
7842#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!<User data storage option byte */
7843#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!<User data storage complemented option byte */
7844
7845/****************** Bit definition for FLASH_WRP0 register ******************/
7846#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!<Flash memory write protection option bytes */
7847#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!<Flash memory write protection complemented option bytes */
7848
7849/****************** Bit definition for FLASH_WRP1 register ******************/
7850#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!<Flash memory write protection option bytes */
7851#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!<Flash memory write protection complemented option bytes */
7852
7853/****************** Bit definition for FLASH_WRP2 register ******************/
7854#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!<Flash memory write protection option bytes */
7855#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!<Flash memory write protection complemented option bytes */
7856
7857/****************** Bit definition for FLASH_WRP3 register ******************/
7858#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!<Flash memory write protection option bytes */
7859#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!<Flash memory write protection complemented option bytes */
7860
7861#ifdef STM32F10X_CL
7862/******************************************************************************/
7863/* Ethernet MAC Registers bits definitions */
7864/******************************************************************************/
7865/* Bit definition for Ethernet MAC Control Register register */
7866#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
7867#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
7868#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
7869 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
7870 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
7871 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
7872 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
7873 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
7874 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
7875 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
7876 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
7877#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
7878#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
7879#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
7880#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
7881#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
7882#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
7883#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
7884#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
7885#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
7886 a transmission attempt during retries after a collision: 0 =< r <2^k */
7887 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
7888 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
7889 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
7890 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
7891#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
7892#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
7893#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
7894
7895/* Bit definition for Ethernet MAC Frame Filter Register */
7896#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
7897#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
7898#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
7899#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
7900#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
7901 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
7902 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
7903 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
7904#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
7905#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
7906#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
7907#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
7908#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
7909#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
7910
7911/* Bit definition for Ethernet MAC Hash Table High Register */
7912#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
7913
7914/* Bit definition for Ethernet MAC Hash Table Low Register */
7915#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
7916
7917/* Bit definition for Ethernet MAC MII Address Register */
7918#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
7919#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
7920#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
7921 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
7922 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
7923 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
7924#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
7925#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
7926
7927/* Bit definition for Ethernet MAC MII Data Register */
7928#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
7929
7930/* Bit definition for Ethernet MAC Flow Control Register */
7931#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
7932#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
7933#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
7934 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
7935 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
7936 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
7937 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
7938#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
7939#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
7940#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
7941#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
7942
7943/* Bit definition for Ethernet MAC VLAN Tag Register */
7944#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
7945#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
7946
7947/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
7948#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
7949/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
7950 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
7951/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
7952 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
7953 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
7954 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
7955 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
7956 RSVD - Filter1 Command - RSVD - Filter0 Command
7957 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
7958 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
7959 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
7960
7961/* Bit definition for Ethernet MAC PMT Control and Status Register */
7962#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
7963#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
7964#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
7965#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
7966#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
7967#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
7968#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
7969
7970/* Bit definition for Ethernet MAC Status Register */
7971#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
7972#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
7973#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
7974#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
7975#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
7976
7977/* Bit definition for Ethernet MAC Interrupt Mask Register */
7978#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
7979#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
7980
7981/* Bit definition for Ethernet MAC Address0 High Register */
7982#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
7983
7984/* Bit definition for Ethernet MAC Address0 Low Register */
7985#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
7986
7987/* Bit definition for Ethernet MAC Address1 High Register */
7988#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
7989#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
7990#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
7991 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
7992 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
7993 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
7994 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
7995 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
7996 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
7997#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
7998
7999/* Bit definition for Ethernet MAC Address1 Low Register */
8000#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
8001
8002/* Bit definition for Ethernet MAC Address2 High Register */
8003#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
8004#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
8005#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
8006 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
8007 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
8008 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
8009 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
8010 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
8011 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
8012#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
8013
8014/* Bit definition for Ethernet MAC Address2 Low Register */
8015#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
8016
8017/* Bit definition for Ethernet MAC Address3 High Register */
8018#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
8019#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
8020#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
8021 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
8022 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
8023 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
8024 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
8025 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
8026 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
8027#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
8028
8029/* Bit definition for Ethernet MAC Address3 Low Register */
8030#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
8031
8032/******************************************************************************/
8033/* Ethernet MMC Registers bits definition */
8034/******************************************************************************/
8035
8036/* Bit definition for Ethernet MMC Contol Register */
8037#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
8038#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
8039#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
8040#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
8041
8042/* Bit definition for Ethernet MMC Receive Interrupt Register */
8043#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
8044#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
8045#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
8046
8047/* Bit definition for Ethernet MMC Transmit Interrupt Register */
8048#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
8049#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
8050#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
8051
8052/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
8053#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
8054#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
8055#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
8056
8057/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
8058#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
8059#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
8060#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
8061
8062/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
8063#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
8064
8065/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
8066#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
8067
8068/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
8069#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
8070
8071/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
8072#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
8073
8074/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
8075#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
8076
8077/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
8078#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
8079
8080/******************************************************************************/
8081/* Ethernet PTP Registers bits definition */
8082/******************************************************************************/
8083
8084/* Bit definition for Ethernet PTP Time Stamp Contol Register */
8085#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
8086#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
8087#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
8088#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
8089#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
8090#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
8091
8092/* Bit definition for Ethernet PTP Sub-Second Increment Register */
8093#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
8094
8095/* Bit definition for Ethernet PTP Time Stamp High Register */
8096#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
8097
8098/* Bit definition for Ethernet PTP Time Stamp Low Register */
8099#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
8100#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
8101
8102/* Bit definition for Ethernet PTP Time Stamp High Update Register */
8103#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
8104
8105/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
8106#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
8107#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
8108
8109/* Bit definition for Ethernet PTP Time Stamp Addend Register */
8110#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
8111
8112/* Bit definition for Ethernet PTP Target Time High Register */
8113#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
8114
8115/* Bit definition for Ethernet PTP Target Time Low Register */
8116#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
8117
8118/******************************************************************************/
8119/* Ethernet DMA Registers bits definition */
8120/******************************************************************************/
8121
8122/* Bit definition for Ethernet DMA Bus Mode Register */
8123#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
8124#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
8125#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
8126#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
8127 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
8128 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
8129 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
8130 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
8131 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
8132 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
8133 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
8134 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
8135 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
8136 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
8137 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
8138 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
8139#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
8140#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
8141 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
8142 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
8143 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
8144 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
8145#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
8146 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
8147 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
8148 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
8149 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
8150 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
8151 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
8152 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
8153 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
8154 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
8155 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
8156 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
8157 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
8158#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
8159#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
8160#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
8161
8162/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
8163#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
8164
8165/* Bit definition for Ethernet DMA Receive Poll Demand Register */
8166#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
8167
8168/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
8169#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
8170
8171/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
8172#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
8173
8174/* Bit definition for Ethernet DMA Status Register */
8175#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
8176#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
8177#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
8178#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
8179 /* combination with EBS[2:0] for GetFlagStatus function */
8180 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
8181 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
8182 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
8183#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
8184 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
8185 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
8186 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
8187 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
8188 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
8189 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
8190#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
8191 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
8192 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
8193 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
8194 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
8195 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
8196 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
8197#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
8198#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
8199#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
8200#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
8201#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
8202#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
8203#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
8204#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
8205#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
8206#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
8207#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
8208#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
8209#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
8210#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
8211#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
8212
8213/* Bit definition for Ethernet DMA Operation Mode Register */
8214#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
8215#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
8216#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
8217#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
8218#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
8219#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
8220 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
8221 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
8222 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
8223 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
8224 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
8225 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
8226 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
8227 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
8228#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
8229#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
8230#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
8231#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
8232 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
8233 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
8234 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
8235 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
8236#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
8237#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
8238
8239/* Bit definition for Ethernet DMA Interrupt Enable Register */
8240#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
8241#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
8242#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
8243#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
8244#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
8245#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
8246#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
8247#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
8248#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
8249#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
8250#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
8251#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
8252#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
8253#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
8254#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
8255
8256/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
8257#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
8258#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
8259#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
8260#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
8261
8262/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
8263#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
8264
8265/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
8266#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
8267
8268/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
8269#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
8270
8271/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
8272#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
8273#endif /* STM32F10X_CL */
8274
8275/**
8276 * @}
8277 */
8278
8279 /**
8280 * @}
8281 */
8282
8283#ifdef USE_STDPERIPH_DRIVER
8284 #include "stm32f10x_conf.h"
8285#endif
8286
8287/** @addtogroup Exported_macro
8288 * @{
8289 */
8290
8291#define SET_BIT(REG, BIT) ((REG) |= (BIT))
8292
8293#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
8294
8295#define READ_BIT(REG, BIT) ((REG) & (BIT))
8296
8297#define CLEAR_REG(REG) ((REG) = (0x0))
8298
8299#define WRITE_REG(REG, VAL) ((REG) = (VAL))
8300
8301#define READ_REG(REG) ((REG))
8302
8303#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
8304
8305/**
8306 * @}
8307 */
8308
8309#ifdef __cplusplus
8310}
8311#endif
8312
8313#endif /* __STM32F10x_H */
8314
8315/**
8316 * @}
8317 */
8318
8319 /**
8320 * @}
8321 */
8322
8323/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/