Blame - src/bsp/lk/platform/stm32f1xx/vectab.c - T103

rjw

1f88458

2022-01-06 17:20:42 +0800

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/*

*

* Permission is hereby granted, free of charge, to any person obtaining

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* a copy of this software and associated documentation files

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* (the "Software"), to deal in the Software without restriction,

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* including without limitation the rights to use, copy, modify, merge,

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* publish, distribute, sublicense, and/or sell copies of the Software,

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* and to permit persons to whom the Software is furnished to do so,

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* subject to the following conditions:

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*

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* The above copyright notice and this permission notice shall be

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* included in all copies or substantial portions of the Software.

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*

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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.

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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY

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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,

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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE

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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

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*/

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#include <debug.h>

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#include <compiler.h>

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#include <stm32f10x.h>

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#include <arch/arm/cm.h>

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#include <platform/stm32.h>

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#include <target/debugconfig.h>

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#include <lib/cbuf.h>

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/* un-overridden irq handler */

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void stm32_dummy_irq(void)

{

arm_cm_irq_entry();

panic("unhandled irq\n");

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}

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/* a list of default handlers that are simply aliases to the dummy handler */

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#define DEFAULT_HANDLER(x) \

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void stm32_##x(void) __WEAK_ALIAS("stm32_dummy_irq");

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DEFAULT_HANDLER(WWDG_IRQ);

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DEFAULT_HANDLER(PVD_IRQ);

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DEFAULT_HANDLER(TAMPER_IRQ);

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DEFAULT_HANDLER(RTC_IRQ);

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DEFAULT_HANDLER(FLASH_IRQ);

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DEFAULT_HANDLER(RCC_IRQ);

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DEFAULT_HANDLER(EXTI0_IRQ);

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DEFAULT_HANDLER(EXTI1_IRQ);

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DEFAULT_HANDLER(EXTI2_IRQ);

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DEFAULT_HANDLER(EXTI3_IRQ);

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DEFAULT_HANDLER(EXTI4_IRQ);

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DEFAULT_HANDLER(DMA1_Channel1_IRQ);

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DEFAULT_HANDLER(DMA1_Channel2_IRQ);

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DEFAULT_HANDLER(DMA1_Channel3_IRQ);

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DEFAULT_HANDLER(DMA1_Channel4_IRQ);

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DEFAULT_HANDLER(DMA1_Channel5_IRQ);

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DEFAULT_HANDLER(DMA1_Channel6_IRQ);

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DEFAULT_HANDLER(DMA1_Channel7_IRQ);

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DEFAULT_HANDLER(USART1_IRQ);

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DEFAULT_HANDLER(USART2_IRQ);

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DEFAULT_HANDLER(USART3_IRQ);

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DEFAULT_HANDLER(TIM2_IRQ);

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DEFAULT_HANDLER(TIM3_IRQ);

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DEFAULT_HANDLER(TIM4_IRQ);

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DEFAULT_HANDLER(TIM5_IRQ);

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DEFAULT_HANDLER(TIM6_IRQ);

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DEFAULT_HANDLER(TIM7_IRQ);

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DEFAULT_HANDLER(ADC1_2_IRQ);

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DEFAULT_HANDLER(USB_HP_CAN1_TX_IRQ);

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DEFAULT_HANDLER(USB_LP_CAN1_RX0_IRQ);

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DEFAULT_HANDLER(CAN1_RX1_IRQ);

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DEFAULT_HANDLER(CAN1_SCE_IRQ);

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DEFAULT_HANDLER(EXTI9_5_IRQ);

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DEFAULT_HANDLER(TIM1_BRK_IRQ);

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DEFAULT_HANDLER(TIM1_UP_IRQ);

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DEFAULT_HANDLER(TIM1_TRG_COM_IRQ);

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DEFAULT_HANDLER(TIM1_CC_IRQ);

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DEFAULT_HANDLER(I2C1_EV_IRQ);

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DEFAULT_HANDLER(I2C1_ER_IRQ);

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DEFAULT_HANDLER(I2C2_EV_IRQ);

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DEFAULT_HANDLER(I2C2_ER_IRQ);

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DEFAULT_HANDLER(SPI1_IRQ);

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DEFAULT_HANDLER(SPI2_IRQ);

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DEFAULT_HANDLER(EXTI15_10_IRQ);

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DEFAULT_HANDLER(RTCAlarm_IRQ);

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DEFAULT_HANDLER(USBWakeUp_IRQ);

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DEFAULT_HANDLER(CAN1_TX_IRQ);

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DEFAULT_HANDLER(CAN1_RX0_IRQ);

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DEFAULT_HANDLER(OTG_FS_WKUP_IRQ);

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DEFAULT_HANDLER(SPI3_IRQ);

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DEFAULT_HANDLER(UART4_IRQ);

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DEFAULT_HANDLER(UART5_IRQ);

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DEFAULT_HANDLER(DMA2_Channel1_IRQ);

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DEFAULT_HANDLER(DMA2_Channel2_IRQ);

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DEFAULT_HANDLER(DMA2_Channel3_IRQ);

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DEFAULT_HANDLER(DMA2_Channel4_IRQ);

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DEFAULT_HANDLER(DMA2_Channel5_IRQ);

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DEFAULT_HANDLER(ETH_IRQ);

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DEFAULT_HANDLER(ETH_WKUP_IRQ);

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DEFAULT_HANDLER(CAN2_TX_IRQ);

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DEFAULT_HANDLER(CAN2_RX0_IRQ);

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DEFAULT_HANDLER(CAN2_RX1_IRQ);

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DEFAULT_HANDLER(CAN2_SCE_IRQ);

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DEFAULT_HANDLER(OTG_FS_IRQ);

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DEFAULT_HANDLER(TIM8_BRK_IRQ);

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DEFAULT_HANDLER(TIM8_UP_IRQ);

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DEFAULT_HANDLER(TIM8_TRG_COM_IRQ);

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DEFAULT_HANDLER(TIM8_CC_IRQ);

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DEFAULT_HANDLER(ADC3_IRQ);

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DEFAULT_HANDLER(FSMC_IRQ);

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DEFAULT_HANDLER(SDIO_IRQ);

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DEFAULT_HANDLER(DMA2_Channel4_5_IRQ);

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DEFAULT_HANDLER(TIM1_BRK_TIM9_IRQ);

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DEFAULT_HANDLER(TIM1_UP_TIM10_IRQ);

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DEFAULT_HANDLER(TIM1_TRG_COM_TIM11_IRQ);

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DEFAULT_HANDLER(TIM8_BRK_TIM12_IRQ);

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DEFAULT_HANDLER(TIM8_UP_TIM13_IRQ);

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DEFAULT_HANDLER(TIM8_TRG_COM_TIM14_IRQ);

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#define VECTAB_ENTRY(x) [x##n] = stm32_##x

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/* appended to the end of the main vector table */

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const void * const __SECTION(".text.boot.vectab2") vectab2[] = {

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VECTAB_ENTRY(WWDG_IRQ), /*!< Window WatchDog Interrupt */

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VECTAB_ENTRY(PVD_IRQ), /*!< PVD through EXTI Line detection Interrupt */

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VECTAB_ENTRY(TAMPER_IRQ), /*!< Tamper Interrupt */

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VECTAB_ENTRY(RTC_IRQ), /*!< RTC global Interrupt */

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VECTAB_ENTRY(FLASH_IRQ), /*!< FLASH global Interrupt */

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VECTAB_ENTRY(RCC_IRQ), /*!< RCC global Interrupt */

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VECTAB_ENTRY(EXTI0_IRQ), /*!< EXTI Line0 Interrupt */

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VECTAB_ENTRY(EXTI1_IRQ), /*!< EXTI Line1 Interrupt */

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VECTAB_ENTRY(EXTI2_IRQ), /*!< EXTI Line2 Interrupt */

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VECTAB_ENTRY(EXTI3_IRQ), /*!< EXTI Line3 Interrupt */

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VECTAB_ENTRY(EXTI4_IRQ), /*!< EXTI Line4 Interrupt */

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VECTAB_ENTRY(DMA1_Channel1_IRQ), /*!< DMA1 Channel 1 global Interrupt */

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VECTAB_ENTRY(DMA1_Channel2_IRQ), /*!< DMA1 Channel 2 global Interrupt */

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VECTAB_ENTRY(DMA1_Channel3_IRQ), /*!< DMA1 Channel 3 global Interrupt */

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VECTAB_ENTRY(DMA1_Channel4_IRQ), /*!< DMA1 Channel 4 global Interrupt */

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VECTAB_ENTRY(DMA1_Channel5_IRQ), /*!< DMA1 Channel 5 global Interrupt */

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VECTAB_ENTRY(DMA1_Channel6_IRQ), /*!< DMA1 Channel 6 global Interrupt */

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VECTAB_ENTRY(DMA1_Channel7_IRQ), /*!< DMA1 Channel 7 global Interrupt */

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/* taken from the stm32 irq definition list */

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#ifdef STM32F10X_LD

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VECTAB_ENTRY(ADC1_2_IRQ), /*!< ADC1 and ADC2 global Interrupt */

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VECTAB_ENTRY(USB_HP_CAN1_TX_IRQ), /*!< USB Device High Priority or CAN1 TX Interrupts */

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VECTAB_ENTRY(USB_LP_CAN1_RX0_IRQ), /*!< USB Device Low Priority or CAN1 RX0 Interrupts */

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VECTAB_ENTRY(CAN1_RX1_IRQ), /*!< CAN1 RX1 Interrupt */

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VECTAB_ENTRY(CAN1_SCE_IRQ), /*!< CAN1 SCE Interrupt */

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VECTAB_ENTRY(EXTI9_5_IRQ), /*!< External Line[9:5] Interrupts */

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VECTAB_ENTRY(TIM1_BRK_IRQ), /*!< TIM1 Break Interrupt */

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VECTAB_ENTRY(TIM1_UP_IRQ), /*!< TIM1 Update Interrupt */

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VECTAB_ENTRY(TIM1_TRG_COM_IRQ), /*!< TIM1 Trigger and Commutation Interrupt */

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VECTAB_ENTRY(TIM1_CC_IRQ), /*!< TIM1 Capture Compare Interrupt */

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VECTAB_ENTRY(TIM2_IRQ), /*!< TIM2 global Interrupt */

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VECTAB_ENTRY(TIM3_IRQ), /*!< TIM3 global Interrupt */

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VECTAB_ENTRY(I2C1_EV_IRQ), /*!< I2C1 Event Interrupt */

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VECTAB_ENTRY(I2C1_ER_IRQ), /*!< I2C1 Error Interrupt */

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VECTAB_ENTRY(SPI1_IRQ), /*!< SPI1 global Interrupt */

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VECTAB_ENTRY(USART1_IRQ), /*!< USART1 global Interrupt */

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VECTAB_ENTRY(USART2_IRQ), /*!< USART2 global Interrupt */

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VECTAB_ENTRY(EXTI15_10_IRQ), /*!< External Line[15:10] Interrupts */

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VECTAB_ENTRY(RTCAlarm_IRQ), /*!< RTC Alarm through EXTI Line Interrupt */

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VECTAB_ENTRY(USBWakeUp_IRQ), /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */

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#endif /* STM32F10X_LD */

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#ifdef STM32F10X_LD_VL

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VECTAB_ENTRY(ADC1_IRQ), /*!< ADC1 global Interrupt */

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VECTAB_ENTRY(EXTI9_5_IRQ), /*!< External Line[9:5] Interrupts */

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VECTAB_ENTRY(TIM1_BRK_TIM15_IRQ), /*!< TIM1 Break and TIM15 Interrupts */

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VECTAB_ENTRY(TIM1_UP_TIM16_IRQ), /*!< TIM1 Update and TIM16 Interrupts */

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VECTAB_ENTRY(TIM1_TRG_COM_TIM17_IRQ), /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */

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VECTAB_ENTRY(TIM1_CC_IRQ), /*!< TIM1 Capture Compare Interrupt */

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VECTAB_ENTRY(TIM2_IRQ), /*!< TIM2 global Interrupt */

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VECTAB_ENTRY(TIM3_IRQ), /*!< TIM3 global Interrupt */

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VECTAB_ENTRY(I2C1_EV_IRQ), /*!< I2C1 Event Interrupt */

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VECTAB_ENTRY(I2C1_ER_IRQ), /*!< I2C1 Error Interrupt */

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VECTAB_ENTRY(SPI1_IRQ), /*!< SPI1 global Interrupt */

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VECTAB_ENTRY(USART1_IRQ), /*!< USART1 global Interrupt */

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VECTAB_ENTRY(USART2_IRQ), /*!< USART2 global Interrupt */

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VECTAB_ENTRY(EXTI15_10_IRQ), /*!< External Line[15:10] Interrupts */

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VECTAB_ENTRY(RTCAlarm_IRQ), /*!< RTC Alarm through EXTI Line Interrupt */

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VECTAB_ENTRY(CEC_IRQ), /*!< HDMI-CEC Interrupt */

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VECTAB_ENTRY(TIM6_DAC_IRQ), /*!< TIM6 and DAC underrun Interrupt */

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VECTAB_ENTRY(TIM7_IRQ), /*!< TIM7 Interrupt */

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#endif /* STM32F10X_LD_VL */

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#ifdef STM32F10X_MD

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VECTAB_ENTRY(ADC1_2_IRQ), /*!< ADC1 and ADC2 global Interrupt */

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VECTAB_ENTRY(USB_HP_CAN1_TX_IRQ), /*!< USB Device High Priority or CAN1 TX Interrupts */

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VECTAB_ENTRY(USB_LP_CAN1_RX0_IRQ), /*!< USB Device Low Priority or CAN1 RX0 Interrupts */

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VECTAB_ENTRY(CAN1_RX1_IRQ), /*!< CAN1 RX1 Interrupt */

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VECTAB_ENTRY(CAN1_SCE_IRQ), /*!< CAN1 SCE Interrupt */

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VECTAB_ENTRY(EXTI9_5_IRQ), /*!< External Line[9:5] Interrupts */

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VECTAB_ENTRY(TIM1_BRK_IRQ), /*!< TIM1 Break Interrupt */

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VECTAB_ENTRY(TIM1_UP_IRQ), /*!< TIM1 Update Interrupt */

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VECTAB_ENTRY(TIM1_TRG_COM_IRQ), /*!< TIM1 Trigger and Commutation Interrupt */

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VECTAB_ENTRY(TIM1_CC_IRQ), /*!< TIM1 Capture Compare Interrupt */

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VECTAB_ENTRY(TIM2_IRQ), /*!< TIM2 global Interrupt */

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VECTAB_ENTRY(TIM3_IRQ), /*!< TIM3 global Interrupt */

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VECTAB_ENTRY(TIM4_IRQ), /*!< TIM4 global Interrupt */

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VECTAB_ENTRY(I2C1_EV_IRQ), /*!< I2C1 Event Interrupt */

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VECTAB_ENTRY(I2C1_ER_IRQ), /*!< I2C1 Error Interrupt */

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VECTAB_ENTRY(I2C2_EV_IRQ), /*!< I2C2 Event Interrupt */

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VECTAB_ENTRY(I2C2_ER_IRQ), /*!< I2C2 Error Interrupt */

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VECTAB_ENTRY(SPI1_IRQ), /*!< SPI1 global Interrupt */

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VECTAB_ENTRY(SPI2_IRQ), /*!< SPI2 global Interrupt */

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VECTAB_ENTRY(USART1_IRQ), /*!< USART1 global Interrupt */

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VECTAB_ENTRY(USART2_IRQ), /*!< USART2 global Interrupt */

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VECTAB_ENTRY(USART3_IRQ), /*!< USART3 global Interrupt */

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VECTAB_ENTRY(EXTI15_10_IRQ), /*!< External Line[15:10] Interrupts */

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VECTAB_ENTRY(RTCAlarm_IRQ), /*!< RTC Alarm through EXTI Line Interrupt */

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VECTAB_ENTRY(USBWakeUp_IRQ), /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */

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#endif /* STM32F10X_MD */

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#ifdef STM32F10X_MD_VL

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VECTAB_ENTRY(ADC1_IRQ), /*!< ADC1 global Interrupt */

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VECTAB_ENTRY(EXTI9_5_IRQ), /*!< External Line[9:5] Interrupts */

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VECTAB_ENTRY(TIM1_BRK_TIM15_IRQ), /*!< TIM1 Break and TIM15 Interrupts */

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VECTAB_ENTRY(TIM1_UP_TIM16_IRQ), /*!< TIM1 Update and TIM16 Interrupts */

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VECTAB_ENTRY(TIM1_TRG_COM_TIM17_IRQ), /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */

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VECTAB_ENTRY(TIM1_CC_IRQ), /*!< TIM1 Capture Compare Interrupt */

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VECTAB_ENTRY(TIM2_IRQ), /*!< TIM2 global Interrupt */

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VECTAB_ENTRY(TIM3_IRQ), /*!< TIM3 global Interrupt */

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VECTAB_ENTRY(TIM4_IRQ), /*!< TIM4 global Interrupt */

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VECTAB_ENTRY(I2C1_EV_IRQ), /*!< I2C1 Event Interrupt */

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VECTAB_ENTRY(I2C1_ER_IRQ), /*!< I2C1 Error Interrupt */

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VECTAB_ENTRY(I2C2_EV_IRQ), /*!< I2C2 Event Interrupt */

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VECTAB_ENTRY(I2C2_ER_IRQ), /*!< I2C2 Error Interrupt */

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VECTAB_ENTRY(SPI1_IRQ), /*!< SPI1 global Interrupt */

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VECTAB_ENTRY(SPI2_IRQ), /*!< SPI2 global Interrupt */

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VECTAB_ENTRY(USART1_IRQ), /*!< USART1 global Interrupt */

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VECTAB_ENTRY(USART2_IRQ), /*!< USART2 global Interrupt */

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VECTAB_ENTRY(USART3_IRQ), /*!< USART3 global Interrupt */

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VECTAB_ENTRY(EXTI15_10_IRQ), /*!< External Line[15:10] Interrupts */

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VECTAB_ENTRY(RTCAlarm_IRQ), /*!< RTC Alarm through EXTI Line Interrupt */

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VECTAB_ENTRY(CEC_IRQ), /*!< HDMI-CEC Interrupt */

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VECTAB_ENTRY(TIM6_DAC_IRQ), /*!< TIM6 and DAC underrun Interrupt */

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VECTAB_ENTRY(TIM7_IRQ), /*!< TIM7 Interrupt */

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#endif /* STM32F10X_MD_VL */

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#ifdef STM32F10X_HD

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VECTAB_ENTRY(ADC1_2_IRQ), /*!< ADC1 and ADC2 global Interrupt */

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VECTAB_ENTRY(USB_HP_CAN1_TX_IRQ), /*!< USB Device High Priority or CAN1 TX Interrupts */

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VECTAB_ENTRY(USB_LP_CAN1_RX0_IRQ), /*!< USB Device Low Priority or CAN1 RX0 Interrupts */

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VECTAB_ENTRY(CAN1_RX1_IRQ), /*!< CAN1 RX1 Interrupt */

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VECTAB_ENTRY(CAN1_SCE_IRQ), /*!< CAN1 SCE Interrupt */

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VECTAB_ENTRY(EXTI9_5_IRQ), /*!< External Line[9:5] Interrupts */

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VECTAB_ENTRY(TIM1_BRK_IRQ), /*!< TIM1 Break Interrupt */

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VECTAB_ENTRY(TIM1_UP_IRQ), /*!< TIM1 Update Interrupt */

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VECTAB_ENTRY(TIM1_TRG_COM_IRQ), /*!< TIM1 Trigger and Commutation Interrupt */

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VECTAB_ENTRY(TIM1_CC_IRQ), /*!< TIM1 Capture Compare Interrupt */

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VECTAB_ENTRY(TIM2_IRQ), /*!< TIM2 global Interrupt */

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VECTAB_ENTRY(TIM3_IRQ), /*!< TIM3 global Interrupt */

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VECTAB_ENTRY(TIM4_IRQ), /*!< TIM4 global Interrupt */

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VECTAB_ENTRY(I2C1_EV_IRQ), /*!< I2C1 Event Interrupt */

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VECTAB_ENTRY(I2C1_ER_IRQ), /*!< I2C1 Error Interrupt */

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VECTAB_ENTRY(I2C2_EV_IRQ), /*!< I2C2 Event Interrupt */

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VECTAB_ENTRY(I2C2_ER_IRQ), /*!< I2C2 Error Interrupt */

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VECTAB_ENTRY(SPI1_IRQ), /*!< SPI1 global Interrupt */

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VECTAB_ENTRY(SPI2_IRQ), /*!< SPI2 global Interrupt */

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VECTAB_ENTRY(USART1_IRQ), /*!< USART1 global Interrupt */

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VECTAB_ENTRY(USART2_IRQ), /*!< USART2 global Interrupt */

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VECTAB_ENTRY(USART3_IRQ), /*!< USART3 global Interrupt */

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VECTAB_ENTRY(EXTI15_10_IRQ), /*!< External Line[15:10] Interrupts */

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VECTAB_ENTRY(RTCAlarm_IRQ), /*!< RTC Alarm through EXTI Line Interrupt */

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VECTAB_ENTRY(USBWakeUp_IRQ), /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */

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VECTAB_ENTRY(TIM8_BRK_IRQ), /*!< TIM8 Break Interrupt */

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VECTAB_ENTRY(TIM8_UP_IRQ), /*!< TIM8 Update Interrupt */

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VECTAB_ENTRY(TIM8_TRG_COM_IRQ), /*!< TIM8 Trigger and Commutation Interrupt */

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VECTAB_ENTRY(TIM8_CC_IRQ), /*!< TIM8 Capture Compare Interrupt */

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VECTAB_ENTRY(ADC3_IRQ), /*!< ADC3 global Interrupt */

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VECTAB_ENTRY(FSMC_IRQ), /*!< FSMC global Interrupt */

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VECTAB_ENTRY(SDIO_IRQ), /*!< SDIO global Interrupt */

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VECTAB_ENTRY(TIM5_IRQ), /*!< TIM5 global Interrupt */

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VECTAB_ENTRY(SPI3_IRQ), /*!< SPI3 global Interrupt */

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VECTAB_ENTRY(UART4_IRQ), /*!< UART4 global Interrupt */

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VECTAB_ENTRY(UART5_IRQ), /*!< UART5 global Interrupt */

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VECTAB_ENTRY(TIM6_IRQ), /*!< TIM6 global Interrupt */

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VECTAB_ENTRY(TIM7_IRQ), /*!< TIM7 global Interrupt */

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VECTAB_ENTRY(DMA2_Channel1_IRQ), /*!< DMA2 Channel 1 global Interrupt */

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VECTAB_ENTRY(DMA2_Channel2_IRQ), /*!< DMA2 Channel 2 global Interrupt */

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VECTAB_ENTRY(DMA2_Channel3_IRQ), /*!< DMA2 Channel 3 global Interrupt */

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VECTAB_ENTRY(DMA2_Channel4_5_IRQ), /*!< DMA2 Channel 4 and Channel 5 global Interrupt */

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#endif /* STM32F10X_HD */

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#ifdef STM32F10X_HD_VL

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VECTAB_ENTRY(ADC1_IRQ), /*!< ADC1 global Interrupt */

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VECTAB_ENTRY(EXTI9_5_IRQ), /*!< External Line[9:5] Interrupts */

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VECTAB_ENTRY(TIM1_BRK_TIM15_IRQ), /*!< TIM1 Break and TIM15 Interrupts */

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VECTAB_ENTRY(TIM1_UP_TIM16_IRQ), /*!< TIM1 Update and TIM16 Interrupts */

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VECTAB_ENTRY(TIM1_TRG_COM_TIM17_IRQ), /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */

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VECTAB_ENTRY(TIM1_CC_IRQ), /*!< TIM1 Capture Compare Interrupt */

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VECTAB_ENTRY(TIM2_IRQ), /*!< TIM2 global Interrupt */

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VECTAB_ENTRY(TIM3_IRQ), /*!< TIM3 global Interrupt */

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VECTAB_ENTRY(TIM4_IRQ), /*!< TIM4 global Interrupt */

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VECTAB_ENTRY(I2C1_EV_IRQ), /*!< I2C1 Event Interrupt */

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VECTAB_ENTRY(I2C1_ER_IRQ), /*!< I2C1 Error Interrupt */

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VECTAB_ENTRY(I2C2_EV_IRQ), /*!< I2C2 Event Interrupt */

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VECTAB_ENTRY(I2C2_ER_IRQ), /*!< I2C2 Error Interrupt */

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VECTAB_ENTRY(SPI1_IRQ), /*!< SPI1 global Interrupt */

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VECTAB_ENTRY(SPI2_IRQ), /*!< SPI2 global Interrupt */

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VECTAB_ENTRY(USART1_IRQ), /*!< USART1 global Interrupt */

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VECTAB_ENTRY(USART2_IRQ), /*!< USART2 global Interrupt */

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VECTAB_ENTRY(USART3_IRQ), /*!< USART3 global Interrupt */

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VECTAB_ENTRY(EXTI15_10_IRQ), /*!< External Line[15:10] Interrupts */

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VECTAB_ENTRY(RTCAlarm_IRQ), /*!< RTC Alarm through EXTI Line Interrupt */

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VECTAB_ENTRY(CEC_IRQ), /*!< HDMI-CEC Interrupt */

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VECTAB_ENTRY(TIM12_IRQ), /*!< TIM12 global Interrupt */

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VECTAB_ENTRY(TIM13_IRQ), /*!< TIM13 global Interrupt */

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VECTAB_ENTRY(TIM14_IRQ), /*!< TIM14 global Interrupt */

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VECTAB_ENTRY(FSMC_IRQ), /*!< FSMC global Interrupt */

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VECTAB_ENTRY(TIM5_IRQ), /*!< TIM5 global Interrupt */

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VECTAB_ENTRY(SPI3_IRQ), /*!< SPI3 global Interrupt */

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VECTAB_ENTRY(UART4_IRQ), /*!< UART4 global Interrupt */

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VECTAB_ENTRY(UART5_IRQ), /*!< UART5 global Interrupt */

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VECTAB_ENTRY(TIM6_DAC_IRQ), /*!< TIM6 and DAC underrun Interrupt */

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VECTAB_ENTRY(TIM7_IRQ), /*!< TIM7 Interrupt */

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VECTAB_ENTRY(DMA2_Channel1_IRQ), /*!< DMA2 Channel 1 global Interrupt */

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VECTAB_ENTRY(DMA2_Channel2_IRQ), /*!< DMA2 Channel 2 global Interrupt */

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VECTAB_ENTRY(DMA2_Channel3_IRQ), /*!< DMA2 Channel 3 global Interrupt */

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VECTAB_ENTRY(DMA2_Channel4_5_IRQ), /*!< DMA2 Channel 4 and Channel 5 global Interrupt */

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VECTAB_ENTRY(DMA2_Channel5_IRQ), /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is

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mapped at postion 60 only if the MISC_REMAP bit in

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the AFIO_MAPR2 register is set) */

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#endif /* STM32F10X_HD_VL */

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#ifdef STM32F10X_XL

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VECTAB_ENTRY(ADC1_2_IRQ), /*!< ADC1 and ADC2 global Interrupt */

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VECTAB_ENTRY(USB_HP_CAN1_TX_IRQ), /*!< USB Device High Priority or CAN1 TX Interrupts */

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VECTAB_ENTRY(USB_LP_CAN1_RX0_IRQ), /*!< USB Device Low Priority or CAN1 RX0 Interrupts */

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VECTAB_ENTRY(CAN1_RX1_IRQ), /*!< CAN1 RX1 Interrupt */

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VECTAB_ENTRY(CAN1_SCE_IRQ), /*!< CAN1 SCE Interrupt */

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VECTAB_ENTRY(EXTI9_5_IRQ), /*!< External Line[9:5] Interrupts */

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VECTAB_ENTRY(TIM1_BRK_TIM9_IRQ), /*!< TIM1 Break Interrupt and TIM9 global Interrupt */

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VECTAB_ENTRY(TIM1_UP_TIM10_IRQ), /*!< TIM1 Update Interrupt and TIM10 global Interrupt */

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VECTAB_ENTRY(TIM1_TRG_COM_TIM11_IRQ), /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */

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VECTAB_ENTRY(TIM1_CC_IRQ), /*!< TIM1 Capture Compare Interrupt */

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VECTAB_ENTRY(TIM2_IRQ), /*!< TIM2 global Interrupt */

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VECTAB_ENTRY(TIM3_IRQ), /*!< TIM3 global Interrupt */

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VECTAB_ENTRY(TIM4_IRQ), /*!< TIM4 global Interrupt */

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VECTAB_ENTRY(I2C1_EV_IRQ), /*!< I2C1 Event Interrupt */

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VECTAB_ENTRY(I2C1_ER_IRQ), /*!< I2C1 Error Interrupt */

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VECTAB_ENTRY(I2C2_EV_IRQ), /*!< I2C2 Event Interrupt */

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VECTAB_ENTRY(I2C2_ER_IRQ), /*!< I2C2 Error Interrupt */

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VECTAB_ENTRY(SPI1_IRQ), /*!< SPI1 global Interrupt */

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VECTAB_ENTRY(SPI2_IRQ), /*!< SPI2 global Interrupt */

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VECTAB_ENTRY(USART1_IRQ), /*!< USART1 global Interrupt */

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VECTAB_ENTRY(USART2_IRQ), /*!< USART2 global Interrupt */

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VECTAB_ENTRY(USART3_IRQ), /*!< USART3 global Interrupt */

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VECTAB_ENTRY(EXTI15_10_IRQ), /*!< External Line[15:10] Interrupts */

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VECTAB_ENTRY(RTCAlarm_IRQ), /*!< RTC Alarm through EXTI Line Interrupt */

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VECTAB_ENTRY(USBWakeUp_IRQ), /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */

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VECTAB_ENTRY(TIM8_BRK_TIM12_IRQ), /*!< TIM8 Break Interrupt and TIM12 global Interrupt */

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VECTAB_ENTRY(TIM8_UP_TIM13_IRQ), /*!< TIM8 Update Interrupt and TIM13 global Interrupt */

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VECTAB_ENTRY(TIM8_TRG_COM_TIM14_IRQ), /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */

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VECTAB_ENTRY(TIM8_CC_IRQ), /*!< TIM8 Capture Compare Interrupt */

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VECTAB_ENTRY(ADC3_IRQ), /*!< ADC3 global Interrupt */

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VECTAB_ENTRY(FSMC_IRQ), /*!< FSMC global Interrupt */

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VECTAB_ENTRY(SDIO_IRQ), /*!< SDIO global Interrupt */

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VECTAB_ENTRY(TIM5_IRQ), /*!< TIM5 global Interrupt */

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VECTAB_ENTRY(SPI3_IRQ), /*!< SPI3 global Interrupt */

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VECTAB_ENTRY(UART4_IRQ), /*!< UART4 global Interrupt */

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VECTAB_ENTRY(UART5_IRQ), /*!< UART5 global Interrupt */

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VECTAB_ENTRY(TIM6_IRQ), /*!< TIM6 global Interrupt */

374

VECTAB_ENTRY(TIM7_IRQ), /*!< TIM7 global Interrupt */

375

VECTAB_ENTRY(DMA2_Channel1_IRQ), /*!< DMA2 Channel 1 global Interrupt */

376

VECTAB_ENTRY(DMA2_Channel2_IRQ), /*!< DMA2 Channel 2 global Interrupt */

377

VECTAB_ENTRY(DMA2_Channel3_IRQ), /*!< DMA2 Channel 3 global Interrupt */

378

VECTAB_ENTRY(DMA2_Channel4_5_IRQ), /*!< DMA2 Channel 4 and Channel 5 global Interrupt */

379

#endif /* STM32F10X_XL */

380

381

#ifdef STM32F10X_CL

382

VECTAB_ENTRY(ADC1_2_IRQ), /*!< ADC1 and ADC2 global Interrupt */

383

VECTAB_ENTRY(CAN1_TX_IRQ), /*!< USB Device High Priority or CAN1 TX Interrupts */

384

VECTAB_ENTRY(CAN1_RX0_IRQ), /*!< USB Device Low Priority or CAN1 RX0 Interrupts */

385

VECTAB_ENTRY(CAN1_RX1_IRQ), /*!< CAN1 RX1 Interrupt */

386

VECTAB_ENTRY(CAN1_SCE_IRQ), /*!< CAN1 SCE Interrupt */

387

VECTAB_ENTRY(EXTI9_5_IRQ), /*!< External Line[9:5] Interrupts */

388

VECTAB_ENTRY(TIM1_BRK_IRQ), /*!< TIM1 Break Interrupt */

389

VECTAB_ENTRY(TIM1_UP_IRQ), /*!< TIM1 Update Interrupt */

390

VECTAB_ENTRY(TIM1_TRG_COM_IRQ), /*!< TIM1 Trigger and Commutation Interrupt */

391

VECTAB_ENTRY(TIM1_CC_IRQ), /*!< TIM1 Capture Compare Interrupt */

392

VECTAB_ENTRY(TIM2_IRQ), /*!< TIM2 global Interrupt */

393

VECTAB_ENTRY(TIM3_IRQ), /*!< TIM3 global Interrupt */

394

VECTAB_ENTRY(TIM4_IRQ), /*!< TIM4 global Interrupt */

395

VECTAB_ENTRY(I2C1_EV_IRQ), /*!< I2C1 Event Interrupt */

396

VECTAB_ENTRY(I2C1_ER_IRQ), /*!< I2C1 Error Interrupt */

397

VECTAB_ENTRY(I2C2_EV_IRQ), /*!< I2C2 Event Interrupt */

398

VECTAB_ENTRY(I2C2_ER_IRQ), /*!< I2C2 Error Interrupt */

399

VECTAB_ENTRY(SPI1_IRQ), /*!< SPI1 global Interrupt */

400

VECTAB_ENTRY(SPI2_IRQ), /*!< SPI2 global Interrupt */

401

VECTAB_ENTRY(USART1_IRQ), /*!< USART1 global Interrupt */

402

VECTAB_ENTRY(USART2_IRQ), /*!< USART2 global Interrupt */

403

VECTAB_ENTRY(USART3_IRQ), /*!< USART3 global Interrupt */

404

VECTAB_ENTRY(EXTI15_10_IRQ), /*!< External Line[15:10] Interrupts */

405

VECTAB_ENTRY(RTCAlarm_IRQ), /*!< RTC Alarm through EXTI Line Interrupt */

406

VECTAB_ENTRY(OTG_FS_WKUP_IRQ), /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */

407

VECTAB_ENTRY(TIM5_IRQ), /*!< TIM5 global Interrupt */

408

VECTAB_ENTRY(SPI3_IRQ), /*!< SPI3 global Interrupt */

409

VECTAB_ENTRY(UART4_IRQ), /*!< UART4 global Interrupt */

410

VECTAB_ENTRY(UART5_IRQ), /*!< UART5 global Interrupt */

411

VECTAB_ENTRY(TIM6_IRQ), /*!< TIM6 global Interrupt */

412

VECTAB_ENTRY(TIM7_IRQ), /*!< TIM7 global Interrupt */

413

VECTAB_ENTRY(DMA2_Channel1_IRQ), /*!< DMA2 Channel 1 global Interrupt */

414

VECTAB_ENTRY(DMA2_Channel2_IRQ), /*!< DMA2 Channel 2 global Interrupt */

415

VECTAB_ENTRY(DMA2_Channel3_IRQ), /*!< DMA2 Channel 3 global Interrupt */

416

VECTAB_ENTRY(DMA2_Channel4_IRQ), /*!< DMA2 Channel 4 global Interrupt */

417

VECTAB_ENTRY(DMA2_Channel5_IRQ), /*!< DMA2 Channel 5 global Interrupt */

418

VECTAB_ENTRY(ETH_IRQ), /*!< Ethernet global Interrupt */

419

VECTAB_ENTRY(ETH_WKUP_IRQ), /*!< Ethernet Wakeup through EXTI line Interrupt */

420

VECTAB_ENTRY(CAN2_TX_IRQ), /*!< CAN2 TX Interrupt */

421

VECTAB_ENTRY(CAN2_RX0_IRQ), /*!< CAN2 RX0 Interrupt */

422

VECTAB_ENTRY(CAN2_RX1_IRQ), /*!< CAN2 RX1 Interrupt */

423

VECTAB_ENTRY(CAN2_SCE_IRQ), /*!< CAN2 SCE Interrupt */

424

VECTAB_ENTRY(OTG_FS_IRQ), /*!< USB OTG FS global Interrupt */

425

#endif /* STM32F10X_CL */

426

};

427