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192.168.1.100 / T103 / 1f884588077ad3476b9c91cbb0ee9ee0332bbb68 / . / src / bsp / lk / platform / stm32f2xx / CMSIS / stm32f2xx.h
blob: 69382cc41c7ae93decc80f3ad94740b49614a729 [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +0800[diff] [blame^]1/**
2 ******************************************************************************
3 * @file stm32f2xx.h
4 * @author MCD Application Team
5 * @version V1.1.3
6 * @date 05-March-2012
7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
8 * This file contains all the peripheral register's definitions, bits
9 * definitions and memory mapping for STM32F2xx devices.
10 *
11 * The file is the unique include file that the application programmer
12 * is using in the C source code, usually in main.c. This file contains:
13 * - Configuration section that allows to select:
14 * - The device used in the target application
15 * - To use or not the peripheral’s drivers in application code(i.e.
16 * code will be based on direct access to peripheral’s registers
17 * rather than drivers API), this option is controlled by
18 * "#define USE_STDPERIPH_DRIVER"
19 * - To change few application-specific parameters such as the HSE
20 * crystal frequency
21 * - Data structures and the address mapping for all peripherals
22 * - Peripheral's registers declarations and bits definition
23 * - Macros to access peripheral’s registers hardware
24 *
25 ******************************************************************************
26 * @attention
27 *
28 * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
29 *
30 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
31 * You may not use this file except in compliance with the License.
32 * You may obtain a copy of the License at:
33 *
34 * http://www.st.com/software_license_agreement_liberty_v2
35 *
36 * Unless required by applicable law or agreed to in writing, software
37 * distributed under the License is distributed on an "AS IS" BASIS,
38 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
39 * See the License for the specific language governing permissions and
40 * limitations under the License.
41 *
42 ******************************************************************************
43 */
44
45/** @addtogroup CMSIS
46 * @{
47 */
48
49/** @addtogroup stm32f2xx
50 * @{
51 */
52
53#ifndef __STM32F2xx_H
54#define __STM32F2xx_H
55
56#ifdef __cplusplus
57 extern "C" {
58#endif /* __cplusplus */
59
60/** @addtogroup Library_configuration_section
61 * @{
62 */
63
64/* Uncomment the line below according to the target STM32 device used in your
65 application
66 */
67
68#if !defined (STM32F2XX)
69 #define STM32F2XX
70#endif
71
72/* Tip: To avoid modifying this file each time you need to switch between these
73 devices, you can define the device in your toolchain compiler preprocessor.
74 */
75
76#if !defined (STM32F2XX)
77 #error "Please select first the target STM32F2XX device used in your application (in stm32f2xx.h file)"
78#endif
79
80#if !defined (USE_STDPERIPH_DRIVER)
81/**
82 * @brief Comment the line below if you will not use the peripherals drivers.
83 In this case, these drivers will not be included and the application code will
84 be based on direct access to peripherals registers
85 */
86 /*#define USE_STDPERIPH_DRIVER*/
87#endif /* USE_STDPERIPH_DRIVER */
88
89/**
90 * @brief In the following line adjust the value of External High Speed oscillator (HSE)
91 used in your application
92
93 Tip: To avoid modifying this file each time you need to use different HSE, you
94 can define the HSE value in your toolchain compiler preprocessor.
95 */
96#if !defined (HSE_VALUE)
97 #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
98#endif /* HSE_VALUE */
99
100/**
101 * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
102 Timeout value
103 */
104#if !defined (HSE_STARTUP_TIMEOUT)
105 #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
106#endif /* HSE_STARTUP_TIMEOUT */
107
108#if !defined (HSI_VALUE)
109 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
110#endif /* HSI_VALUE */
111
112/**
113 * @brief STM32F2XX Standard Peripherals Library version number V1.1.3
114 */
115#define __STM32F2XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
116#define __STM32F2XX_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
117#define __STM32F2XX_STDPERIPH_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
118#define __STM32F2XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
119#define __STM32F2XX_STDPERIPH_VERSION ((__STM32F2XX_STDPERIPH_VERSION_MAIN << 24)\
120 |(__STM32F2XX_STDPERIPH_VERSION_SUB1 << 16)\
121 |(__STM32F2XX_STDPERIPH_VERSION_SUB2 << 8)\
122 |(__STM32F2XX_STDPERIPH_VERSION_RC))
123
124/**
125 * @}
126 */
127
128/** @addtogroup Configuration_section_for_CMSIS
129 * @{
130 */
131
132/**
133 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
134 */
135#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
136#define __MPU_PRESENT 1 /*!< STM32F2XX provides an MPU */
137#define __NVIC_PRIO_BITS 4 /*!< STM32F2XX uses 4 Bits for the Priority Levels */
138#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
139
140/**
141 * @brief STM32F2XX Interrupt Number Definition, according to the selected device
142 * in @ref Library_configuration_section
143 */
144typedef enum IRQn
145{
146/****** Cortex-M3 Processor Exceptions Numbers ****************************************************************/
147 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
148 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
149 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
150 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
151 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
152 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
153 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
154 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
155/****** STM32 specific Interrupt Numbers **********************************************************************/
156 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
157 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
158 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
159 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
160 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
161 RCC_IRQn = 5, /*!< RCC global Interrupt */
162 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
163 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
164 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
165 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
166 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
167 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
168 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
169 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
170 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
171 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
172 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
173 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
174 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
175 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
176 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
177 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
178 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
179 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
180 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
181 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
182 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
183 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
184 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
185 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
186 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
187 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
188 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
189 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
190 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
191 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
192 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
193 USART1_IRQn = 37, /*!< USART1 global Interrupt */
194 USART2_IRQn = 38, /*!< USART2 global Interrupt */
195 USART3_IRQn = 39, /*!< USART3 global Interrupt */
196 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
197 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
198 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
199 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
200 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
201 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
202 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
203 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
204 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
205 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
206 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
207 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
208 UART4_IRQn = 52, /*!< UART4 global Interrupt */
209 UART5_IRQn = 53, /*!< UART5 global Interrupt */
210 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
211 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
212 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
213 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
214 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
215 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
216 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
217 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
218 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
219 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
220 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
221 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
222 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
223 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
224 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
225 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
226 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
227 USART6_IRQn = 71, /*!< USART6 global interrupt */
228 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
229 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
230 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
231 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
232 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
233 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
234 DCMI_IRQn = 78, /*!< DCMI global interrupt */
235 CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
236 HASH_RNG_IRQn = 80 /*!< Hash and Rng global interrupt */
237} IRQn_Type;
238
239/**
240 * @}
241 */
242
243#if ARM_CPU_CORTEX_M3
244#include "core_cm3.h"
245#elif ARM_CPU_CORTEX_M4
246#include "core_cm4.h"
247#endif
248#include "system_stm32f2xx.h"
249#include <stdint.h>
250
251/* CA - Quieting the periph lib build */
252#define assert_param(x)
253/** @addtogroup Exported_types
254 * @{
255 */
256/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
257typedef int32_t s32;
258typedef int16_t s16;
259typedef int8_t s8;
260
261typedef const int32_t sc32; /*!< Read Only */
262typedef const int16_t sc16; /*!< Read Only */
263typedef const int8_t sc8; /*!< Read Only */
264
265typedef __IO int32_t vs32;
266typedef __IO int16_t vs16;
267typedef __IO int8_t vs8;
268
269typedef __I int32_t vsc32; /*!< Read Only */
270typedef __I int16_t vsc16; /*!< Read Only */
271typedef __I int8_t vsc8; /*!< Read Only */
272
273typedef uint32_t u32;
274typedef uint16_t u16;
275typedef uint8_t u8;
276
277typedef const uint32_t uc32; /*!< Read Only */
278typedef const uint16_t uc16; /*!< Read Only */
279typedef const uint8_t uc8; /*!< Read Only */
280
281typedef __IO uint32_t vu32;
282typedef __IO uint16_t vu16;
283typedef __IO uint8_t vu8;
284
285typedef __I uint32_t vuc32; /*!< Read Only */
286typedef __I uint16_t vuc16; /*!< Read Only */
287typedef __I uint8_t vuc8; /*!< Read Only */
288
289typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
290
291typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
292#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
293
294typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
295
296/**
297 * @}
298 */
299
300/** @addtogroup Peripheral_registers_structures
301 * @{
302 */
303
304/**
305 * @brief Analog to Digital Converter
306 */
307
308typedef struct
309{
310 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
311 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
312 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
313 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
314 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
315 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
316 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
317 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
318 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
319 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
320 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
321 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
322 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
323 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
324 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
325 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
326 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
327 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
328 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
329 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
330} ADC_TypeDef;
331
332typedef struct
333{
334 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
335 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
336 __IO uint32_t CDR; /*!< ADC common regular data register for dual
337 AND triple modes, Address offset: ADC1 base address + 0x308 */
338} ADC_Common_TypeDef;
339
340
341/**
342 * @brief Controller Area Network TxMailBox
343 */
344
345typedef struct
346{
347 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
348 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
349 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
350 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
351} CAN_TxMailBox_TypeDef;
352
353/**
354 * @brief Controller Area Network FIFOMailBox
355 */
356
357typedef struct
358{
359 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
360 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
361 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
362 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
363} CAN_FIFOMailBox_TypeDef;
364
365/**
366 * @brief Controller Area Network FilterRegister
367 */
368
369typedef struct
370{
371 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
372 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
373} CAN_FilterRegister_TypeDef;
374
375/**
376 * @brief Controller Area Network
377 */
378
379typedef struct
380{
381 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
382 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
383 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
384 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
385 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
386 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
387 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
388 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
389 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
390 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
391 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
392 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
393 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
394 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
395 uint32_t RESERVED2; /*!< Reserved, 0x208 */
396 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
397 uint32_t RESERVED3; /*!< Reserved, 0x210 */
398 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
399 uint32_t RESERVED4; /*!< Reserved, 0x218 */
400 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
401 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
402 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
403} CAN_TypeDef;
404
405/**
406 * @brief CRC calculation unit
407 */
408
409typedef struct
410{
411 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
412 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
413 uint8_t RESERVED0; /*!< Reserved, 0x05 */
414 uint16_t RESERVED1; /*!< Reserved, 0x06 */
415 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
416} CRC_TypeDef;
417
418/**
419 * @brief Digital to Analog Converter
420 */
421
422typedef struct
423{
424 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
425 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
426 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
427 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
428 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
429 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
430 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
431 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
432 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
433 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
434 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
435 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
436 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
437 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
438} DAC_TypeDef;
439
440/**
441 * @brief Debug MCU
442 */
443
444typedef struct
445{
446 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
447 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
448 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
449 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
450}DBGMCU_TypeDef;
451
452/**
453 * @brief DCMI
454 */
455
456typedef struct
457{
458 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
459 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
460 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
461 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
462 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
463 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
464 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
465 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
466 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
467 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
468 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
469} DCMI_TypeDef;
470
471/**
472 * @brief DMA Controller
473 */
474
475typedef struct
476{
477 __IO uint32_t CR; /*!< DMA stream x configuration register */
478 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
479 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
480 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
481 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
482 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
483} DMA_Stream_TypeDef;
484
485typedef struct
486{
487 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
488 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
489 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
490 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
491} DMA_TypeDef;
492
493/**
494 * @brief Ethernet MAC
495 */
496
497typedef struct
498{
499 __IO uint32_t MACCR;
500 __IO uint32_t MACFFR;
501 __IO uint32_t MACHTHR;
502 __IO uint32_t MACHTLR;
503 __IO uint32_t MACMIIAR;
504 __IO uint32_t MACMIIDR;
505 __IO uint32_t MACFCR;
506 __IO uint32_t MACVLANTR; /* 8 */
507 uint32_t RESERVED0[2];
508 __IO uint32_t MACRWUFFR; /* 11 */
509 __IO uint32_t MACPMTCSR;
510 uint32_t RESERVED1[2];
511 __IO uint32_t MACSR; /* 15 */
512 __IO uint32_t MACIMR;
513 __IO uint32_t MACA0HR;
514 __IO uint32_t MACA0LR;
515 __IO uint32_t MACA1HR;
516 __IO uint32_t MACA1LR;
517 __IO uint32_t MACA2HR;
518 __IO uint32_t MACA2LR;
519 __IO uint32_t MACA3HR;
520 __IO uint32_t MACA3LR; /* 24 */
521 uint32_t RESERVED2[40];
522 __IO uint32_t MMCCR; /* 65 */
523 __IO uint32_t MMCRIR;
524 __IO uint32_t MMCTIR;
525 __IO uint32_t MMCRIMR;
526 __IO uint32_t MMCTIMR; /* 69 */
527 uint32_t RESERVED3[14];
528 __IO uint32_t MMCTGFSCCR; /* 84 */
529 __IO uint32_t MMCTGFMSCCR;
530 uint32_t RESERVED4[5];
531 __IO uint32_t MMCTGFCR;
532 uint32_t RESERVED5[10];
533 __IO uint32_t MMCRFCECR;
534 __IO uint32_t MMCRFAECR;
535 uint32_t RESERVED6[10];
536 __IO uint32_t MMCRGUFCR;
537 uint32_t RESERVED7[334];
538 __IO uint32_t PTPTSCR;
539 __IO uint32_t PTPSSIR;
540 __IO uint32_t PTPTSHR;
541 __IO uint32_t PTPTSLR;
542 __IO uint32_t PTPTSHUR;
543 __IO uint32_t PTPTSLUR;
544 __IO uint32_t PTPTSAR;
545 __IO uint32_t PTPTTHR;
546 __IO uint32_t PTPTTLR;
547 __IO uint32_t RESERVED8;
548 __IO uint32_t PTPTSSR; /* added for STM32F2xx */
549 uint32_t RESERVED9[565];
550 __IO uint32_t DMABMR;
551 __IO uint32_t DMATPDR;
552 __IO uint32_t DMARPDR;
553 __IO uint32_t DMARDLAR;
554 __IO uint32_t DMATDLAR;
555 __IO uint32_t DMASR;
556 __IO uint32_t DMAOMR;
557 __IO uint32_t DMAIER;
558 __IO uint32_t DMAMFBOCR;
559 __IO uint32_t DMARSWTR; /* added for STM32F2xx */
560 uint32_t RESERVED10[8];
561 __IO uint32_t DMACHTDR;
562 __IO uint32_t DMACHRDR;
563 __IO uint32_t DMACHTBAR;
564 __IO uint32_t DMACHRBAR;
565} ETH_TypeDef;
566
567/**
568 * @brief External Interrupt/Event Controller
569 */
570
571typedef struct
572{
573 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
574 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
575 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
576 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
577 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
578 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
579} EXTI_TypeDef;
580
581/**
582 * @brief FLASH Registers
583 */
584
585typedef struct
586{
587 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
588 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
589 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
590 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
591 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
592 __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */
593} FLASH_TypeDef;
594
595/**
596 * @brief Flexible Static Memory Controller
597 */
598
599typedef struct
600{
601 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
602} FSMC_Bank1_TypeDef;
603
604/**
605 * @brief Flexible Static Memory Controller Bank1E
606 */
607
608typedef struct
609{
610 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
611} FSMC_Bank1E_TypeDef;
612
613/**
614 * @brief Flexible Static Memory Controller Bank2
615 */
616
617typedef struct
618{
619 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
620 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
621 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
622 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
623 uint32_t RESERVED0; /*!< Reserved, 0x70 */
624 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
625} FSMC_Bank2_TypeDef;
626
627/**
628 * @brief Flexible Static Memory Controller Bank3
629 */
630
631typedef struct
632{
633 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
634 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
635 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
636 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
637 uint32_t RESERVED0; /*!< Reserved, 0x90 */
638 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
639} FSMC_Bank3_TypeDef;
640
641/**
642 * @brief Flexible Static Memory Controller Bank4
643 */
644
645typedef struct
646{
647 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
648 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
649 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
650 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
651 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
652} FSMC_Bank4_TypeDef;
653
654/**
655 * @brief General Purpose I/O
656 */
657
658typedef struct
659{
660 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
661 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
662 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
663 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
664 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
665 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
666 __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
667 __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
668 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
669 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
670} GPIO_TypeDef;
671
672/**
673 * @brief System configuration controller
674 */
675
676typedef struct
677{
678 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
679 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
680 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
681 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
682 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
683} SYSCFG_TypeDef;
684
685/**
686 * @brief Inter-integrated Circuit Interface
687 */
688
689typedef struct
690{
691 __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
692 uint16_t RESERVED0; /*!< Reserved, 0x02 */
693 __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
694 uint16_t RESERVED1; /*!< Reserved, 0x06 */
695 __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
696 uint16_t RESERVED2; /*!< Reserved, 0x0A */
697 __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
698 uint16_t RESERVED3; /*!< Reserved, 0x0E */
699 __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */
700 uint16_t RESERVED4; /*!< Reserved, 0x12 */
701 __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
702 uint16_t RESERVED5; /*!< Reserved, 0x16 */
703 __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
704 uint16_t RESERVED6; /*!< Reserved, 0x1A */
705 __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
706 uint16_t RESERVED7; /*!< Reserved, 0x1E */
707 __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
708 uint16_t RESERVED8; /*!< Reserved, 0x22 */
709} I2C_TypeDef;
710
711/**
712 * @brief Independent WATCHDOG
713 */
714
715typedef struct
716{
717 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
718 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
719 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
720 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
721} IWDG_TypeDef;
722
723/**
724 * @brief Power Control
725 */
726
727typedef struct
728{
729 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
730 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
731} PWR_TypeDef;
732
733/**
734 * @brief Reset and Clock Control
735 */
736
737typedef struct
738{
739 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
740 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
741 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
742 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
743 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
744 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
745 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
746 uint32_t RESERVED0; /*!< Reserved, 0x1C */
747 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
748 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
749 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
750 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
751 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
752 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
753 uint32_t RESERVED2; /*!< Reserved, 0x3C */
754 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
755 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
756 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
757 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
758 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
759 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
760 uint32_t RESERVED4; /*!< Reserved, 0x5C */
761 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
762 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
763 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
764 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
765 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
766 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
767 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
768 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
769} RCC_TypeDef;
770
771/**
772 * @brief Real-Time Clock
773 */
774
775typedef struct
776{
777 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
778 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
779 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
780 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
781 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
782 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
783 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
784 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
785 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
786 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
787 uint32_t RESERVED1; /*!< Reserved, 0x28 */
788 uint32_t RESERVED2; /*!< Reserved, 0x2C */
789 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
790 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
791 uint32_t RESERVED3; /*!< Reserved, 0x38 */
792 uint32_t RESERVED4; /*!< Reserved, 0x3C */
793 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
794 uint32_t RESERVED5; /*!< Reserved, 0x44 */
795 uint32_t RESERVED6; /*!< Reserved, 0x48 */
796 uint32_t RESERVED7; /*!< Reserved, 0x4C */
797 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
798 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
799 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
800 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
801 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
802 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
803 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
804 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
805 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
806 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
807 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
808 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
809 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
810 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
811 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
812 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
813 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
814 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
815 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
816 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
817} RTC_TypeDef;
818
819/**
820 * @brief SD host Interface
821 */
822
823typedef struct
824{
825 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
826 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
827 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
828 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
829 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
830 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
831 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
832 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
833 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
834 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
835 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
836 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
837 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
838 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
839 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
840 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
841 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
842 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
843 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
844 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
845} SDIO_TypeDef;
846
847/**
848 * @brief Serial Peripheral Interface
849 */
850
851typedef struct
852{
853 __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
854 uint16_t RESERVED0; /*!< Reserved, 0x02 */
855 __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
856 uint16_t RESERVED1; /*!< Reserved, 0x06 */
857 __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */
858 uint16_t RESERVED2; /*!< Reserved, 0x0A */
859 __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
860 uint16_t RESERVED3; /*!< Reserved, 0x0E */
861 __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
862 uint16_t RESERVED4; /*!< Reserved, 0x12 */
863 __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
864 uint16_t RESERVED5; /*!< Reserved, 0x16 */
865 __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
866 uint16_t RESERVED6; /*!< Reserved, 0x1A */
867 __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
868 uint16_t RESERVED7; /*!< Reserved, 0x1E */
869 __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
870 uint16_t RESERVED8; /*!< Reserved, 0x22 */
871} SPI_TypeDef;
872
873/**
874 * @brief TIM
875 */
876
877typedef struct
878{
879 __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
880 uint16_t RESERVED0; /*!< Reserved, 0x02 */
881 __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
882 uint16_t RESERVED1; /*!< Reserved, 0x06 */
883 __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
884 uint16_t RESERVED2; /*!< Reserved, 0x0A */
885 __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
886 uint16_t RESERVED3; /*!< Reserved, 0x0E */
887 __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
888 uint16_t RESERVED4; /*!< Reserved, 0x12 */
889 __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
890 uint16_t RESERVED5; /*!< Reserved, 0x16 */
891 __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
892 uint16_t RESERVED6; /*!< Reserved, 0x1A */
893 __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
894 uint16_t RESERVED7; /*!< Reserved, 0x1E */
895 __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
896 uint16_t RESERVED8; /*!< Reserved, 0x22 */
897 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
898 __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
899 uint16_t RESERVED9; /*!< Reserved, 0x2A */
900 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
901 __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
902 uint16_t RESERVED10; /*!< Reserved, 0x32 */
903 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
904 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
905 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
906 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
907 __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
908 uint16_t RESERVED11; /*!< Reserved, 0x46 */
909 __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
910 uint16_t RESERVED12; /*!< Reserved, 0x4A */
911 __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
912 uint16_t RESERVED13; /*!< Reserved, 0x4E */
913 __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
914 uint16_t RESERVED14; /*!< Reserved, 0x52 */
915} TIM_TypeDef;
916
917/**
918 * @brief Universal Synchronous Asynchronous Receiver Transmitter
919 */
920
921typedef struct
922{
923 __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */
924 uint16_t RESERVED0; /*!< Reserved, 0x02 */
925 __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */
926 uint16_t RESERVED1; /*!< Reserved, 0x06 */
927 __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
928 uint16_t RESERVED2; /*!< Reserved, 0x0A */
929 __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
930 uint16_t RESERVED3; /*!< Reserved, 0x0E */
931 __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
932 uint16_t RESERVED4; /*!< Reserved, 0x12 */
933 __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
934 uint16_t RESERVED5; /*!< Reserved, 0x16 */
935 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
936 uint16_t RESERVED6; /*!< Reserved, 0x1A */
937} USART_TypeDef;
938
939/**
940 * @brief Window WATCHDOG
941 */
942
943typedef struct
944{
945 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
946 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
947 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
948} WWDG_TypeDef;
949
950/**
951 * @brief Crypto Processor
952 */
953
954typedef struct
955{
956 __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
957 __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
958 __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
959 __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
960 __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
961 __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
962 __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
963 __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
964 __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
965 __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
966 __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
967 __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
968 __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
969 __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
970 __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
971 __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
972 __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
973 __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
974 __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
975 __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
976} CRYP_TypeDef;
977
978/**
979 * @brief HASH
980 */
981
982typedef struct
983{
984 __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
985 __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
986 __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
987 __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
988 __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
989 __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
990 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
991 __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */
992} HASH_TypeDef;
993
994/**
995 * @brief HASH
996 */
997
998typedef struct
999{
1000 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1001 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1002 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1003} RNG_TypeDef;
1004
1005/**
1006 * @}
1007 */
1008
1009/** @addtogroup Peripheral_memory_map
1010 * @{
1011 */
1012
1013#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
1014#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
1015#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
1016
1017#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
1018#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
1019
1020#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
1021
1022/*!< Peripheral memory map */
1023#define APB1PERIPH_BASE PERIPH_BASE
1024#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
1025#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
1026#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
1027
1028/*!< APB1 peripherals */
1029#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
1030#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
1031#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
1032#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
1033#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
1034#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
1035#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
1036#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
1037#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
1038#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
1039#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
1040#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
1041#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
1042#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
1043#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
1044#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
1045#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
1046#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
1047#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
1048#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
1049#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
1050#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
1051#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
1052#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
1053#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
1054
1055/*!< APB2 peripherals */
1056#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
1057#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
1058#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
1059#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
1060#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
1061#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
1062#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
1063#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
1064#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
1065#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
1066#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
1067#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
1068#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
1069#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
1070#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
1071
1072/*!< AHB1 peripherals */
1073#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
1074#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
1075#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
1076#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
1077#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
1078#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
1079#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
1080#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
1081#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
1082#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
1083#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
1084#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
1085#define BKPSRAM_BASE (AHB1PERIPH_BASE + 0x4000)
1086#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
1087#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
1088#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
1089#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
1090#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
1091#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
1092#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
1093#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
1094#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
1095#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
1096#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
1097#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
1098#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
1099#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
1100#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
1101#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
1102#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
1103#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
1104#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
1105#define ETH_MAC_BASE (ETH_BASE)
1106#define ETH_MMC_BASE (ETH_BASE + 0x0100)
1107#define ETH_PTP_BASE (ETH_BASE + 0x0700)
1108#define ETH_DMA_BASE (ETH_BASE + 0x1000)
1109
1110/*!< AHB2 peripherals */
1111#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
1112#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)
1113#define HASH_BASE (AHB2PERIPH_BASE + 0x60400)
1114#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
1115
1116/*!< FSMC Bankx registers base address */
1117#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
1118#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
1119#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
1120#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
1121#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
1122
1123/* Debug MCU registers base address */
1124#define DBGMCU_BASE ((uint32_t )0xE0042000)
1125
1126/**
1127 * @}
1128 */
1129
1130/** @addtogroup Peripheral_declaration
1131 * @{
1132 */
1133#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1134#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1135#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1136#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1137#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1138#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1139#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1140#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1141#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1142#define RTC ((RTC_TypeDef *) RTC_BASE)
1143#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1144#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1145#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1146#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1147#define USART2 ((USART_TypeDef *) USART2_BASE)
1148#define USART3 ((USART_TypeDef *) USART3_BASE)
1149#define UART4 ((USART_TypeDef *) UART4_BASE)
1150#define UART5 ((USART_TypeDef *) UART5_BASE)
1151#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1152#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1153#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1154#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1155#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1156#define PWR ((PWR_TypeDef *) PWR_BASE)
1157#define DAC ((DAC_TypeDef *) DAC_BASE)
1158#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1159#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1160#define USART1 ((USART_TypeDef *) USART1_BASE)
1161#define USART6 ((USART_TypeDef *) USART6_BASE)
1162#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1163#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1164#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1165#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1166#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1167#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1168#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1169#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1170#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1171#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1172#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1173#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1174#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1175#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1176#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1177#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1178#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1179#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1180#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1181#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1182#define CRC ((CRC_TypeDef *) CRC_BASE)
1183#define RCC ((RCC_TypeDef *) RCC_BASE)
1184#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1185#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1186#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1187#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1188#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1189#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1190#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1191#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1192#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1193#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1194#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1195#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1196#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1197#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1198#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1199#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1200#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1201#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1202#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1203#define ETH ((ETH_TypeDef *) ETH_BASE)
1204#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1205#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
1206#define HASH ((HASH_TypeDef *) HASH_BASE)
1207#define RNG ((RNG_TypeDef *) RNG_BASE)
1208#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1209#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1210#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
1211#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
1212#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
1213#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1214
1215/**
1216 * @}
1217 */
1218
1219/** @addtogroup Exported_constants
1220 * @{
1221 */
1222
1223 /** @addtogroup Peripheral_Registers_Bits_Definition
1224 * @{
1225 */
1226
1227/******************************************************************************/
1228/* Peripheral Registers_Bits_Definition */
1229/******************************************************************************/
1230
1231/******************************************************************************/
1232/* */
1233/* Analog to Digital Converter */
1234/* */
1235/******************************************************************************/
1236/******************** Bit definition for ADC_SR register ********************/
1237#define ADC_SR_AWD ((uint8_t)0x01) /*!<Analog watchdog flag */
1238#define ADC_SR_EOC ((uint8_t)0x02) /*!<End of conversion */
1239#define ADC_SR_JEOC ((uint8_t)0x04) /*!<Injected channel end of conversion */
1240#define ADC_SR_JSTRT ((uint8_t)0x08) /*!<Injected channel Start flag */
1241#define ADC_SR_STRT ((uint8_t)0x10) /*!<Regular channel Start flag */
1242#define ADC_SR_OVR ((uint8_t)0x20) /*!<Overrun flag */
1243
1244/******************* Bit definition for ADC_CR1 register ********************/
1245#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1246#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1247#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1248#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1249#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1250#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1251#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
1252#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
1253#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
1254#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
1255#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
1256#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
1257#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
1258#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
1259#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1260#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
1261#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
1262#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
1263#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
1264#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
1265#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
1266#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1267#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1268#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
1269
1270/******************* Bit definition for ADC_CR2 register ********************/
1271#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
1272#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
1273#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
1274#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
1275#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
1276#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
1277#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1278#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
1279#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
1280#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
1281#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
1282#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1283#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1284#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1285#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
1286#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1287#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1288#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1289#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
1290#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
1291#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1292#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
1293#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
1294#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
1295
1296/****************** Bit definition for ADC_SMPR1 register *******************/
1297#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1298#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1299#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1300#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1301#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1302#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
1303#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
1304#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
1305#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1306#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
1307#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
1308#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
1309#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1310#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
1311#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
1312#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
1313#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1314#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
1315#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
1316#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
1317#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1318#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1319#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1320#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1321#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1322#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
1323#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
1324#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
1325#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1326#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
1327#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
1328#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
1329#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1330#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1331#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1332#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
1333
1334/****************** Bit definition for ADC_SMPR2 register *******************/
1335#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1336#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1337#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1338#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1339#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1340#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
1341#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
1342#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
1343#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1344#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
1345#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
1346#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
1347#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1348#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
1349#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
1350#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
1351#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1352#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
1353#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
1354#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
1355#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1356#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1357#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1358#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1359#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1360#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
1361#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
1362#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
1363#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1364#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
1365#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
1366#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
1367#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1368#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1369#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1370#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
1371#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1372#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
1373#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
1374#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
1375
1376/****************** Bit definition for ADC_JOFR1 register *******************/
1377#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */
1378
1379/****************** Bit definition for ADC_JOFR2 register *******************/
1380#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */
1381
1382/****************** Bit definition for ADC_JOFR3 register *******************/
1383#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */
1384
1385/****************** Bit definition for ADC_JOFR4 register *******************/
1386#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */
1387
1388/******************* Bit definition for ADC_HTR register ********************/
1389#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */
1390
1391/******************* Bit definition for ADC_LTR register ********************/
1392#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */
1393
1394/******************* Bit definition for ADC_SQR1 register *******************/
1395#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1396#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1397#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1398#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1399#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1400#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1401#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1402#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1403#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1404#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1405#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1406#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1407#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1408#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1409#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1410#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1411#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1412#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1413#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1414#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1415#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1416#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1417#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1418#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1419#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
1420#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1421#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1422#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1423#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
1424
1425/******************* Bit definition for ADC_SQR2 register *******************/
1426#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1427#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1428#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1429#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1430#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1431#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1432#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1433#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1434#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1435#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1436#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1437#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1438#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1439#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1440#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1441#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1442#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1443#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1444#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1445#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1446#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1447#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1448#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1449#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1450#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1451#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1452#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1453#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1454#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
1455#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
1456#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1457#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
1458#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
1459#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
1460#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
1461#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
1462
1463/******************* Bit definition for ADC_SQR3 register *******************/
1464#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1465#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1466#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1467#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1468#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1469#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1470#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1471#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1472#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1473#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1474#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1475#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1476#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1477#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1478#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1479#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1480#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1481#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1482#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1483#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1484#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1485#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1486#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1487#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1488#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1489#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1490#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1491#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1492#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
1493#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
1494#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1495#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
1496#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
1497#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
1498#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
1499#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
1500
1501/******************* Bit definition for ADC_JSQR register *******************/
1502#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1503#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1504#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1505#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1506#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1507#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1508#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1509#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1510#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1511#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1512#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1513#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1514#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1515#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1516#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1517#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1518#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1519#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1520#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1521#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1522#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1523#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1524#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1525#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1526#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
1527#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1528#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1529
1530/******************* Bit definition for ADC_JDR1 register *******************/
1531#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
1532
1533/******************* Bit definition for ADC_JDR2 register *******************/
1534#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
1535
1536/******************* Bit definition for ADC_JDR3 register *******************/
1537#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
1538
1539/******************* Bit definition for ADC_JDR4 register *******************/
1540#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
1541
1542/******************** Bit definition for ADC_DR register ********************/
1543#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
1544#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
1545
1546/******************* Bit definition for ADC_CSR register ********************/
1547#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
1548#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
1549#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
1550#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
1551#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
1552#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
1553#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
1554#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
1555#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
1556#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
1557#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
1558#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
1559#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
1560#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
1561#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
1562#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
1563#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
1564#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
1565
1566/******************* Bit definition for ADC_CCR register ********************/
1567#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1568#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1569#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1570#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1571#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1572#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1573#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1574#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
1575#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
1576#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
1577#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
1578#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
1579#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1580#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
1581#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
1582#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
1583#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
1584#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
1585#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
1586#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
1587
1588/******************* Bit definition for ADC_CDR register ********************/
1589#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
1590#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
1591
1592/******************************************************************************/
1593/* */
1594/* Controller Area Network */
1595/* */
1596/******************************************************************************/
1597/*!<CAN control and status registers */
1598/******************* Bit definition for CAN_MCR register ********************/
1599#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */
1600#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */
1601#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */
1602#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */
1603#define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */
1604#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */
1605#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */
1606#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */
1607#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */
1608
1609/******************* Bit definition for CAN_MSR register ********************/
1610#define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */
1611#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */
1612#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */
1613#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */
1614#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */
1615#define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */
1616#define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */
1617#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */
1618#define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */
1619
1620/******************* Bit definition for CAN_TSR register ********************/
1621#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
1622#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
1623#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
1624#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
1625#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
1626#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
1627#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
1628#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
1629#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
1630#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
1631#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
1632#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
1633#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
1634#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
1635#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
1636#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
1637
1638#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
1639#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
1640#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
1641#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
1642
1643#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
1644#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
1645#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
1646#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
1647
1648/******************* Bit definition for CAN_RF0R register *******************/
1649#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */
1650#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */
1651#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */
1652#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */
1653
1654/******************* Bit definition for CAN_RF1R register *******************/
1655#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */
1656#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */
1657#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */
1658#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */
1659
1660/******************** Bit definition for CAN_IER register *******************/
1661#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
1662#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
1663#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
1664#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
1665#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
1666#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
1667#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
1668#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
1669#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
1670#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
1671#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
1672#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
1673#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
1674#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
1675
1676/******************** Bit definition for CAN_ESR register *******************/
1677#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
1678#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
1679#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
1680
1681#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
1682#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
1683#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
1684#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
1685
1686#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
1687#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
1688
1689/******************* Bit definition for CAN_BTR register ********************/
1690#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
1691#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
1692#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
1693#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
1694#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
1695#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
1696
1697/*!<Mailbox registers */
1698/****************** Bit definition for CAN_TI0R register ********************/
1699#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1700#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1701#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1702#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1703#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1704
1705/****************** Bit definition for CAN_TDT0R register *******************/
1706#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1707#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1708#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1709
1710/****************** Bit definition for CAN_TDL0R register *******************/
1711#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1712#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1713#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1714#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1715
1716/****************** Bit definition for CAN_TDH0R register *******************/
1717#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1718#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1719#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1720#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1721
1722/******************* Bit definition for CAN_TI1R register *******************/
1723#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1724#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1725#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1726#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1727#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1728
1729/******************* Bit definition for CAN_TDT1R register ******************/
1730#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1731#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1732#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1733
1734/******************* Bit definition for CAN_TDL1R register ******************/
1735#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1736#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1737#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1738#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1739
1740/******************* Bit definition for CAN_TDH1R register ******************/
1741#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1742#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1743#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1744#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1745
1746/******************* Bit definition for CAN_TI2R register *******************/
1747#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1748#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1749#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1750#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
1751#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1752
1753/******************* Bit definition for CAN_TDT2R register ******************/
1754#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1755#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1756#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1757
1758/******************* Bit definition for CAN_TDL2R register ******************/
1759#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1760#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1761#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1762#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1763
1764/******************* Bit definition for CAN_TDH2R register ******************/
1765#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1766#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1767#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1768#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1769
1770/******************* Bit definition for CAN_RI0R register *******************/
1771#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1772#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1773#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1774#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1775
1776/******************* Bit definition for CAN_RDT0R register ******************/
1777#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1778#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
1779#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1780
1781/******************* Bit definition for CAN_RDL0R register ******************/
1782#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1783#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1784#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1785#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1786
1787/******************* Bit definition for CAN_RDH0R register ******************/
1788#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1789#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1790#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1791#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1792
1793/******************* Bit definition for CAN_RI1R register *******************/
1794#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1795#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1796#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
1797#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1798
1799/******************* Bit definition for CAN_RDT1R register ******************/
1800#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1801#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
1802#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1803
1804/******************* Bit definition for CAN_RDL1R register ******************/
1805#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1806#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1807#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1808#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1809
1810/******************* Bit definition for CAN_RDH1R register ******************/
1811#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1812#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1813#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1814#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1815
1816/*!<CAN filter registers */
1817/******************* Bit definition for CAN_FMR register ********************/
1818#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
1819
1820/******************* Bit definition for CAN_FM1R register *******************/
1821#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */
1822#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */
1823#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */
1824#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */
1825#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */
1826#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */
1827#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */
1828#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */
1829#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */
1830#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */
1831#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */
1832#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */
1833#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */
1834#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */
1835#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */
1836
1837/******************* Bit definition for CAN_FS1R register *******************/
1838#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */
1839#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */
1840#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */
1841#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */
1842#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */
1843#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */
1844#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */
1845#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */
1846#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */
1847#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */
1848#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */
1849#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */
1850#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */
1851#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */
1852#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */
1853
1854/****************** Bit definition for CAN_FFA1R register *******************/
1855#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */
1856#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
1857#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
1858#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
1859#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
1860#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
1861#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
1862#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
1863#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
1864#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
1865#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
1866#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
1867#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
1868#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
1869#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
1870
1871/******************* Bit definition for CAN_FA1R register *******************/
1872#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */
1873#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */
1874#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */
1875#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */
1876#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */
1877#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */
1878#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */
1879#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */
1880#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */
1881#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */
1882#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */
1883#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */
1884#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */
1885#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */
1886#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */
1887
1888/******************* Bit definition for CAN_F0R1 register *******************/
1889#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
1890#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
1891#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
1892#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
1893#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
1894#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
1895#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
1896#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
1897#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
1898#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
1899#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
1900#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
1901#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
1902#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
1903#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
1904#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
1905#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
1906#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
1907#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
1908#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
1909#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
1910#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
1911#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
1912#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
1913#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
1914#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
1915#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
1916#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
1917#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
1918#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
1919#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
1920#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
1921
1922/******************* Bit definition for CAN_F1R1 register *******************/
1923#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
1924#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
1925#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
1926#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
1927#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
1928#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
1929#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
1930#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
1931#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
1932#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
1933#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
1934#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
1935#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
1936#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
1937#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
1938#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
1939#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
1940#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
1941#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
1942#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
1943#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
1944#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
1945#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
1946#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
1947#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
1948#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
1949#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
1950#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
1951#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
1952#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
1953#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
1954#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
1955
1956/******************* Bit definition for CAN_F2R1 register *******************/
1957#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
1958#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
1959#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
1960#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
1961#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
1962#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
1963#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
1964#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
1965#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
1966#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
1967#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
1968#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
1969#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
1970#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
1971#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
1972#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
1973#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
1974#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
1975#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
1976#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
1977#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
1978#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
1979#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
1980#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
1981#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
1982#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
1983#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
1984#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
1985#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
1986#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
1987#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
1988#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
1989
1990/******************* Bit definition for CAN_F3R1 register *******************/
1991#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
1992#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
1993#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
1994#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
1995#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
1996#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
1997#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
1998#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
1999#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2000#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2001#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2002#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2003#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2004#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2005#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2006#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2007#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2008#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2009#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2010#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2011#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2012#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2013#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2014#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2015#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2016#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2017#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2018#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2019#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2020#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2021#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2022#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2023
2024/******************* Bit definition for CAN_F4R1 register *******************/
2025#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2026#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2027#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2028#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2029#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2030#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2031#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2032#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2033#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2034#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2035#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2036#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2037#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2038#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2039#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2040#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2041#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2042#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2043#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2044#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2045#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2046#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2047#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2048#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2049#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2050#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2051#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2052#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2053#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2054#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2055#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2056#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2057
2058/******************* Bit definition for CAN_F5R1 register *******************/
2059#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2060#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2061#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2062#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2063#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2064#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2065#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2066#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2067#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2068#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2069#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2070#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2071#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2072#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2073#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2074#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2075#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2076#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2077#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2078#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2079#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2080#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2081#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2082#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2083#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2084#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2085#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2086#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2087#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2088#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2089#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2090#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2091
2092/******************* Bit definition for CAN_F6R1 register *******************/
2093#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2094#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2095#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2096#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2097#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2098#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2099#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2100#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2101#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2102#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2103#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2104#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2105#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2106#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2107#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2108#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2109#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2110#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2111#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2112#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2113#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2114#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2115#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2116#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2117#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2118#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2119#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2120#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2121#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2122#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2123#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2124#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2125
2126/******************* Bit definition for CAN_F7R1 register *******************/
2127#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2128#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2129#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2130#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2131#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2132#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2133#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2134#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2135#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2136#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2137#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2138#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2139#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2140#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2141#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2142#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2143#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2144#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2145#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2146#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2147#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2148#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2149#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2150#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2151#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2152#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2153#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2154#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2155#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2156#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2157#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2158#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2159
2160/******************* Bit definition for CAN_F8R1 register *******************/
2161#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2162#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2163#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2164#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2165#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2166#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2167#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2168#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2169#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2170#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2171#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2172#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2173#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2174#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2175#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2176#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2177#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2178#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2179#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2180#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2181#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2182#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2183#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2184#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2185#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2186#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2187#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2188#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2189#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2190#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2191#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2192#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2193
2194/******************* Bit definition for CAN_F9R1 register *******************/
2195#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2196#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2197#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2198#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2199#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2200#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2201#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2202#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2203#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2204#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2205#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2206#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2207#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2208#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2209#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2210#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2211#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2212#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2213#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2214#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2215#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2216#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2217#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2218#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2219#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2220#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2221#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2222#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2223#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2224#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2225#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2226#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2227
2228/******************* Bit definition for CAN_F10R1 register ******************/
2229#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2230#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2231#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2232#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2233#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2234#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2235#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2236#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2237#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2238#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2239#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2240#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2241#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2242#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2243#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2244#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2245#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2246#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2247#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2248#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2249#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2250#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2251#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2252#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2253#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2254#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2255#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2256#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2257#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2258#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2259#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2260#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2261
2262/******************* Bit definition for CAN_F11R1 register ******************/
2263#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2264#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2265#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2266#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2267#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2268#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2269#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2270#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2271#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2272#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2273#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2274#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2275#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2276#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2277#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2278#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2279#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2280#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2281#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2282#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2283#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2284#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2285#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2286#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2287#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2288#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2289#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2290#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2291#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2292#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2293#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2294#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2295
2296/******************* Bit definition for CAN_F12R1 register ******************/
2297#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2298#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2299#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2300#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2301#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2302#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2303#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2304#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2305#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2306#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2307#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2308#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2309#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2310#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2311#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2312#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2313#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2314#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2315#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2316#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2317#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2318#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2319#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2320#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2321#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2322#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2323#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2324#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2325#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2326#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2327#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2328#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2329
2330/******************* Bit definition for CAN_F13R1 register ******************/
2331#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2332#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2333#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2334#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2335#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2336#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2337#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2338#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2339#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2340#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2341#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2342#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2343#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2344#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2345#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2346#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2347#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2348#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2349#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2350#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2351#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2352#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2353#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2354#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2355#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2356#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2357#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2358#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2359#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2360#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2361#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2362#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2363
2364/******************* Bit definition for CAN_F0R2 register *******************/
2365#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2366#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2367#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2368#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2369#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2370#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2371#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2372#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2373#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2374#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2375#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2376#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2377#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2378#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2379#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2380#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2381#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2382#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2383#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2384#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2385#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2386#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2387#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2388#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2389#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2390#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2391#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2392#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2393#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2394#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2395#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2396#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2397
2398/******************* Bit definition for CAN_F1R2 register *******************/
2399#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2400#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2401#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2402#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2403#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2404#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2405#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2406#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2407#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2408#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2409#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2410#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2411#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2412#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2413#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2414#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2415#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2416#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2417#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2418#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2419#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2420#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2421#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2422#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2423#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2424#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2425#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2426#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2427#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2428#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2429#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2430#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2431
2432/******************* Bit definition for CAN_F2R2 register *******************/
2433#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2434#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2435#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2436#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2437#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2438#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2439#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2440#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2441#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2442#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2443#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2444#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2445#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2446#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2447#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2448#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2449#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2450#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2451#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2452#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2453#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2454#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2455#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2456#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2457#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2458#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2459#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2460#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2461#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2462#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2463#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2464#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2465
2466/******************* Bit definition for CAN_F3R2 register *******************/
2467#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2468#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2469#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2470#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2471#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2472#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2473#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2474#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2475#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2476#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2477#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2478#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2479#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2480#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2481#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2482#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2483#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2484#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2485#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2486#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2487#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2488#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2489#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2490#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2491#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2492#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2493#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2494#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2495#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2496#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2497#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2498#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2499
2500/******************* Bit definition for CAN_F4R2 register *******************/
2501#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2502#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2503#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2504#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2505#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2506#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2507#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2508#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2509#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2510#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2511#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2512#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2513#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2514#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2515#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2516#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2517#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2518#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2519#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2520#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2521#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2522#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2523#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2524#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2525#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2526#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2527#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2528#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2529#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2530#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2531#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2532#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2533
2534/******************* Bit definition for CAN_F5R2 register *******************/
2535#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2536#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2537#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2538#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2539#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2540#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2541#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2542#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2543#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2544#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2545#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2546#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2547#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2548#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2549#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2550#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2551#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2552#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2553#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2554#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2555#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2556#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2557#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2558#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2559#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2560#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2561#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2562#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2563#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2564#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2565#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2566#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2567
2568/******************* Bit definition for CAN_F6R2 register *******************/
2569#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2570#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2571#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2572#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2573#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2574#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2575#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2576#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2577#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2578#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2579#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2580#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2581#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2582#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2583#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2584#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2585#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2586#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2587#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2588#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2589#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2590#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2591#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2592#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2593#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2594#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2595#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2596#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2597#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2598#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2599#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2600#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2601
2602/******************* Bit definition for CAN_F7R2 register *******************/
2603#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2604#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2605#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2606#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2607#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2608#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2609#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2610#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2611#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2612#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2613#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2614#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2615#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2616#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2617#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2618#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2619#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2620#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2621#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2622#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2623#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2624#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2625#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2626#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2627#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2628#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2629#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2630#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2631#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2632#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2633#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2634#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2635
2636/******************* Bit definition for CAN_F8R2 register *******************/
2637#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2638#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2639#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2640#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2641#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2642#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2643#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2644#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2645#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2646#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2647#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2648#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2649#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2650#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2651#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2652#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2653#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2654#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2655#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2656#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2657#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2658#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2659#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2660#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2661#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2662#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2663#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2664#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2665#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2666#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2667#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2668#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2669
2670/******************* Bit definition for CAN_F9R2 register *******************/
2671#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2672#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2673#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2674#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2675#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2676#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2677#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2678#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2679#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2680#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2681#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2682#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2683#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2684#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2685#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2686#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2687#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2688#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2689#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2690#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2691#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2692#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2693#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2694#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2695#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2696#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2697#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2698#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2699#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2700#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2701#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2702#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2703
2704/******************* Bit definition for CAN_F10R2 register ******************/
2705#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2706#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2707#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2708#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2709#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2710#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2711#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2712#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2713#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2714#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2715#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2716#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2717#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2718#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2719#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2720#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2721#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2722#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2723#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2724#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2725#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2726#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2727#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2728#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2729#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2730#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2731#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2732#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2733#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2734#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2735#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2736#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2737
2738/******************* Bit definition for CAN_F11R2 register ******************/
2739#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2740#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2741#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2742#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2743#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2744#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2745#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2746#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2747#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2748#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2749#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2750#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2751#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2752#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2753#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2754#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2755#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2756#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2757#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2758#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2759#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2760#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2761#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2762#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2763#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2764#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2765#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2766#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2767#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2768#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2769#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2770#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2771
2772/******************* Bit definition for CAN_F12R2 register ******************/
2773#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2774#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2775#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2776#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2777#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2778#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2779#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2780#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2781#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2782#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2783#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2784#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2785#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2786#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2787#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2788#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2789#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2790#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2791#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2792#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2793#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2794#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2795#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2796#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2797#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2798#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2799#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2800#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2801#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2802#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2803#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2804#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2805
2806/******************* Bit definition for CAN_F13R2 register ******************/
2807#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2808#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2809#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2810#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2811#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2812#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2813#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2814#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2815#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2816#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2817#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2818#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2819#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2820#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2821#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2822#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2823#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2824#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2825#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2826#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2827#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2828#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2829#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2830#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2831#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2832#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2833#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2834#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2835#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2836#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2837#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2838#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2839
2840/******************************************************************************/
2841/* */
2842/* CRC calculation unit */
2843/* */
2844/******************************************************************************/
2845/******************* Bit definition for CRC_DR register *********************/
2846#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
2847
2848
2849/******************* Bit definition for CRC_IDR register ********************/
2850#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
2851
2852
2853/******************** Bit definition for CRC_CR register ********************/
2854#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */
2855
2856/******************************************************************************/
2857/* */
2858/* Crypto Processor */
2859/* */
2860/******************************************************************************/
2861/******************* Bits definition for CRYP_CR register ********************/
2862#define CRYP_CR_ALGODIR ((uint32_t)0x00000004)
2863
2864#define CRYP_CR_ALGOMODE ((uint32_t)0x00000038)
2865#define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008)
2866#define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010)
2867#define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020)
2868#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
2869#define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008)
2870#define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010)
2871#define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018)
2872#define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020)
2873#define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028)
2874#define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030)
2875#define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038)
2876
2877#define CRYP_CR_DATATYPE ((uint32_t)0x000000C0)
2878#define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040)
2879#define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080)
2880#define CRYP_CR_KEYSIZE ((uint32_t)0x00000300)
2881#define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100)
2882#define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200)
2883#define CRYP_CR_FFLUSH ((uint32_t)0x00004000)
2884#define CRYP_CR_CRYPEN ((uint32_t)0x00008000)
2885/****************** Bits definition for CRYP_SR register *********************/
2886#define CRYP_SR_IFEM ((uint32_t)0x00000001)
2887#define CRYP_SR_IFNF ((uint32_t)0x00000002)
2888#define CRYP_SR_OFNE ((uint32_t)0x00000004)
2889#define CRYP_SR_OFFU ((uint32_t)0x00000008)
2890#define CRYP_SR_BUSY ((uint32_t)0x00000010)
2891/****************** Bits definition for CRYP_DMACR register ******************/
2892#define CRYP_DMACR_DIEN ((uint32_t)0x00000001)
2893#define CRYP_DMACR_DOEN ((uint32_t)0x00000002)
2894/***************** Bits definition for CRYP_IMSCR register ******************/
2895#define CRYP_IMSCR_INIM ((uint32_t)0x00000001)
2896#define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002)
2897/****************** Bits definition for CRYP_RISR register *******************/
2898#define CRYP_RISR_OUTRIS ((uint32_t)0x00000001)
2899#define CRYP_RISR_INRIS ((uint32_t)0x00000002)
2900/****************** Bits definition for CRYP_MISR register *******************/
2901#define CRYP_MISR_INMIS ((uint32_t)0x00000001)
2902#define CRYP_MISR_OUTMIS ((uint32_t)0x00000002)
2903
2904/******************************************************************************/
2905/* */
2906/* Digital to Analog Converter */
2907/* */
2908/******************************************************************************/
2909/******************** Bit definition for DAC_CR register ********************/
2910#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
2911#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
2912#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
2913
2914#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
2915#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
2916#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
2917#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
2918
2919#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
2920#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
2921#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
2922
2923#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
2924#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
2925#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
2926#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
2927#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
2928
2929#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
2930#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun interrupt enable >*/
2931
2932#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
2933#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
2934#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
2935
2936#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
2937#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
2938#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
2939#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
2940
2941#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
2942#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
2943#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
2944
2945#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
2946#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
2947#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
2948#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
2949#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
2950
2951#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
2952#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun interrupt enable >*/
2953
2954/***************** Bit definition for DAC_SWTRIGR register ******************/
2955#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */
2956#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */
2957
2958/***************** Bit definition for DAC_DHR12R1 register ******************/
2959#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
2960
2961/***************** Bit definition for DAC_DHR12L1 register ******************/
2962#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
2963
2964/****************** Bit definition for DAC_DHR8R1 register ******************/
2965#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
2966
2967/***************** Bit definition for DAC_DHR12R2 register ******************/
2968#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
2969
2970/***************** Bit definition for DAC_DHR12L2 register ******************/
2971#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
2972
2973/****************** Bit definition for DAC_DHR8R2 register ******************/
2974#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
2975
2976/***************** Bit definition for DAC_DHR12RD register ******************/
2977#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
2978#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
2979
2980/***************** Bit definition for DAC_DHR12LD register ******************/
2981#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
2982#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
2983
2984/****************** Bit definition for DAC_DHR8RD register ******************/
2985#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
2986#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
2987
2988/******************* Bit definition for DAC_DOR1 register *******************/
2989#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */
2990
2991/******************* Bit definition for DAC_DOR2 register *******************/
2992#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
2993
2994/******************** Bit definition for DAC_SR register ********************/
2995#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
2996#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
2997
2998/******************************************************************************/
2999/* */
3000/* Debug MCU */
3001/* */
3002/******************************************************************************/
3003
3004/******************************************************************************/
3005/* */
3006/* DCMI */
3007/* */
3008/******************************************************************************/
3009/******************** Bits definition for DCMI_CR register ******************/
3010#define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
3011#define DCMI_CR_CM ((uint32_t)0x00000002)
3012#define DCMI_CR_CROP ((uint32_t)0x00000004)
3013#define DCMI_CR_JPEG ((uint32_t)0x00000008)
3014#define DCMI_CR_ESS ((uint32_t)0x00000010)
3015#define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
3016#define DCMI_CR_HSPOL ((uint32_t)0x00000040)
3017#define DCMI_CR_VSPOL ((uint32_t)0x00000080)
3018#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
3019#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
3020#define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
3021#define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
3022#define DCMI_CR_CRE ((uint32_t)0x00001000)
3023#define DCMI_CR_ENABLE ((uint32_t)0x00004000)
3024
3025/******************** Bits definition for DCMI_SR register ******************/
3026#define DCMI_SR_HSYNC ((uint32_t)0x00000001)
3027#define DCMI_SR_VSYNC ((uint32_t)0x00000002)
3028#define DCMI_SR_FNE ((uint32_t)0x00000004)
3029
3030/******************** Bits definition for DCMI_RISR register ****************/
3031#define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
3032#define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
3033#define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
3034#define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
3035#define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
3036
3037/******************** Bits definition for DCMI_IER register *****************/
3038#define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
3039#define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
3040#define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
3041#define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
3042#define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
3043
3044/******************** Bits definition for DCMI_MISR register ****************/
3045#define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
3046#define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
3047#define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
3048#define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
3049#define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
3050
3051/******************** Bits definition for DCMI_ICR register *****************/
3052#define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
3053#define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
3054#define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
3055#define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
3056#define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
3057
3058/******************************************************************************/
3059/* */
3060/* DMA Controller */
3061/* */
3062/******************************************************************************/
3063/******************** Bits definition for DMA_SxCR register *****************/
3064#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
3065#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
3066#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
3067#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
3068#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
3069#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
3070#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
3071#define DMA_SxCR_PBURST ((uint32_t)0x00600000)
3072#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
3073#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
3074#define DMA_SxCR_ACK ((uint32_t)0x00100000)
3075#define DMA_SxCR_CT ((uint32_t)0x00080000)
3076#define DMA_SxCR_DBM ((uint32_t)0x00040000)
3077#define DMA_SxCR_PL ((uint32_t)0x00030000)
3078#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
3079#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
3080#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
3081#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
3082#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
3083#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
3084#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
3085#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
3086#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
3087#define DMA_SxCR_MINC ((uint32_t)0x00000400)
3088#define DMA_SxCR_PINC ((uint32_t)0x00000200)
3089#define DMA_SxCR_CIRC ((uint32_t)0x00000100)
3090#define DMA_SxCR_DIR ((uint32_t)0x000000C0)
3091#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
3092#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
3093#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
3094#define DMA_SxCR_TCIE ((uint32_t)0x00000010)
3095#define DMA_SxCR_HTIE ((uint32_t)0x00000008)
3096#define DMA_SxCR_TEIE ((uint32_t)0x00000004)
3097#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
3098#define DMA_SxCR_EN ((uint32_t)0x00000001)
3099
3100/******************** Bits definition for DMA_SxCNDTR register **************/
3101#define DMA_SxNDT ((uint32_t)0x0000FFFF)
3102#define DMA_SxNDT_0 ((uint32_t)0x00000001)
3103#define DMA_SxNDT_1 ((uint32_t)0x00000002)
3104#define DMA_SxNDT_2 ((uint32_t)0x00000004)
3105#define DMA_SxNDT_3 ((uint32_t)0x00000008)
3106#define DMA_SxNDT_4 ((uint32_t)0x00000010)
3107#define DMA_SxNDT_5 ((uint32_t)0x00000020)
3108#define DMA_SxNDT_6 ((uint32_t)0x00000040)
3109#define DMA_SxNDT_7 ((uint32_t)0x00000080)
3110#define DMA_SxNDT_8 ((uint32_t)0x00000100)
3111#define DMA_SxNDT_9 ((uint32_t)0x00000200)
3112#define DMA_SxNDT_10 ((uint32_t)0x00000400)
3113#define DMA_SxNDT_11 ((uint32_t)0x00000800)
3114#define DMA_SxNDT_12 ((uint32_t)0x00001000)
3115#define DMA_SxNDT_13 ((uint32_t)0x00002000)
3116#define DMA_SxNDT_14 ((uint32_t)0x00004000)
3117#define DMA_SxNDT_15 ((uint32_t)0x00008000)
3118
3119/******************** Bits definition for DMA_SxFCR register ****************/
3120#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
3121#define DMA_SxFCR_FS ((uint32_t)0x00000038)
3122#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
3123#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
3124#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
3125#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
3126#define DMA_SxFCR_FTH ((uint32_t)0x00000003)
3127#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
3128#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
3129
3130/******************** Bits definition for DMA_LISR register *****************/
3131#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
3132#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
3133#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
3134#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
3135#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
3136#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
3137#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
3138#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
3139#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
3140#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
3141#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
3142#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
3143#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
3144#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
3145#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
3146#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
3147#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
3148#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
3149#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
3150#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
3151
3152/******************** Bits definition for DMA_HISR register *****************/
3153#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
3154#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
3155#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
3156#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
3157#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
3158#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
3159#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
3160#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
3161#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
3162#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
3163#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
3164#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
3165#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
3166#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
3167#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
3168#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
3169#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
3170#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
3171#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
3172#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
3173
3174/******************** Bits definition for DMA_LIFCR register ****************/
3175#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
3176#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
3177#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
3178#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
3179#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
3180#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
3181#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
3182#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
3183#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
3184#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
3185#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
3186#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
3187#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
3188#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
3189#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
3190#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
3191#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
3192#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
3193#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
3194#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
3195
3196/******************** Bits definition for DMA_HIFCR register ****************/
3197#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
3198#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
3199#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
3200#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
3201#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
3202#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
3203#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
3204#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
3205#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
3206#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
3207#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
3208#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
3209#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
3210#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
3211#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
3212#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
3213#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
3214#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
3215#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
3216#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
3217
3218/******************************************************************************/
3219/* */
3220/* External Interrupt/Event Controller */
3221/* */
3222/******************************************************************************/
3223/******************* Bit definition for EXTI_IMR register *******************/
3224#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
3225#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
3226#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
3227#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
3228#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
3229#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
3230#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
3231#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
3232#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
3233#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
3234#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
3235#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
3236#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
3237#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
3238#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
3239#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
3240#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
3241#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
3242#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
3243#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
3244
3245/******************* Bit definition for EXTI_EMR register *******************/
3246#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
3247#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
3248#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
3249#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
3250#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
3251#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
3252#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
3253#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
3254#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
3255#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
3256#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
3257#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
3258#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
3259#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
3260#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
3261#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
3262#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
3263#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
3264#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
3265#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
3266
3267/****************** Bit definition for EXTI_RTSR register *******************/
3268#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
3269#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
3270#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
3271#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
3272#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
3273#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
3274#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
3275#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
3276#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
3277#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
3278#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
3279#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
3280#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
3281#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
3282#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
3283#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
3284#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
3285#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
3286#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
3287#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
3288
3289/****************** Bit definition for EXTI_FTSR register *******************/
3290#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
3291#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
3292#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
3293#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
3294#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
3295#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
3296#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
3297#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
3298#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
3299#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
3300#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
3301#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
3302#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
3303#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
3304#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
3305#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
3306#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
3307#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
3308#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
3309#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
3310
3311/****************** Bit definition for EXTI_SWIER register ******************/
3312#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
3313#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
3314#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
3315#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
3316#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
3317#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
3318#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
3319#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
3320#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
3321#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
3322#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
3323#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
3324#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
3325#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
3326#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
3327#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
3328#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
3329#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
3330#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
3331#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
3332
3333/******************* Bit definition for EXTI_PR register ********************/
3334#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
3335#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
3336#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
3337#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
3338#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
3339#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
3340#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
3341#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
3342#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
3343#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
3344#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
3345#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
3346#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
3347#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
3348#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
3349#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
3350#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
3351#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
3352#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
3353#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
3354
3355/******************************************************************************/
3356/* */
3357/* FLASH */
3358/* */
3359/******************************************************************************/
3360/******************* Bits definition for FLASH_ACR register *****************/
3361#define FLASH_ACR_LATENCY ((uint32_t)0x00000007)
3362#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
3363#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
3364#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
3365#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
3366#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
3367#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
3368#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
3369#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
3370
3371#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
3372#define FLASH_ACR_ICEN ((uint32_t)0x00000200)
3373#define FLASH_ACR_DCEN ((uint32_t)0x00000400)
3374#define FLASH_ACR_ICRST ((uint32_t)0x00000800)
3375#define FLASH_ACR_DCRST ((uint32_t)0x00001000)
3376#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
3377#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
3378
3379/******************* Bits definition for FLASH_SR register ******************/
3380#define FLASH_SR_EOP ((uint32_t)0x00000001)
3381#define FLASH_SR_SOP ((uint32_t)0x00000002)
3382#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
3383#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
3384#define FLASH_SR_PGPERR ((uint32_t)0x00000040)
3385#define FLASH_SR_PGSERR ((uint32_t)0x00000080)
3386#define FLASH_SR_BSY ((uint32_t)0x00010000)
3387
3388/******************* Bits definition for FLASH_CR register ******************/
3389#define FLASH_CR_PG ((uint32_t)0x00000001)
3390#define FLASH_CR_SER ((uint32_t)0x00000002)
3391#define FLASH_CR_MER ((uint32_t)0x00000004)
3392#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
3393#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
3394#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
3395#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
3396#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
3397#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
3398#define FLASH_CR_STRT ((uint32_t)0x00010000)
3399#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
3400#define FLASH_CR_LOCK ((uint32_t)0x80000000)
3401
3402/******************* Bits definition for FLASH_OPTCR register ***************/
3403#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
3404#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
3405#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
3406#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
3407#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
3408#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
3409#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
3410#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
3411#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
3412#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
3413#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
3414#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
3415#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
3416#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
3417#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
3418#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
3419#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
3420#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
3421#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
3422#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
3423#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
3424#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
3425#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
3426#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
3427#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
3428#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
3429#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
3430#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
3431
3432/******************************************************************************/
3433/* */
3434/* Flexible Static Memory Controller */
3435/* */
3436/******************************************************************************/
3437/****************** Bit definition for FSMC_BCR1 register *******************/
3438#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3439#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3440
3441#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3442#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3443#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3444
3445#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3446#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3447#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3448
3449#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3450#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3451#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3452#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3453#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3454#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3455#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3456#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3457#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3458#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3459
3460/****************** Bit definition for FSMC_BCR2 register *******************/
3461#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3462#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3463
3464#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3465#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3466#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3467
3468#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3469#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3470#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3471
3472#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3473#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3474#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3475#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3476#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3477#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3478#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3479#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3480#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3481#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3482
3483/****************** Bit definition for FSMC_BCR3 register *******************/
3484#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3485#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3486
3487#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3488#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3489#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3490
3491#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3492#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3493#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3494
3495#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3496#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3497#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit. */
3498#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3499#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3500#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3501#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3502#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3503#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3504#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3505
3506/****************** Bit definition for FSMC_BCR4 register *******************/
3507#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3508#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3509
3510#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3511#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3512#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3513
3514#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3515#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3516#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3517
3518#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3519#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3520#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3521#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3522#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3523#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3524#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3525#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3526#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3527#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3528
3529/****************** Bit definition for FSMC_BTR1 register ******************/
3530#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3531#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3532#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3533#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3534#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3535
3536#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3537#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3538#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3539#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3540#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3541
3542#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
3543#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3544#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3545#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3546#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3547#define FSMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3548#define FSMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3549#define FSMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3550#define FSMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3551
3552#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3553#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3554#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3555#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3556#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3557
3558#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3559#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3560#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3561#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3562#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3563
3564#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3565#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3566#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3567#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3568#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3569
3570#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3571#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3572#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3573
3574/****************** Bit definition for FSMC_BTR2 register *******************/
3575#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3576#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3577#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3578#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3579#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3580
3581#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3582#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3583#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3584#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3585#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3586
3587#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
3588#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3589#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3590#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3591#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3592#define FSMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3593#define FSMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3594#define FSMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3595#define FSMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3596
3597#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3598#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3599#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3600#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3601#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3602
3603#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3604#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3605#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3606#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3607#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3608
3609#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3610#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3611#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3612#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3613#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3614
3615#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3616#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3617#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3618
3619/******************* Bit definition for FSMC_BTR3 register *******************/
3620#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3621#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3622#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3623#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3624#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3625
3626#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3627#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3628#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3629#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3630#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3631
3632#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
3633#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3634#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3635#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3636#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3637#define FSMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3638#define FSMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3639#define FSMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3640#define FSMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3641
3642#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3643#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3644#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3645#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3646#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3647
3648#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3649#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3650#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3651#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3652#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3653
3654#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3655#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3656#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3657#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3658#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3659
3660#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3661#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3662#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3663
3664/****************** Bit definition for FSMC_BTR4 register *******************/
3665#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3666#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3667#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3668#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3669#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3670
3671#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3672#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3673#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3674#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3675#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3676
3677#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
3678#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3679#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3680#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3681#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3682#define FSMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3683#define FSMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3684#define FSMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3685#define FSMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3686
3687#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3688#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3689#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3690#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3691#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3692
3693#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3694#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3695#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3696#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3697#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3698
3699#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3700#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3701#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3702#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3703#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3704
3705#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3706#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3707#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3708
3709/****************** Bit definition for FSMC_BWTR1 register ******************/
3710#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3711#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3712#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3713#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3714#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3715
3716#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3717#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3718#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3719#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3720#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3721
3722#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
3723#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3724#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3725#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3726#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3727#define FSMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3728#define FSMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3729#define FSMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3730#define FSMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3731
3732#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3733#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3734#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3735#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3736#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3737
3738#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3739#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3740#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3741#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3742#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3743
3744#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3745#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3746#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3747
3748/****************** Bit definition for FSMC_BWTR2 register ******************/
3749#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3750#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3751#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3752#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3753#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3754
3755#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3756#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3757#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3758#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3759#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3760
3761#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
3762#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3763#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3764#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3765#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3766#define FSMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3767#define FSMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3768#define FSMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3769#define FSMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3770
3771#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3772#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3773#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
3774#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3775#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3776
3777#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3778#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3779#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3780#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3781#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3782
3783#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3784#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3785#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3786
3787/****************** Bit definition for FSMC_BWTR3 register ******************/
3788#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3789#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3790#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3791#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3792#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3793
3794#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3795#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3796#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3797#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3798#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3799
3800#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
3801#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3802#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3803#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3804#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3805#define FSMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3806#define FSMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3807#define FSMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3808#define FSMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3809
3810#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3811#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3812#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3813#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3814#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3815
3816#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3817#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3818#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3819#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3820#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3821
3822#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3823#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3824#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3825
3826/****************** Bit definition for FSMC_BWTR4 register ******************/
3827#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3828#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3829#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3830#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3831#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3832
3833#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3834#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3835#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3836#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3837#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3838
3839#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
3840#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3841#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3842#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3843#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3844#define FSMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3845#define FSMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3846#define FSMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3847#define FSMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3848
3849#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3850#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3851#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3852#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3853#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3854
3855#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3856#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3857#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3858#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3859#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3860
3861#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3862#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3863#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3864
3865/****************** Bit definition for FSMC_PCR2 register *******************/
3866#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
3867#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
3868#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
3869
3870#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
3871#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3872#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3873
3874#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
3875
3876#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
3877#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
3878#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
3879#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
3880#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
3881
3882#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
3883#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
3884#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
3885#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
3886#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
3887
3888#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
3889#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
3890#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
3891#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
3892
3893/****************** Bit definition for FSMC_PCR3 register *******************/
3894#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
3895#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
3896#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
3897
3898#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
3899#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3900#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3901
3902#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
3903
3904#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
3905#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
3906#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
3907#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
3908#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
3909
3910#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
3911#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
3912#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
3913#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
3914#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
3915
3916#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
3917#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
3918#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
3919#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
3920
3921/****************** Bit definition for FSMC_PCR4 register *******************/
3922#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
3923#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
3924#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
3925
3926#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
3927#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3928#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3929
3930#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
3931
3932#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
3933#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
3934#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
3935#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
3936#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
3937
3938#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
3939#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
3940#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
3941#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
3942#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
3943
3944#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
3945#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
3946#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
3947#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
3948
3949/******************* Bit definition for FSMC_SR2 register *******************/
3950#define FSMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
3951#define FSMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
3952#define FSMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
3953#define FSMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
3954#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
3955#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
3956#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
3957
3958/******************* Bit definition for FSMC_SR3 register *******************/
3959#define FSMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
3960#define FSMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
3961#define FSMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
3962#define FSMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
3963#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
3964#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
3965#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
3966
3967/******************* Bit definition for FSMC_SR4 register *******************/
3968#define FSMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
3969#define FSMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
3970#define FSMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
3971#define FSMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
3972#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
3973#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
3974#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
3975
3976/****************** Bit definition for FSMC_PMEM2 register ******************/
3977#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
3978#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3979#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3980#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3981#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3982#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3983#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
3984#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
3985#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
3986
3987#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
3988#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3989#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3990#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3991#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3992#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3993#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3994#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3995#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3996
3997#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
3998#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3999#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4000#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4001#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4002#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4003#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4004#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4005#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4006
4007#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
4008#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4009#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4010#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4011#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4012#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4013#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4014#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4015#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4016
4017/****************** Bit definition for FSMC_PMEM3 register ******************/
4018#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
4019#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4020#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4021#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4022#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4023#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4024#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4025#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4026#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4027
4028#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
4029#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4030#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4031#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4032#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4033#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4034#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4035#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4036#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4037
4038#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
4039#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4040#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4041#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4042#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4043#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4044#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4045#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4046#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4047
4048#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
4049#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4050#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4051#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4052#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4053#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4054#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4055#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4056#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4057
4058/****************** Bit definition for FSMC_PMEM4 register ******************/
4059#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
4060#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4061#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4062#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4063#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4064#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4065#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4066#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4067#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4068
4069#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
4070#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4071#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4072#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4073#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4074#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4075#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4076#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4077#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4078
4079#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
4080#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4081#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4082#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4083#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4084#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4085#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4086#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4087#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4088
4089#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
4090#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4091#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4092#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4093#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4094#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4095#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4096#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4097#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4098
4099/****************** Bit definition for FSMC_PATT2 register ******************/
4100#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
4101#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4102#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4103#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4104#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4105#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4106#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4107#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4108#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4109
4110#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
4111#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4112#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4113#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4114#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4115#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4116#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4117#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4118#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4119
4120#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
4121#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4122#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4123#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4124#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4125#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4126#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4127#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4128#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4129
4130#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
4131#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4132#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4133#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4134#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4135#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4136#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4137#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4138#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4139
4140/****************** Bit definition for FSMC_PATT3 register ******************/
4141#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
4142#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4143#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4144#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4145#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4146#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4147#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4148#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4149#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4150
4151#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
4152#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4153#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4154#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4155#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4156#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4157#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4158#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4159#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4160
4161#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
4162#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4163#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4164#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4165#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4166#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4167#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4168#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4169#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4170
4171#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
4172#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4173#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4174#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4175#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4176#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4177#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4178#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4179#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4180
4181/****************** Bit definition for FSMC_PATT4 register ******************/
4182#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
4183#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4184#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4185#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4186#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4187#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4188#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4189#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4190#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4191
4192#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
4193#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4194#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4195#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4196#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4197#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4198#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4199#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4200#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4201
4202#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
4203#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4204#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4205#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4206#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4207#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4208#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4209#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4210#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4211
4212#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
4213#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4214#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4215#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4216#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4217#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4218#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4219#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4220#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4221
4222/****************** Bit definition for FSMC_PIO4 register *******************/
4223#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
4224#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4225#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4226#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4227#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4228#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4229#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4230#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4231#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4232
4233#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
4234#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4235#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4236#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4237#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4238#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4239#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4240#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4241#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4242
4243#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
4244#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4245#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4246#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4247#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4248#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4249#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4250#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4251#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4252
4253#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
4254#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4255#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4256#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4257#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4258#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4259#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4260#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4261#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4262
4263/****************** Bit definition for FSMC_ECCR2 register ******************/
4264#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
4265
4266/****************** Bit definition for FSMC_ECCR3 register ******************/
4267#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
4268
4269/******************************************************************************/
4270/* */
4271/* General Purpose I/O */
4272/* */
4273/******************************************************************************/
4274/****************** Bits definition for GPIO_MODER register *****************/
4275#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
4276#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
4277#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
4278
4279#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
4280#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
4281#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
4282
4283#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
4284#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
4285#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
4286
4287#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
4288#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
4289#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
4290
4291#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
4292#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
4293#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
4294
4295#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
4296#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
4297#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
4298
4299#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
4300#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
4301#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
4302
4303#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
4304#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
4305#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
4306
4307#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
4308#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
4309#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
4310
4311#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
4312#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
4313#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
4314
4315#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
4316#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
4317#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
4318
4319#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
4320#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
4321#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
4322
4323#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
4324#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
4325#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
4326
4327#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
4328#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
4329#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
4330
4331#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
4332#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
4333#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
4334
4335#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
4336#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
4337#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
4338
4339/****************** Bits definition for GPIO_OTYPER register ****************/
4340#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
4341#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
4342#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
4343#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
4344#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
4345#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
4346#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
4347#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
4348#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
4349#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
4350#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
4351#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
4352#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
4353#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
4354#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
4355#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
4356
4357/****************** Bits definition for GPIO_OSPEEDR register ***************/
4358#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
4359#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
4360#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
4361
4362#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
4363#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
4364#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
4365
4366#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
4367#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
4368#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
4369
4370#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
4371#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
4372#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
4373
4374#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
4375#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
4376#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
4377
4378#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
4379#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
4380#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
4381
4382#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
4383#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
4384#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
4385
4386#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
4387#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
4388#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
4389
4390#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
4391#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
4392#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
4393
4394#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
4395#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
4396#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
4397
4398#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
4399#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
4400#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
4401
4402#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
4403#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
4404#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
4405
4406#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
4407#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
4408#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
4409
4410#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
4411#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
4412#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
4413
4414#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
4415#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
4416#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
4417
4418#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
4419#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
4420#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
4421
4422/****************** Bits definition for GPIO_PUPDR register *****************/
4423#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
4424#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
4425#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
4426
4427#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
4428#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
4429#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
4430
4431#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
4432#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
4433#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
4434
4435#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
4436#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
4437#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
4438
4439#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
4440#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
4441#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
4442
4443#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
4444#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
4445#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
4446
4447#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
4448#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
4449#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
4450
4451#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
4452#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
4453#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
4454
4455#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
4456#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
4457#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
4458
4459#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
4460#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
4461#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
4462
4463#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
4464#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
4465#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
4466
4467#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
4468#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
4469#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
4470
4471#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
4472#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
4473#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
4474
4475#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
4476#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
4477#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
4478
4479#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
4480#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
4481#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
4482
4483#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
4484#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
4485#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
4486
4487/****************** Bits definition for GPIO_IDR register *******************/
4488#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
4489#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
4490#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
4491#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
4492#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
4493#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
4494#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
4495#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
4496#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
4497#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
4498#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
4499#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
4500#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
4501#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
4502#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
4503#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
4504/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
4505#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
4506#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
4507#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
4508#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
4509#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
4510#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
4511#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
4512#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
4513#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
4514#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
4515#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
4516#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
4517#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
4518#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
4519#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
4520#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
4521
4522/****************** Bits definition for GPIO_ODR register *******************/
4523#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
4524#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
4525#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
4526#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
4527#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
4528#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
4529#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
4530#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
4531#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
4532#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
4533#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
4534#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
4535#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
4536#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
4537#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
4538#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
4539/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
4540#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
4541#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
4542#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
4543#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
4544#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
4545#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
4546#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
4547#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
4548#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
4549#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
4550#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
4551#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
4552#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
4553#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
4554#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
4555#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
4556
4557
4558/****************** Bits definition for GPIO_BSRR register ******************/
4559#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
4560#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
4561#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
4562#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
4563#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
4564#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
4565#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
4566#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
4567#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
4568#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
4569#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
4570#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
4571#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
4572#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
4573#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
4574#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
4575#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
4576#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
4577#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
4578#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
4579#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
4580#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
4581#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
4582#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
4583#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
4584#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
4585#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
4586#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
4587#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
4588#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
4589#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
4590#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
4591
4592/******************************************************************************/
4593/* */
4594/* HASH */
4595/* */
4596/******************************************************************************/
4597/****************** Bits definition for HASH_CR register ********************/
4598#define HASH_CR_INIT ((uint32_t)0x00000004)
4599#define HASH_CR_DMAE ((uint32_t)0x00000008)
4600#define HASH_CR_DATATYPE ((uint32_t)0x00000030)
4601#define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010)
4602#define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020)
4603#define HASH_CR_MODE ((uint32_t)0x00000040)
4604#define HASH_CR_ALGO ((uint32_t)0x00000080)
4605#define HASH_CR_NBW ((uint32_t)0x00000F00)
4606#define HASH_CR_NBW_0 ((uint32_t)0x00000100)
4607#define HASH_CR_NBW_1 ((uint32_t)0x00000200)
4608#define HASH_CR_NBW_2 ((uint32_t)0x00000400)
4609#define HASH_CR_NBW_3 ((uint32_t)0x00000800)
4610#define HASH_CR_DINNE ((uint32_t)0x00001000)
4611#define HASH_CR_LKEY ((uint32_t)0x00010000)
4612
4613/****************** Bits definition for HASH_STR register *******************/
4614#define HASH_STR_NBW ((uint32_t)0x0000001F)
4615#define HASH_STR_NBW_0 ((uint32_t)0x00000001)
4616#define HASH_STR_NBW_1 ((uint32_t)0x00000002)
4617#define HASH_STR_NBW_2 ((uint32_t)0x00000004)
4618#define HASH_STR_NBW_3 ((uint32_t)0x00000008)
4619#define HASH_STR_NBW_4 ((uint32_t)0x00000010)
4620#define HASH_STR_DCAL ((uint32_t)0x00000100)
4621
4622/****************** Bits definition for HASH_IMR register *******************/
4623#define HASH_IMR_DINIM ((uint32_t)0x00000001)
4624#define HASH_IMR_DCIM ((uint32_t)0x00000002)
4625
4626/****************** Bits definition for HASH_SR register ********************/
4627#define HASH_SR_DINIS ((uint32_t)0x00000001)
4628#define HASH_SR_DCIS ((uint32_t)0x00000002)
4629#define HASH_SR_DMAS ((uint32_t)0x00000004)
4630#define HASH_SR_BUSY ((uint32_t)0x00000008)
4631
4632/******************************************************************************/
4633/* */
4634/* Inter-integrated Circuit Interface */
4635/* */
4636/******************************************************************************/
4637/******************* Bit definition for I2C_CR1 register ********************/
4638#define I2C_CR1_PE ((uint16_t)0x0001) /*!<Peripheral Enable */
4639#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!<SMBus Mode */
4640#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!<SMBus Type */
4641#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!<ARP Enable */
4642#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!<PEC Enable */
4643#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!<General Call Enable */
4644#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!<Clock Stretching Disable (Slave mode) */
4645#define I2C_CR1_START ((uint16_t)0x0100) /*!<Start Generation */
4646#define I2C_CR1_STOP ((uint16_t)0x0200) /*!<Stop Generation */
4647#define I2C_CR1_ACK ((uint16_t)0x0400) /*!<Acknowledge Enable */
4648#define I2C_CR1_POS ((uint16_t)0x0800) /*!<Acknowledge/PEC Position (for data reception) */
4649#define I2C_CR1_PEC ((uint16_t)0x1000) /*!<Packet Error Checking */
4650#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!<SMBus Alert */
4651#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!<Software Reset */
4652
4653/******************* Bit definition for I2C_CR2 register ********************/
4654#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
4655#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!<Bit 0 */
4656#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!<Bit 1 */
4657#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!<Bit 2 */
4658#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!<Bit 3 */
4659#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!<Bit 4 */
4660#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!<Bit 5 */
4661
4662#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!<Error Interrupt Enable */
4663#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!<Event Interrupt Enable */
4664#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!<Buffer Interrupt Enable */
4665#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!<DMA Requests Enable */
4666#define I2C_CR2_LAST ((uint16_t)0x1000) /*!<DMA Last Transfer */
4667
4668/******************* Bit definition for I2C_OAR1 register *******************/
4669#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!<Interface Address */
4670#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!<Interface Address */
4671
4672#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!<Bit 0 */
4673#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!<Bit 1 */
4674#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!<Bit 2 */
4675#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!<Bit 3 */
4676#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!<Bit 4 */
4677#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!<Bit 5 */
4678#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!<Bit 6 */
4679#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!<Bit 7 */
4680#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!<Bit 8 */
4681#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!<Bit 9 */
4682
4683#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!<Addressing Mode (Slave mode) */
4684
4685/******************* Bit definition for I2C_OAR2 register *******************/
4686#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!<Dual addressing mode enable */
4687#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!<Interface address */
4688
4689/******************** Bit definition for I2C_DR register ********************/
4690#define I2C_DR_DR ((uint8_t)0xFF) /*!<8-bit Data Register */
4691
4692/******************* Bit definition for I2C_SR1 register ********************/
4693#define I2C_SR1_SB ((uint16_t)0x0001) /*!<Start Bit (Master mode) */
4694#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!<Address sent (master mode)/matched (slave mode) */
4695#define I2C_SR1_BTF ((uint16_t)0x0004) /*!<Byte Transfer Finished */
4696#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!<10-bit header sent (Master mode) */
4697#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!<Stop detection (Slave mode) */
4698#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!<Data Register not Empty (receivers) */
4699#define I2C_SR1_TXE ((uint16_t)0x0080) /*!<Data Register Empty (transmitters) */
4700#define I2C_SR1_BERR ((uint16_t)0x0100) /*!<Bus Error */
4701#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!<Arbitration Lost (master mode) */
4702#define I2C_SR1_AF ((uint16_t)0x0400) /*!<Acknowledge Failure */
4703#define I2C_SR1_OVR ((uint16_t)0x0800) /*!<Overrun/Underrun */
4704#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!<PEC Error in reception */
4705#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!<Timeout or Tlow Error */
4706#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!<SMBus Alert */
4707
4708/******************* Bit definition for I2C_SR2 register ********************/
4709#define I2C_SR2_MSL ((uint16_t)0x0001) /*!<Master/Slave */
4710#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!<Bus Busy */
4711#define I2C_SR2_TRA ((uint16_t)0x0004) /*!<Transmitter/Receiver */
4712#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!<General Call Address (Slave mode) */
4713#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!<SMBus Device Default Address (Slave mode) */
4714#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!<SMBus Host Header (Slave mode) */
4715#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!<Dual Flag (Slave mode) */
4716#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!<Packet Error Checking Register */
4717
4718/******************* Bit definition for I2C_CCR register ********************/
4719#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
4720#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!<Fast Mode Duty Cycle */
4721#define I2C_CCR_FS ((uint16_t)0x8000) /*!<I2C Master Mode Selection */
4722
4723/****************** Bit definition for I2C_TRISE register *******************/
4724#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
4725
4726/******************************************************************************/
4727/* */
4728/* Independent WATCHDOG */
4729/* */
4730/******************************************************************************/
4731/******************* Bit definition for IWDG_KR register ********************/
4732#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */
4733
4734/******************* Bit definition for IWDG_PR register ********************/
4735#define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */
4736#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */
4737#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */
4738#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */
4739
4740/******************* Bit definition for IWDG_RLR register *******************/
4741#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */
4742
4743/******************* Bit definition for IWDG_SR register ********************/
4744#define IWDG_SR_PVU ((uint8_t)0x01) /*!<Watchdog prescaler value update */
4745#define IWDG_SR_RVU ((uint8_t)0x02) /*!<Watchdog counter reload value update */
4746
4747/******************************************************************************/
4748/* */
4749/* Power Control */
4750/* */
4751/******************************************************************************/
4752/******************** Bit definition for PWR_CR register ********************/
4753#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */
4754#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
4755#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
4756#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
4757#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
4758
4759#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
4760#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
4761#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
4762#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
4763
4764/*!< PVD level configuration */
4765#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */
4766#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */
4767#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */
4768#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */
4769#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */
4770#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */
4771#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */
4772#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */
4773
4774#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
4775#define PWR_CR_FPDS ((uint16_t)0x0200) /*!< Flash power down in Stop mode */
4776
4777
4778/******************* Bit definition for PWR_CSR register ********************/
4779#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
4780#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
4781#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
4782#define PWR_CSR_BRR ((uint16_t)0x0008) /*!< Backup regulator ready */
4783#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */
4784#define PWR_CSR_BRE ((uint16_t)0x0200) /*!< Backup regulator enable */
4785
4786/******************************************************************************/
4787/* */
4788/* Reset and Clock Control */
4789/* */
4790/******************************************************************************/
4791/******************** Bit definition for RCC_CR register ********************/
4792#define RCC_CR_HSION ((uint32_t)0x00000001)
4793#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
4794
4795#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
4796#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
4797#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
4798#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
4799#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
4800#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
4801
4802#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
4803#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
4804#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
4805#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
4806#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
4807#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
4808#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
4809#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
4810#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
4811
4812#define RCC_CR_HSEON ((uint32_t)0x00010000)
4813#define RCC_CR_HSERDY ((uint32_t)0x00020000)
4814#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
4815#define RCC_CR_CSSON ((uint32_t)0x00080000)
4816#define RCC_CR_PLLON ((uint32_t)0x01000000)
4817#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
4818#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
4819#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
4820
4821/******************** Bit definition for RCC_PLLCFGR register ***************/
4822#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
4823#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
4824#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
4825#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
4826#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
4827#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
4828#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
4829
4830#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
4831#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
4832#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
4833#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
4834#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
4835#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
4836#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
4837#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
4838#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
4839#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
4840
4841#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
4842#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
4843#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
4844
4845#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
4846#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
4847#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
4848
4849#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
4850#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
4851#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
4852#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
4853#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
4854
4855/******************** Bit definition for RCC_CFGR register ******************/
4856/*!< SW configuration */
4857#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
4858#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
4859#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
4860
4861#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
4862#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
4863#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
4864
4865/*!< SWS configuration */
4866#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
4867#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
4868#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
4869
4870#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
4871#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
4872#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
4873
4874/*!< HPRE configuration */
4875#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
4876#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
4877#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
4878#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
4879#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
4880
4881#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
4882#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
4883#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
4884#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
4885#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
4886#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
4887#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
4888#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
4889#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
4890
4891/*!< PPRE1 configuration */
4892#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
4893#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
4894#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
4895#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
4896
4897#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
4898#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
4899#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
4900#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
4901#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
4902
4903/*!< PPRE2 configuration */
4904#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
4905#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
4906#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
4907#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
4908
4909#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
4910#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
4911#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
4912#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
4913#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
4914
4915/*!< RTCPRE configuration */
4916#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
4917#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
4918#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
4919#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
4920#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
4921#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
4922
4923/*!< MCO1 configuration */
4924#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
4925#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
4926#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
4927
4928#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
4929
4930#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
4931#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
4932#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
4933#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
4934
4935#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
4936#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
4937#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
4938#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
4939
4940#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
4941#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
4942#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
4943
4944/******************** Bit definition for RCC_CIR register *******************/
4945#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
4946#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
4947#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
4948#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
4949#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
4950#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
4951#define RCC_CIR_CSSF ((uint32_t)0x00000080)
4952#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
4953#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
4954#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
4955#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
4956#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
4957#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
4958#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
4959#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
4960#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
4961#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
4962#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
4963#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
4964#define RCC_CIR_CSSC ((uint32_t)0x00800000)
4965
4966/******************** Bit definition for RCC_AHB1RSTR register **************/
4967#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
4968#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
4969#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
4970#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
4971#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
4972#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
4973#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
4974#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
4975#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
4976#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
4977#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
4978#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
4979#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
4980#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
4981
4982/******************** Bit definition for RCC_AHB2RSTR register **************/
4983#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
4984#define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
4985#define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020)
4986 /* maintained for legacy purpose */
4987 #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
4988#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
4989#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
4990
4991/******************** Bit definition for RCC_AHB3RSTR register **************/
4992#define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)
4993
4994/******************** Bit definition for RCC_APB1RSTR register **************/
4995#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
4996#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
4997#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
4998#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
4999#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
5000#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
5001#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
5002#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
5003#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
5004#define RCC_APB1RSTR_WWDGEN ((uint32_t)0x00000800)
5005#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00008000)
5006#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00010000)
5007#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
5008#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
5009#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
5010#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
5011#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
5012#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
5013#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
5014#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
5015#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
5016#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
5017#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
5018
5019/******************** Bit definition for RCC_APB2RSTR register **************/
5020#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
5021#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
5022#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
5023#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
5024#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
5025#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
5026#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
5027#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
5028#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
5029#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
5030#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
5031/* Old SPI1RST bit definition, maintained for legacy purpose */
5032#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
5033
5034/******************** Bit definition for RCC_AHB1ENR register ***************/
5035#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
5036#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
5037#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
5038#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
5039#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
5040#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
5041#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
5042#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
5043#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
5044#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
5045#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
5046#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
5047#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
5048#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
5049#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
5050#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
5051#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
5052#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
5053#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
5054
5055/******************** Bit definition for RCC_AHB2ENR register ***************/
5056#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
5057#define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)
5058#define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)
5059#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
5060#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
5061
5062/******************** Bit definition for RCC_AHB3ENR register ***************/
5063#define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)
5064
5065/******************** Bit definition for RCC_APB1ENR register ***************/
5066#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
5067#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
5068#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
5069#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
5070#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
5071#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
5072#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
5073#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
5074#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
5075#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
5076#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
5077#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
5078#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
5079#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
5080#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
5081#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
5082#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
5083#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
5084#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
5085#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
5086#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
5087#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
5088#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
5089
5090/******************** Bit definition for RCC_APB2ENR register ***************/
5091#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
5092#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
5093#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
5094#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
5095#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
5096#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
5097#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
5098#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
5099#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
5100#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
5101#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
5102#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
5103#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
5104
5105/******************** Bit definition for RCC_AHB1LPENR register *************/
5106#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
5107#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
5108#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
5109#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
5110#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
5111#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
5112#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
5113#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
5114#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
5115#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
5116#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
5117#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
5118#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
5119#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
5120#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
5121#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
5122#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
5123#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
5124#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
5125#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
5126#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
5127#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
5128
5129/******************** Bit definition for RCC_AHB2LPENR register *************/
5130#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
5131#define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)
5132#define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)
5133#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
5134#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
5135
5136/******************** Bit definition for RCC_AHB3LPENR register *************/
5137#define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
5138
5139/******************** Bit definition for RCC_APB1LPENR register *************/
5140#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
5141#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
5142#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
5143#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
5144#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
5145#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
5146#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
5147#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
5148#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
5149#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
5150#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
5151#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
5152#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
5153#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
5154#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
5155#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
5156#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
5157#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
5158#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
5159#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
5160#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
5161#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
5162#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
5163
5164/******************** Bit definition for RCC_APB2LPENR register *************/
5165#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
5166#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
5167#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
5168#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
5169#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
5170#define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)
5171#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
5172#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
5173#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
5174#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
5175#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
5176#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
5177#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
5178
5179/******************** Bit definition for RCC_BDCR register ******************/
5180#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
5181#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
5182#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
5183
5184#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
5185#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
5186#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
5187
5188#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
5189#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
5190
5191/******************** Bit definition for RCC_CSR register *******************/
5192#define RCC_CSR_LSION ((uint32_t)0x00000001)
5193#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
5194#define RCC_CSR_RMVF ((uint32_t)0x01000000)
5195#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
5196#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
5197#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
5198#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
5199#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
5200#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
5201#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
5202
5203/******************** Bit definition for RCC_SSCGR register *****************/
5204#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
5205#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
5206#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
5207#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
5208
5209/******************** Bit definition for RCC_PLLI2SCFGR register ************/
5210#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
5211#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
5212
5213/******************************************************************************/
5214/* */
5215/* RNG */
5216/* */
5217/******************************************************************************/
5218/******************** Bits definition for RNG_CR register *******************/
5219#define RNG_CR_RNGEN ((uint32_t)0x00000004)
5220#define RNG_CR_IE ((uint32_t)0x00000008)
5221
5222/******************** Bits definition for RNG_SR register *******************/
5223#define RNG_SR_DRDY ((uint32_t)0x00000001)
5224#define RNG_SR_CECS ((uint32_t)0x00000002)
5225#define RNG_SR_SECS ((uint32_t)0x00000004)
5226#define RNG_SR_CEIS ((uint32_t)0x00000020)
5227#define RNG_SR_SEIS ((uint32_t)0x00000040)
5228
5229/******************************************************************************/
5230/* */
5231/* Real-Time Clock (RTC) */
5232/* */
5233/******************************************************************************/
5234/******************** Bits definition for RTC_TR register *******************/
5235#define RTC_TR_PM ((uint32_t)0x00400000)
5236#define RTC_TR_HT ((uint32_t)0x00300000)
5237#define RTC_TR_HT_0 ((uint32_t)0x00100000)
5238#define RTC_TR_HT_1 ((uint32_t)0x00200000)
5239#define RTC_TR_HU ((uint32_t)0x000F0000)
5240#define RTC_TR_HU_0 ((uint32_t)0x00010000)
5241#define RTC_TR_HU_1 ((uint32_t)0x00020000)
5242#define RTC_TR_HU_2 ((uint32_t)0x00040000)
5243#define RTC_TR_HU_3 ((uint32_t)0x00080000)
5244#define RTC_TR_MNT ((uint32_t)0x00007000)
5245#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
5246#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
5247#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
5248#define RTC_TR_MNU ((uint32_t)0x00000F00)
5249#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
5250#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
5251#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
5252#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
5253#define RTC_TR_ST ((uint32_t)0x00000070)
5254#define RTC_TR_ST_0 ((uint32_t)0x00000010)
5255#define RTC_TR_ST_1 ((uint32_t)0x00000020)
5256#define RTC_TR_ST_2 ((uint32_t)0x00000040)
5257#define RTC_TR_SU ((uint32_t)0x0000000F)
5258#define RTC_TR_SU_0 ((uint32_t)0x00000001)
5259#define RTC_TR_SU_1 ((uint32_t)0x00000002)
5260#define RTC_TR_SU_2 ((uint32_t)0x00000004)
5261#define RTC_TR_SU_3 ((uint32_t)0x00000008)
5262
5263/******************** Bits definition for RTC_DR register *******************/
5264#define RTC_DR_YT ((uint32_t)0x00F00000)
5265#define RTC_DR_YT_0 ((uint32_t)0x00100000)
5266#define RTC_DR_YT_1 ((uint32_t)0x00200000)
5267#define RTC_DR_YT_2 ((uint32_t)0x00400000)
5268#define RTC_DR_YT_3 ((uint32_t)0x00800000)
5269#define RTC_DR_YU ((uint32_t)0x000F0000)
5270#define RTC_DR_YU_0 ((uint32_t)0x00010000)
5271#define RTC_DR_YU_1 ((uint32_t)0x00020000)
5272#define RTC_DR_YU_2 ((uint32_t)0x00040000)
5273#define RTC_DR_YU_3 ((uint32_t)0x00080000)
5274#define RTC_DR_WDU ((uint32_t)0x0000E000)
5275#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
5276#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
5277#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
5278#define RTC_DR_MT ((uint32_t)0x00001000)
5279#define RTC_DR_MU ((uint32_t)0x00000F00)
5280#define RTC_DR_MU_0 ((uint32_t)0x00000100)
5281#define RTC_DR_MU_1 ((uint32_t)0x00000200)
5282#define RTC_DR_MU_2 ((uint32_t)0x00000400)
5283#define RTC_DR_MU_3 ((uint32_t)0x00000800)
5284#define RTC_DR_DT ((uint32_t)0x00000030)
5285#define RTC_DR_DT_0 ((uint32_t)0x00000010)
5286#define RTC_DR_DT_1 ((uint32_t)0x00000020)
5287#define RTC_DR_DU ((uint32_t)0x0000000F)
5288#define RTC_DR_DU_0 ((uint32_t)0x00000001)
5289#define RTC_DR_DU_1 ((uint32_t)0x00000002)
5290#define RTC_DR_DU_2 ((uint32_t)0x00000004)
5291#define RTC_DR_DU_3 ((uint32_t)0x00000008)
5292
5293/******************** Bits definition for RTC_CR register *******************/
5294#define RTC_CR_COE ((uint32_t)0x00800000)
5295#define RTC_CR_OSEL ((uint32_t)0x00600000)
5296#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
5297#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
5298#define RTC_CR_POL ((uint32_t)0x00100000)
5299#define RTC_CR_BCK ((uint32_t)0x00040000)
5300#define RTC_CR_SUB1H ((uint32_t)0x00020000)
5301#define RTC_CR_ADD1H ((uint32_t)0x00010000)
5302#define RTC_CR_TSIE ((uint32_t)0x00008000)
5303#define RTC_CR_WUTIE ((uint32_t)0x00004000)
5304#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
5305#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
5306#define RTC_CR_TSE ((uint32_t)0x00000800)
5307#define RTC_CR_WUTE ((uint32_t)0x00000400)
5308#define RTC_CR_ALRBE ((uint32_t)0x00000200)
5309#define RTC_CR_ALRAE ((uint32_t)0x00000100)
5310#define RTC_CR_DCE ((uint32_t)0x00000080)
5311#define RTC_CR_FMT ((uint32_t)0x00000040)
5312#define RTC_CR_REFCKON ((uint32_t)0x00000010)
5313#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
5314#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
5315#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
5316#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
5317#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
5318
5319/******************** Bits definition for RTC_ISR register ******************/
5320#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
5321#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
5322#define RTC_ISR_TSF ((uint32_t)0x00000800)
5323#define RTC_ISR_WUTF ((uint32_t)0x00000400)
5324#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
5325#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
5326#define RTC_ISR_INIT ((uint32_t)0x00000080)
5327#define RTC_ISR_INITF ((uint32_t)0x00000040)
5328#define RTC_ISR_RSF ((uint32_t)0x00000020)
5329#define RTC_ISR_INITS ((uint32_t)0x00000010)
5330#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
5331#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
5332#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
5333
5334/******************** Bits definition for RTC_PRER register *****************/
5335#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
5336#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
5337
5338/******************** Bits definition for RTC_WUTR register *****************/
5339#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
5340
5341/******************** Bits definition for RTC_CALIBR register ***************/
5342#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
5343#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
5344
5345/******************** Bits definition for RTC_ALRMAR register ***************/
5346#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
5347#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
5348#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
5349#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
5350#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
5351#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
5352#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
5353#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
5354#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
5355#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
5356#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
5357#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
5358#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
5359#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
5360#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
5361#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
5362#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
5363#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
5364#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
5365#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
5366#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
5367#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
5368#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
5369#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
5370#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
5371#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
5372#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
5373#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
5374#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
5375#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
5376#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
5377#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
5378#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
5379#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
5380#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
5381#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
5382#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
5383#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
5384#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
5385#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
5386
5387/******************** Bits definition for RTC_ALRMBR register ***************/
5388#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
5389#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
5390#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
5391#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
5392#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
5393#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
5394#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
5395#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
5396#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
5397#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
5398#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
5399#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
5400#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
5401#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
5402#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
5403#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
5404#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
5405#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
5406#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
5407#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
5408#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
5409#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
5410#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
5411#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
5412#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
5413#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
5414#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
5415#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
5416#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
5417#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
5418#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
5419#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
5420#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
5421#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
5422#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
5423#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
5424#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
5425#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
5426#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
5427#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
5428
5429/******************** Bits definition for RTC_WPR register ******************/
5430#define RTC_WPR_KEY ((uint32_t)0x000000FF)
5431
5432/******************** Bits definition for RTC_TSTR register *****************/
5433#define RTC_TSTR_PM ((uint32_t)0x00400000)
5434#define RTC_TSTR_HT ((uint32_t)0x00300000)
5435#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
5436#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
5437#define RTC_TSTR_HU ((uint32_t)0x000F0000)
5438#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
5439#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
5440#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
5441#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
5442#define RTC_TSTR_MNT ((uint32_t)0x00007000)
5443#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
5444#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
5445#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
5446#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
5447#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
5448#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
5449#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
5450#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
5451#define RTC_TSTR_ST ((uint32_t)0x00000070)
5452#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
5453#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
5454#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
5455#define RTC_TSTR_SU ((uint32_t)0x0000000F)
5456#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
5457#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
5458#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
5459#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
5460
5461/******************** Bits definition for RTC_TSDR register *****************/
5462#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
5463#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
5464#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
5465#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
5466#define RTC_TSDR_MT ((uint32_t)0x00001000)
5467#define RTC_TSDR_MU ((uint32_t)0x00000F00)
5468#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
5469#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
5470#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
5471#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
5472#define RTC_TSDR_DT ((uint32_t)0x00000030)
5473#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
5474#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
5475#define RTC_TSDR_DU ((uint32_t)0x0000000F)
5476#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
5477#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
5478#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
5479#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
5480
5481/******************** Bits definition for RTC_TAFCR register ****************/
5482#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
5483#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
5484#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
5485#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
5486#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
5487#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
5488
5489/******************** Bits definition for RTC_BKP0R register ****************/
5490#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
5491
5492/******************** Bits definition for RTC_BKP1R register ****************/
5493#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
5494
5495/******************** Bits definition for RTC_BKP2R register ****************/
5496#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
5497
5498/******************** Bits definition for RTC_BKP3R register ****************/
5499#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
5500
5501/******************** Bits definition for RTC_BKP4R register ****************/
5502#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
5503
5504/******************** Bits definition for RTC_BKP5R register ****************/
5505#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
5506
5507/******************** Bits definition for RTC_BKP6R register ****************/
5508#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
5509
5510/******************** Bits definition for RTC_BKP7R register ****************/
5511#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
5512
5513/******************** Bits definition for RTC_BKP8R register ****************/
5514#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
5515
5516/******************** Bits definition for RTC_BKP9R register ****************/
5517#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
5518
5519/******************** Bits definition for RTC_BKP10R register ***************/
5520#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
5521
5522/******************** Bits definition for RTC_BKP11R register ***************/
5523#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
5524
5525/******************** Bits definition for RTC_BKP12R register ***************/
5526#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
5527
5528/******************** Bits definition for RTC_BKP13R register ***************/
5529#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
5530
5531/******************** Bits definition for RTC_BKP14R register ***************/
5532#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
5533
5534/******************** Bits definition for RTC_BKP15R register ***************/
5535#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
5536
5537/******************** Bits definition for RTC_BKP16R register ***************/
5538#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
5539
5540/******************** Bits definition for RTC_BKP17R register ***************/
5541#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
5542
5543/******************** Bits definition for RTC_BKP18R register ***************/
5544#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
5545
5546/******************** Bits definition for RTC_BKP19R register ***************/
5547#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
5548
5549/******************************************************************************/
5550/* */
5551/* SD host Interface */
5552/* */
5553/******************************************************************************/
5554/****************** Bit definition for SDIO_POWER register ******************/
5555#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
5556#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!<Bit 0 */
5557#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!<Bit 1 */
5558
5559/****************** Bit definition for SDIO_CLKCR register ******************/
5560#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!<Clock divide factor */
5561#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!<Clock enable bit */
5562#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!<Power saving configuration bit */
5563#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!<Clock divider bypass enable bit */
5564
5565#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
5566#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!<Bit 0 */
5567#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!<Bit 1 */
5568
5569#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!<SDIO_CK dephasing selection bit */
5570#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!<HW Flow Control enable */
5571
5572/******************* Bit definition for SDIO_ARG register *******************/
5573#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
5574
5575/******************* Bit definition for SDIO_CMD register *******************/
5576#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!<Command Index */
5577
5578#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
5579#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */
5580#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */
5581
5582#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!<CPSM Waits for Interrupt Request */
5583#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
5584#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
5585#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!<SD I/O suspend command */
5586#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!<Enable CMD completion */
5587#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!<Not Interrupt Enable */
5588#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!<CE-ATA command */
5589
5590/***************** Bit definition for SDIO_RESPCMD register *****************/
5591#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!<Response command index */
5592
5593/****************** Bit definition for SDIO_RESP0 register ******************/
5594#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5595
5596/****************** Bit definition for SDIO_RESP1 register ******************/
5597#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5598
5599/****************** Bit definition for SDIO_RESP2 register ******************/
5600#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5601
5602/****************** Bit definition for SDIO_RESP3 register ******************/
5603#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5604
5605/****************** Bit definition for SDIO_RESP4 register ******************/
5606#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5607
5608/****************** Bit definition for SDIO_DTIMER register *****************/
5609#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
5610
5611/****************** Bit definition for SDIO_DLEN register *******************/
5612#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
5613
5614/****************** Bit definition for SDIO_DCTRL register ******************/
5615#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!<Data transfer enabled bit */
5616#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!<Data transfer direction selection */
5617#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!<Data transfer mode selection */
5618#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!<DMA enabled bit */
5619
5620#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
5621#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!<Bit 0 */
5622#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!<Bit 1 */
5623#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!<Bit 2 */
5624#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!<Bit 3 */
5625
5626#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!<Read wait start */
5627#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!<Read wait stop */
5628#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!<Read wait mode */
5629#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!<SD I/O enable functions */
5630
5631/****************** Bit definition for SDIO_DCOUNT register *****************/
5632#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
5633
5634/****************** Bit definition for SDIO_STA register ********************/
5635#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
5636#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
5637#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
5638#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
5639#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
5640#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
5641#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
5642#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
5643#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
5644#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
5645#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
5646#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
5647#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
5648#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
5649#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
5650#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
5651#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
5652#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
5653#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
5654#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
5655#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
5656#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
5657#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
5658#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
5659
5660/******************* Bit definition for SDIO_ICR register *******************/
5661#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
5662#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
5663#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
5664#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
5665#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
5666#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
5667#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
5668#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
5669#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
5670#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
5671#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
5672#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
5673#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
5674
5675/****************** Bit definition for SDIO_MASK register *******************/
5676#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
5677#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
5678#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
5679#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
5680#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
5681#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
5682#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
5683#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
5684#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
5685#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
5686#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
5687#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
5688#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
5689#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
5690#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
5691#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
5692#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
5693#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
5694#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
5695#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
5696#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
5697#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
5698#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
5699#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
5700
5701/***************** Bit definition for SDIO_FIFOCNT register *****************/
5702#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
5703
5704/****************** Bit definition for SDIO_FIFO register *******************/
5705#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
5706
5707/******************************************************************************/
5708/* */
5709/* Serial Peripheral Interface */
5710/* */
5711/******************************************************************************/
5712/******************* Bit definition for SPI_CR1 register ********************/
5713#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!<Clock Phase */
5714#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!<Clock Polarity */
5715#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!<Master Selection */
5716
5717#define SPI_CR1_BR ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */
5718#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!<Bit 0 */
5719#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!<Bit 1 */
5720#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!<Bit 2 */
5721
5722#define SPI_CR1_SPE ((uint16_t)0x0040) /*!<SPI Enable */
5723#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!<Frame Format */
5724#define SPI_CR1_SSI ((uint16_t)0x0100) /*!<Internal slave select */
5725#define SPI_CR1_SSM ((uint16_t)0x0200) /*!<Software slave management */
5726#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!<Receive only */
5727#define SPI_CR1_DFF ((uint16_t)0x0800) /*!<Data Frame Format */
5728#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!<Transmit CRC next */
5729#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!<Hardware CRC calculation enable */
5730#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */
5731#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!<Bidirectional data mode enable */
5732
5733/******************* Bit definition for SPI_CR2 register ********************/
5734#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */
5735#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */
5736#define SPI_CR2_SSOE ((uint8_t)0x04) /*!<SS Output Enable */
5737#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!<Error Interrupt Enable */
5738#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */
5739#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */
5740
5741/******************** Bit definition for SPI_SR register ********************/
5742#define SPI_SR_RXNE ((uint8_t)0x01) /*!<Receive buffer Not Empty */
5743#define SPI_SR_TXE ((uint8_t)0x02) /*!<Transmit buffer Empty */
5744#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!<Channel side */
5745#define SPI_SR_UDR ((uint8_t)0x08) /*!<Underrun flag */
5746#define SPI_SR_CRCERR ((uint8_t)0x10) /*!<CRC Error flag */
5747#define SPI_SR_MODF ((uint8_t)0x20) /*!<Mode fault */
5748#define SPI_SR_OVR ((uint8_t)0x40) /*!<Overrun flag */
5749#define SPI_SR_BSY ((uint8_t)0x80) /*!<Busy flag */
5750
5751/******************** Bit definition for SPI_DR register ********************/
5752#define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */
5753
5754/******************* Bit definition for SPI_CRCPR register ******************/
5755#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!<CRC polynomial register */
5756
5757/****************** Bit definition for SPI_RXCRCR register ******************/
5758#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!<Rx CRC Register */
5759
5760/****************** Bit definition for SPI_TXCRCR register ******************/
5761#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!<Tx CRC Register */
5762
5763/****************** Bit definition for SPI_I2SCFGR register *****************/
5764#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
5765
5766#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
5767#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
5768#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
5769
5770#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
5771
5772#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
5773#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
5774#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
5775
5776#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
5777
5778#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
5779#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
5780#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
5781
5782#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
5783#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
5784
5785/****************** Bit definition for SPI_I2SPR register *******************/
5786#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
5787#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
5788#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
5789
5790/******************************************************************************/
5791/* */
5792/* SYSCFG */
5793/* */
5794/******************************************************************************/
5795/****************** Bit definition for SYSCFG_MEMRMP register ***************/
5796#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) /*!<SYSCFG_Memory Remap Config */
5797#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
5798#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
5799
5800/****************** Bit definition for SYSCFG_PMC register ******************/
5801#define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
5802/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
5803#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
5804
5805/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
5806#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!<EXTI 0 configuration */
5807#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!<EXTI 1 configuration */
5808#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!<EXTI 2 configuration */
5809#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!<EXTI 3 configuration */
5810/**
5811 * @brief EXTI0 configuration
5812 */
5813#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!<PA[0] pin */
5814#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!<PB[0] pin */
5815#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!<PC[0] pin */
5816#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!<PD[0] pin */
5817#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!<PE[0] pin */
5818#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!<PF[0] pin */
5819#define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!<PG[0] pin */
5820#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) /*!<PH[0] pin */
5821#define SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) /*!<PI[0] pin */
5822/**
5823 * @brief EXTI1 configuration
5824 */
5825#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!<PA[1] pin */
5826#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!<PB[1] pin */
5827#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!<PC[1] pin */
5828#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!<PD[1] pin */
5829#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!<PE[1] pin */
5830#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!<PF[1] pin */
5831#define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!<PG[1] pin */
5832#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) /*!<PH[1] pin */
5833#define SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) /*!<PI[1] pin */
5834/**
5835 * @brief EXTI2 configuration
5836 */
5837#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!<PA[2] pin */
5838#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!<PB[2] pin */
5839#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!<PC[2] pin */
5840#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!<PD[2] pin */
5841#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!<PE[2] pin */
5842#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!<PF[2] pin */
5843#define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!<PG[2] pin */
5844#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) /*!<PH[2] pin */
5845#define SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) /*!<PI[2] pin */
5846/**
5847 * @brief EXTI3 configuration
5848 */
5849#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!<PA[3] pin */
5850#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!<PB[3] pin */
5851#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!<PC[3] pin */
5852#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!<PD[3] pin */
5853#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!<PE[3] pin */
5854#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!<PF[3] pin */
5855#define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!<PG[3] pin */
5856#define SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) /*!<PH[3] pin */
5857#define SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) /*!<PI[3] pin */
5858
5859/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
5860#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!<EXTI 4 configuration */
5861#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!<EXTI 5 configuration */
5862#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!<EXTI 6 configuration */
5863#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!<EXTI 7 configuration */
5864/**
5865 * @brief EXTI4 configuration
5866 */
5867#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!<PA[4] pin */
5868#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!<PB[4] pin */
5869#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!<PC[4] pin */
5870#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!<PD[4] pin */
5871#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!<PE[4] pin */
5872#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!<PF[4] pin */
5873#define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!<PG[4] pin */
5874#define SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) /*!<PH[4] pin */
5875#define SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) /*!<PI[4] pin */
5876/**
5877 * @brief EXTI5 configuration
5878 */
5879#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!<PA[5] pin */
5880#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!<PB[5] pin */
5881#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!<PC[5] pin */
5882#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!<PD[5] pin */
5883#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!<PE[5] pin */
5884#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!<PF[5] pin */
5885#define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!<PG[5] pin */
5886#define SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) /*!<PH[5] pin */
5887#define SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) /*!<PI[5] pin */
5888/**
5889 * @brief EXTI6 configuration
5890 */
5891#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!<PA[6] pin */
5892#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!<PB[6] pin */
5893#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!<PC[6] pin */
5894#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!<PD[6] pin */
5895#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!<PE[6] pin */
5896#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!<PF[6] pin */
5897#define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!<PG[6] pin */
5898#define SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) /*!<PH[6] pin */
5899#define SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) /*!<PI[6] pin */
5900/**
5901 * @brief EXTI7 configuration
5902 */
5903#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!<PA[7] pin */
5904#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!<PB[7] pin */
5905#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!<PC[7] pin */
5906#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!<PD[7] pin */
5907#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!<PE[7] pin */
5908#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!<PF[7] pin */
5909#define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!<PG[7] pin */
5910#define SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) /*!<PH[7] pin */
5911#define SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) /*!<PI[7] pin */
5912
5913/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
5914#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!<EXTI 8 configuration */
5915#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!<EXTI 9 configuration */
5916#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!<EXTI 10 configuration */
5917#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!<EXTI 11 configuration */
5918
5919/**
5920 * @brief EXTI8 configuration
5921 */
5922#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!<PA[8] pin */
5923#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!<PB[8] pin */
5924#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!<PC[8] pin */
5925#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!<PD[8] pin */
5926#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!<PE[8] pin */
5927#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!<PF[8] pin */
5928#define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!<PG[8] pin */
5929#define SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) /*!<PH[8] pin */
5930#define SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) /*!<PI[8] pin */
5931/**
5932 * @brief EXTI9 configuration
5933 */
5934#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!<PA[9] pin */
5935#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!<PB[9] pin */
5936#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!<PC[9] pin */
5937#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!<PD[9] pin */
5938#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!<PE[9] pin */
5939#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!<PF[9] pin */
5940#define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!<PG[9] pin */
5941#define SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) /*!<PH[9] pin */
5942#define SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) /*!<PI[9] pin */
5943/**
5944 * @brief EXTI10 configuration
5945 */
5946#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!<PA[10] pin */
5947#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!<PB[10] pin */
5948#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!<PC[10] pin */
5949#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!<PD[10] pin */
5950#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!<PE[10] pin */
5951#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!<PF[10] pin */
5952#define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!<PG[10] pin */
5953#define SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) /*!<PH[10] pin */
5954#define SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) /*!<PI[10] pin */
5955/**
5956 * @brief EXTI11 configuration
5957 */
5958#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!<PA[11] pin */
5959#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!<PB[11] pin */
5960#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!<PC[11] pin */
5961#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!<PD[11] pin */
5962#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!<PE[11] pin */
5963#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!<PF[11] pin */
5964#define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!<PG[11] pin */
5965#define SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) /*!<PH[11] pin */
5966#define SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) /*!<PI[11] pin */
5967
5968/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
5969#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!<EXTI 12 configuration */
5970#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!<EXTI 13 configuration */
5971#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!<EXTI 14 configuration */
5972#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!<EXTI 15 configuration */
5973/**
5974 * @brief EXTI12 configuration
5975 */
5976#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!<PA[12] pin */
5977#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!<PB[12] pin */
5978#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!<PC[12] pin */
5979#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!<PD[12] pin */
5980#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!<PE[12] pin */
5981#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!<PF[12] pin */
5982#define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!<PG[12] pin */
5983#define SYSCFG_EXTICR3_EXTI12_PH ((uint16_t)0x0007) /*!<PH[12] pin */
5984/**
5985 * @brief EXTI13 configuration
5986 */
5987#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!<PA[13] pin */
5988#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!<PB[13] pin */
5989#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!<PC[13] pin */
5990#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!<PD[13] pin */
5991#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!<PE[13] pin */
5992#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!<PF[13] pin */
5993#define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!<PG[13] pin */
5994#define SYSCFG_EXTICR3_EXTI13_PH ((uint16_t)0x0070) /*!<PH[13] pin */
5995/**
5996 * @brief EXTI14 configuration
5997 */
5998#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!<PA[14] pin */
5999#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!<PB[14] pin */
6000#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!<PC[14] pin */
6001#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!<PD[14] pin */
6002#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!<PE[14] pin */
6003#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!<PF[14] pin */
6004#define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!<PG[14] pin */
6005#define SYSCFG_EXTICR3_EXTI14_PH ((uint16_t)0x0700) /*!<PH[14] pin */
6006/**
6007 * @brief EXTI15 configuration
6008 */
6009#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!<PA[15] pin */
6010#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!<PB[15] pin */
6011#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!<PC[15] pin */
6012#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!<PD[15] pin */
6013#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!<PE[15] pin */
6014#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!<PF[15] pin */
6015#define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!<PG[15] pin */
6016#define SYSCFG_EXTICR3_EXTI15_PH ((uint16_t)0x7000) /*!<PH[15] pin */
6017
6018/****************** Bit definition for SYSCFG_CMPCR register ****************/
6019#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
6020#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
6021
6022/******************************************************************************/
6023/* */
6024/* TIM */
6025/* */
6026/******************************************************************************/
6027/******************* Bit definition for TIM_CR1 register ********************/
6028#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
6029#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
6030#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
6031#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
6032#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
6033
6034#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
6035#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
6036#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
6037
6038#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
6039
6040#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
6041#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
6042#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
6043
6044/******************* Bit definition for TIM_CR2 register ********************/
6045#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */
6046#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */
6047#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
6048
6049#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
6050#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
6051#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
6052#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
6053
6054#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
6055#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
6056#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
6057#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
6058#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
6059#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
6060#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
6061#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
6062
6063/******************* Bit definition for TIM_SMCR register *******************/
6064#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
6065#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
6066#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
6067#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
6068
6069#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
6070#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
6071#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
6072#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
6073
6074#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
6075
6076#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
6077#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
6078#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
6079#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
6080#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
6081
6082#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
6083#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
6084#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
6085
6086#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
6087#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
6088
6089/******************* Bit definition for TIM_DIER register *******************/
6090#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
6091#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
6092#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
6093#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
6094#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
6095#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
6096#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
6097#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
6098#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
6099#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
6100#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
6101#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
6102#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
6103#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
6104#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
6105
6106/******************** Bit definition for TIM_SR register ********************/
6107#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
6108#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
6109#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
6110#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
6111#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
6112#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */
6113#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
6114#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */
6115#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
6116#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
6117#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
6118#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
6119
6120/******************* Bit definition for TIM_EGR register ********************/
6121#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
6122#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
6123#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
6124#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
6125#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
6126#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */
6127#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
6128#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */
6129
6130/****************** Bit definition for TIM_CCMR1 register *******************/
6131#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
6132#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
6133#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
6134
6135#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
6136#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
6137
6138#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
6139#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
6140#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
6141#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
6142
6143#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
6144
6145#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
6146#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
6147#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
6148
6149#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
6150#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
6151
6152#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
6153#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
6154#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
6155#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
6156
6157#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
6158
6159/*----------------------------------------------------------------------------*/
6160
6161#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
6162#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
6163#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
6164
6165#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
6166#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
6167#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
6168#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
6169#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
6170
6171#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
6172#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
6173#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
6174
6175#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
6176#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
6177#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
6178#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
6179#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
6180
6181/****************** Bit definition for TIM_CCMR2 register *******************/
6182#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
6183#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
6184#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
6185
6186#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
6187#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
6188
6189#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
6190#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
6191#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
6192#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
6193
6194#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
6195
6196#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
6197#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
6198#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
6199
6200#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
6201#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
6202
6203#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
6204#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
6205#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
6206#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
6207
6208#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
6209
6210/*----------------------------------------------------------------------------*/
6211
6212#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
6213#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
6214#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
6215
6216#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
6217#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
6218#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
6219#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
6220#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
6221
6222#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
6223#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
6224#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
6225
6226#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
6227#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
6228#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
6229#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
6230#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
6231
6232/******************* Bit definition for TIM_CCER register *******************/
6233#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
6234#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
6235#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
6236#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
6237#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
6238#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
6239#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
6240#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
6241#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
6242#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
6243#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
6244#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
6245#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
6246#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
6247#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
6248
6249/******************* Bit definition for TIM_CNT register ********************/
6250#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
6251
6252/******************* Bit definition for TIM_PSC register ********************/
6253#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
6254
6255/******************* Bit definition for TIM_ARR register ********************/
6256#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
6257
6258/******************* Bit definition for TIM_RCR register ********************/
6259#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
6260
6261/******************* Bit definition for TIM_CCR1 register *******************/
6262#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
6263
6264/******************* Bit definition for TIM_CCR2 register *******************/
6265#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
6266
6267/******************* Bit definition for TIM_CCR3 register *******************/
6268#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
6269
6270/******************* Bit definition for TIM_CCR4 register *******************/
6271#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
6272
6273/******************* Bit definition for TIM_BDTR register *******************/
6274#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
6275#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */
6276#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */
6277#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */
6278#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */
6279#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */
6280#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */
6281#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */
6282#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */
6283
6284#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
6285#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */
6286#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */
6287
6288#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */
6289#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */
6290#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */
6291#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */
6292#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */
6293#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */
6294
6295/******************* Bit definition for TIM_DCR register ********************/
6296#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
6297#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
6298#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
6299#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
6300#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
6301#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
6302
6303#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
6304#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
6305#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
6306#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
6307#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
6308#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
6309
6310/******************* Bit definition for TIM_DMAR register *******************/
6311#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
6312
6313/******************* Bit definition for TIM_OR register *********************/
6314#define TIM_OR_TI4_RMP ((uint16_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
6315#define TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) /*!<Bit 0 */
6316#define TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) /*!<Bit 1 */
6317#define TIM_OR_ITR1_RMP ((uint16_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
6318#define TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) /*!<Bit 0 */
6319#define TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) /*!<Bit 1 */
6320
6321
6322/******************************************************************************/
6323/* */
6324/* Universal Synchronous Asynchronous Receiver Transmitter */
6325/* */
6326/******************************************************************************/
6327/******************* Bit definition for USART_SR register *******************/
6328#define USART_SR_PE ((uint16_t)0x0001) /*!<Parity Error */
6329#define USART_SR_FE ((uint16_t)0x0002) /*!<Framing Error */
6330#define USART_SR_NE ((uint16_t)0x0004) /*!<Noise Error Flag */
6331#define USART_SR_ORE ((uint16_t)0x0008) /*!<OverRun Error */
6332#define USART_SR_IDLE ((uint16_t)0x0010) /*!<IDLE line detected */
6333#define USART_SR_RXNE ((uint16_t)0x0020) /*!<Read Data Register Not Empty */
6334#define USART_SR_TC ((uint16_t)0x0040) /*!<Transmission Complete */
6335#define USART_SR_TXE ((uint16_t)0x0080) /*!<Transmit Data Register Empty */
6336#define USART_SR_LBD ((uint16_t)0x0100) /*!<LIN Break Detection Flag */
6337#define USART_SR_CTS ((uint16_t)0x0200) /*!<CTS Flag */
6338
6339/******************* Bit definition for USART_DR register *******************/
6340#define USART_DR_DR ((uint16_t)0x01FF) /*!<Data value */
6341
6342/****************** Bit definition for USART_BRR register *******************/
6343#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!<Fraction of USARTDIV */
6344#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!<Mantissa of USARTDIV */
6345
6346/****************** Bit definition for USART_CR1 register *******************/
6347#define USART_CR1_SBK ((uint16_t)0x0001) /*!<Send Break */
6348#define USART_CR1_RWU ((uint16_t)0x0002) /*!<Receiver wakeup */
6349#define USART_CR1_RE ((uint16_t)0x0004) /*!<Receiver Enable */
6350#define USART_CR1_TE ((uint16_t)0x0008) /*!<Transmitter Enable */
6351#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!<IDLE Interrupt Enable */
6352#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!<RXNE Interrupt Enable */
6353#define USART_CR1_TCIE ((uint16_t)0x0040) /*!<Transmission Complete Interrupt Enable */
6354#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!<PE Interrupt Enable */
6355#define USART_CR1_PEIE ((uint16_t)0x0100) /*!<PE Interrupt Enable */
6356#define USART_CR1_PS ((uint16_t)0x0200) /*!<Parity Selection */
6357#define USART_CR1_PCE ((uint16_t)0x0400) /*!<Parity Control Enable */
6358#define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */
6359#define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */
6360#define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */
6361#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!<USART Oversampling by 8 enable */
6362
6363/****************** Bit definition for USART_CR2 register *******************/
6364#define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */
6365#define USART_CR2_LBDL ((uint16_t)0x0020) /*!<LIN Break Detection Length */
6366#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
6367#define USART_CR2_LBCL ((uint16_t)0x0100) /*!<Last Bit Clock pulse */
6368#define USART_CR2_CPHA ((uint16_t)0x0200) /*!<Clock Phase */
6369#define USART_CR2_CPOL ((uint16_t)0x0400) /*!<Clock Polarity */
6370#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!<Clock Enable */
6371
6372#define USART_CR2_STOP ((uint16_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
6373#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!<Bit 0 */
6374#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!<Bit 1 */
6375
6376#define USART_CR2_LINEN ((uint16_t)0x4000) /*!<LIN mode enable */
6377
6378/****************** Bit definition for USART_CR3 register *******************/
6379#define USART_CR3_EIE ((uint16_t)0x0001) /*!<Error Interrupt Enable */
6380#define USART_CR3_IREN ((uint16_t)0x0002) /*!<IrDA mode Enable */
6381#define USART_CR3_IRLP ((uint16_t)0x0004) /*!<IrDA Low-Power */
6382#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!<Half-Duplex Selection */
6383#define USART_CR3_NACK ((uint16_t)0x0010) /*!<Smartcard NACK enable */
6384#define USART_CR3_SCEN ((uint16_t)0x0020) /*!<Smartcard mode enable */
6385#define USART_CR3_DMAR ((uint16_t)0x0040) /*!<DMA Enable Receiver */
6386#define USART_CR3_DMAT ((uint16_t)0x0080) /*!<DMA Enable Transmitter */
6387#define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */
6388#define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */
6389#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */
6390#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!<USART One bit method enable */
6391
6392/****************** Bit definition for USART_GTPR register ******************/
6393#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
6394#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!<Bit 0 */
6395#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!<Bit 1 */
6396#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!<Bit 2 */
6397#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!<Bit 3 */
6398#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!<Bit 4 */
6399#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!<Bit 5 */
6400#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!<Bit 6 */
6401#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!<Bit 7 */
6402
6403#define USART_GTPR_GT ((uint16_t)0xFF00) /*!<Guard time value */
6404
6405/******************************************************************************/
6406/* */
6407/* Window WATCHDOG */
6408/* */
6409/******************************************************************************/
6410/******************* Bit definition for WWDG_CR register ********************/
6411#define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
6412#define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */
6413#define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */
6414#define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */
6415#define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */
6416#define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */
6417#define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */
6418#define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */
6419
6420#define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */
6421
6422/******************* Bit definition for WWDG_CFR register *******************/
6423#define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
6424#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */
6425#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */
6426#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */
6427#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */
6428#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */
6429#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */
6430#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */
6431
6432#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
6433#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */
6434#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */
6435
6436#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */
6437
6438/******************* Bit definition for WWDG_SR register ********************/
6439#define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */
6440
6441
6442/******************************************************************************/
6443/* */
6444/* DBG */
6445/* */
6446/******************************************************************************/
6447/******************** Bit definition for DBGMCU_IDCODE register *************/
6448#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
6449#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
6450
6451/******************** Bit definition for DBGMCU_CR register *****************/
6452#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
6453#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
6454#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
6455#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
6456
6457#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
6458#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
6459#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
6460
6461/******************** Bit definition for DBGMCU_APB1_FZ register ************/
6462#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
6463#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
6464#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
6465#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
6466#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
6467#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
6468#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
6469#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
6470#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
6471#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
6472#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
6473#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
6474#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
6475#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
6476#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
6477#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
6478#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
6479/* Old IWDGSTOP bit definition, maintained for legacy purpose */
6480#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
6481
6482/******************** Bit definition for DBGMCU_APB2_FZ register ************/
6483#define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
6484#define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
6485#define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
6486#define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
6487#define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
6488
6489/******************************************************************************/
6490/* */
6491/* Ethernet MAC Registers bits definitions */
6492/* */
6493/******************************************************************************/
6494/* Bit definition for Ethernet MAC Control Register register */
6495#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
6496#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
6497#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
6498#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
6499 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
6500 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
6501 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
6502 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
6503 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
6504 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
6505 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
6506#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
6507#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
6508#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
6509#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
6510#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
6511#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
6512#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
6513#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
6514#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
6515 a transmission attempt during retries after a collision: 0 =< r <2^k */
6516 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
6517 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
6518 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
6519 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
6520#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
6521#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
6522#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
6523
6524/* Bit definition for Ethernet MAC Frame Filter Register */
6525#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
6526#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
6527#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
6528#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
6529#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
6530 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
6531 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
6532 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
6533#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
6534#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
6535#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
6536#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
6537#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
6538#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
6539
6540/* Bit definition for Ethernet MAC Hash Table High Register */
6541#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
6542
6543/* Bit definition for Ethernet MAC Hash Table Low Register */
6544#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
6545
6546/* Bit definition for Ethernet MAC MII Address Register */
6547#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
6548#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
6549#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
6550 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
6551 #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-120 MHz; MDC clock= HCLK/62 */
6552 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
6553 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/42 */
6554#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
6555#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
6556
6557/* Bit definition for Ethernet MAC MII Data Register */
6558#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
6559
6560/* Bit definition for Ethernet MAC Flow Control Register */
6561#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
6562#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
6563#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
6564 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
6565 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
6566 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
6567 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
6568#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
6569#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
6570#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
6571#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
6572
6573/* Bit definition for Ethernet MAC VLAN Tag Register */
6574#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
6575#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
6576
6577/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
6578#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
6579/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
6580 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
6581/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
6582 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
6583 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
6584 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
6585 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
6586 RSVD - Filter1 Command - RSVD - Filter0 Command
6587 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
6588 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
6589 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
6590
6591/* Bit definition for Ethernet MAC PMT Control and Status Register */
6592#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
6593#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
6594#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
6595#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
6596#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
6597#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
6598#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
6599
6600/* Bit definition for Ethernet MAC Status Register */
6601#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
6602#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
6603#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
6604#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
6605#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
6606
6607/* Bit definition for Ethernet MAC Interrupt Mask Register */
6608#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
6609#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
6610
6611/* Bit definition for Ethernet MAC Address0 High Register */
6612#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
6613
6614/* Bit definition for Ethernet MAC Address0 Low Register */
6615#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
6616
6617/* Bit definition for Ethernet MAC Address1 High Register */
6618#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
6619#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
6620#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
6621 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
6622 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
6623 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
6624 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
6625 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
6626 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
6627#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
6628
6629/* Bit definition for Ethernet MAC Address1 Low Register */
6630#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
6631
6632/* Bit definition for Ethernet MAC Address2 High Register */
6633#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
6634#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
6635#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
6636 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
6637 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
6638 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
6639 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
6640 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
6641 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
6642#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
6643
6644/* Bit definition for Ethernet MAC Address2 Low Register */
6645#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
6646
6647/* Bit definition for Ethernet MAC Address3 High Register */
6648#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
6649#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
6650#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
6651 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
6652 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
6653 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
6654 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
6655 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
6656 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
6657#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
6658
6659/* Bit definition for Ethernet MAC Address3 Low Register */
6660#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
6661
6662/******************************************************************************/
6663/* Ethernet MMC Registers bits definition */
6664/******************************************************************************/
6665
6666/* Bit definition for Ethernet MMC Contol Register */
6667#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset (Only in STM32F2xx) */
6668#define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset (Only in STM32F2xx) */
6669#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
6670#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
6671#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
6672#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
6673
6674/* Bit definition for Ethernet MMC Receive Interrupt Register */
6675#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
6676#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
6677#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
6678
6679/* Bit definition for Ethernet MMC Transmit Interrupt Register */
6680#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
6681#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
6682#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
6683
6684/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
6685#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
6686#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
6687#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
6688
6689/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
6690#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
6691#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
6692#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
6693
6694/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
6695#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
6696
6697/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
6698#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
6699
6700/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
6701#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
6702
6703/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
6704#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
6705
6706/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
6707#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
6708
6709/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
6710#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
6711
6712/******************************************************************************/
6713/* Ethernet PTP Registers bits definition */
6714/******************************************************************************/
6715
6716/* Bit definition for Ethernet PTP Time Stamp Contol Register */
6717#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
6718#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
6719#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
6720#define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
6721#define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
6722#define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
6723#define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
6724#define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
6725#define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
6726
6727#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
6728#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
6729#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
6730#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
6731#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
6732#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
6733
6734/* Bit definition for Ethernet PTP Sub-Second Increment Register */
6735#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
6736
6737/* Bit definition for Ethernet PTP Time Stamp High Register */
6738#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
6739
6740/* Bit definition for Ethernet PTP Time Stamp Low Register */
6741#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
6742#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
6743
6744/* Bit definition for Ethernet PTP Time Stamp High Update Register */
6745#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
6746
6747/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
6748#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
6749#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
6750
6751/* Bit definition for Ethernet PTP Time Stamp Addend Register */
6752#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
6753
6754/* Bit definition for Ethernet PTP Target Time High Register */
6755#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
6756
6757/* Bit definition for Ethernet PTP Target Time Low Register */
6758#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
6759
6760/* Bit definition for Ethernet PTP Time Stamp Status Register */
6761#define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
6762#define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
6763
6764/******************************************************************************/
6765/* Ethernet DMA Registers bits definition */
6766/******************************************************************************/
6767
6768/* Bit definition for Ethernet DMA Bus Mode Register */
6769#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
6770#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
6771#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
6772#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
6773 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
6774 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
6775 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
6776 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
6777 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
6778 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
6779 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
6780 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
6781 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
6782 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
6783 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
6784 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
6785#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
6786#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
6787 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
6788 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
6789 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
6790 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
6791#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
6792 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
6793 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
6794 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
6795 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
6796 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
6797 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
6798 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
6799 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
6800 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
6801 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
6802 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
6803 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
6804#define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
6805#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
6806#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
6807#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
6808
6809/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
6810#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
6811
6812/* Bit definition for Ethernet DMA Receive Poll Demand Register */
6813#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
6814
6815/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
6816#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
6817
6818/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
6819#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
6820
6821/* Bit definition for Ethernet DMA Status Register */
6822#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
6823#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
6824#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
6825#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
6826 /* combination with EBS[2:0] for GetFlagStatus function */
6827 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
6828 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
6829 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
6830#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
6831 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
6832 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
6833 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
6834 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
6835 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
6836 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
6837#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
6838 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
6839 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
6840 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
6841 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
6842 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
6843 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
6844#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
6845#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
6846#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
6847#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
6848#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
6849#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
6850#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
6851#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
6852#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
6853#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
6854#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
6855#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
6856#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
6857#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
6858#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
6859
6860/* Bit definition for Ethernet DMA Operation Mode Register */
6861#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
6862#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
6863#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
6864#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
6865#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
6866#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
6867 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
6868 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
6869 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
6870 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
6871 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
6872 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
6873 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
6874 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
6875#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
6876#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
6877#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
6878#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
6879 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
6880 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
6881 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
6882 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
6883#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
6884#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
6885
6886/* Bit definition for Ethernet DMA Interrupt Enable Register */
6887#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
6888#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
6889#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
6890#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
6891#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
6892#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
6893#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
6894#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
6895#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
6896#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
6897#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
6898#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
6899#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
6900#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
6901#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
6902
6903/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
6904#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
6905#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
6906#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
6907#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
6908
6909/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
6910#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
6911
6912/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
6913#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
6914
6915/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
6916#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
6917
6918/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
6919#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
6920
6921/**
6922 * @}
6923 */
6924
6925 /**
6926 * @}
6927 */
6928
6929#ifdef USE_STDPERIPH_DRIVER
6930 #include "stm32f2xx_conf.h"
6931#endif /* USE_STDPERIPH_DRIVER */
6932
6933/** @addtogroup Exported_macro
6934 * @{
6935 */
6936
6937#define SET_BIT(REG, BIT) ((REG) |= (BIT))
6938
6939#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
6940
6941#define READ_BIT(REG, BIT) ((REG) & (BIT))
6942
6943#define CLEAR_REG(REG) ((REG) = (0x0))
6944
6945#define WRITE_REG(REG, VAL) ((REG) = (VAL))
6946
6947#define READ_REG(REG) ((REG))
6948
6949#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
6950
6951/**
6952 * @}
6953 */
6954
6955#ifdef __cplusplus
6956}
6957#endif /* __cplusplus */
6958
6959#endif /* __STM32F2xx_H */
6960
6961/**
6962 * @}
6963 */
6964
6965 /**
6966 * @}
6967 */
6968
6969/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/