Blame - src/bsp/lk/platform/stm32f4xx/CMSIS/stm32f4xx.h - T103

#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */

9687

9688

/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */

9689

#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */

9690

9691

/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */

9692

#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */

9693

9694

/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */

9695

#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */

9696

9697

/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */

9698

#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */

9699

9700

/******************************************************************************/

9701

/* Ethernet PTP Registers bits definition */

9702

/******************************************************************************/

9703

9704

/* Bit definition for Ethernet PTP Time Stamp Contol Register */

9705

#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */

9706

#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */

9707

#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */

9708

#define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */

9709

#define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */

9710

#define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */

9711

#define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */

9712

#define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */

9713

#define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */

9714

9715

#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */

9716

#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */

9717

#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */

9718

#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */

9719

#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */

9720

#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */

9721

9722

/* Bit definition for Ethernet PTP Sub-Second Increment Register */

9723

#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */

9724

9725

/* Bit definition for Ethernet PTP Time Stamp High Register */

9726

#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */

9727

9728

/* Bit definition for Ethernet PTP Time Stamp Low Register */

9729

#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */

9730

#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */

9731

9732

/* Bit definition for Ethernet PTP Time Stamp High Update Register */

9733

#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */

9734

9735

/* Bit definition for Ethernet PTP Time Stamp Low Update Register */

9736

#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */

9737

#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */

9738

9739

/* Bit definition for Ethernet PTP Time Stamp Addend Register */

9740

#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */

9741

9742

/* Bit definition for Ethernet PTP Target Time High Register */

9743

#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */

9744

9745

/* Bit definition for Ethernet PTP Target Time Low Register */

9746

#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */

9747

9748

/* Bit definition for Ethernet PTP Time Stamp Status Register */

9749

#define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */

9750

#define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */

9751

9752

/******************************************************************************/

9753

/* Ethernet DMA Registers bits definition */

9754

/******************************************************************************/

9755

9756

/* Bit definition for Ethernet DMA Bus Mode Register */

9757

#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */

9758

#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */

9759

#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */

9760

#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */

9761

#define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */

9762

#define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */

9763

#define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */

9764

#define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */

9765

#define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */

9766

#define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */

9767

#define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */

9768

#define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */

9769

#define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */

9770

#define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */

9771

#define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */

9772

#define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */

9773

#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */

9774

#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */

9775

#define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */

9776

#define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */

9777

#define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */

9778

#define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */

9779

#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */

9780

#define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */

9781

#define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */

9782

#define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */

9783

#define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */

9784

#define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */

9785

#define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */

9786

#define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */

9787

#define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */

9788

#define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */

9789

#define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */

9790

#define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */

9791

#define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */

9792

#define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */

9793

#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */

9794

#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */

9795

#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */

9796

9797

/* Bit definition for Ethernet DMA Transmit Poll Demand Register */

9798

#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */

9799

9800

/* Bit definition for Ethernet DMA Receive Poll Demand Register */

9801

#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */

9802

9803

/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */

9804

#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */

9805

9806

/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */

9807

#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */

9808

9809

/* Bit definition for Ethernet DMA Status Register */

9810

#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */

9811

#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */

9812

#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */

9813

#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */

9814

/* combination with EBS[2:0] for GetFlagStatus function */

9815

#define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */

9816

#define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */

9817

#define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */

9818

#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */

9819

#define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */

9820

#define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */

9821

#define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */

9822

#define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */

9823

#define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */

9824

#define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */

9825

#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */

9826

#define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */

9827

#define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */

9828

#define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */

9829

#define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */

9830

#define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */

9831

#define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */

9832

#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */

9833

#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */

9834

#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */

9835

#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */

9836

#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */

9837

#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */

9838

#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */

9839

#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */

9840

#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */

9841

#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */

9842

#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */

9843

#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */

9844

#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */

9845

#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */

9846

#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */

9847

9848

/* Bit definition for Ethernet DMA Operation Mode Register */

9849

#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */

9850

#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */

9851

#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */

9852

#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */

9853

#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */

9854

#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */

9855

#define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */

9856

#define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */

9857

#define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */

9858

#define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */

9859

#define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */

9860

#define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */

9861

#define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */

9862

#define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */

9863

#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */

9864

#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */

9865

#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */

9866

#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */

9867

#define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */

9868

#define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */

9869

#define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */

9870

#define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */

9871

#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */

9872

#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */

9873

9874

/* Bit definition for Ethernet DMA Interrupt Enable Register */

9875

#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */

9876

#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */

9877

#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */

9878

#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */

9879

#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */

9880

#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */

9881

#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */

9882

#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */

9883

#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */

9884

#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */

9885

#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */

9886

#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */

9887

#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */

9888

#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */

9889

#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */

9890

9891

/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */

9892

#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */

9893

#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */

9894

#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */

9895

#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */

9896

9897

/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */

9898

#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */

9899

9900

/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */

9901

#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */

9902

9903

/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */

9904

#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */

9905

9906

/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */

9907

#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */

/**

*

*/

/**

* @}

*/

#ifdef USE_STDPERIPH_DRIVER

9918

#include "stm32f4xx_conf.h"

9919

#endif /* USE_STDPERIPH_DRIVER */

9920

9921

/** @addtogroup Exported_macro

* @{

*/

#define SET_BIT(REG, BIT) ((REG) |= (BIT))

9926

9927

#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))

9928

9929

#define READ_BIT(REG, BIT) ((REG) & (BIT))

9930

9931

#define CLEAR_REG(REG) ((REG) = (0x0))

9932

9933

#define WRITE_REG(REG, VAL) ((REG) = (VAL))

9934

9935

#define READ_REG(REG) ((REG))

9936

9937

#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))

/**

* @}

*/

#ifdef __cplusplus

}

#endif /* __cplusplus */

9946

9947

#endif /* __STM32F4xx_H */

/**

* @}

*/

/**

* @}

*/

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/