blob: 366c46b63230d50c4c8cebfd26a324b186484f01 [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +08001/*
2 * Copyright (c) 2012 Travis Geiselbrecht
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files
6 * (the "Software"), to deal in the Software without restriction,
7 * including without limitation the rights to use, copy, modify, merge,
8 * publish, distribute, sublicense, and/or sell copies of the Software,
9 * and to permit persons to whom the Software is furnished to do so,
10 * subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23#include <stdarg.h>
24#include <reg.h>
25#include <debug.h>
26#include <stdio.h>
27#include <kernel/thread.h>
28#include <platform/debug.h>
29#include <arch/ops.h>
30#include <dev/uart.h>
31#include <target/debugconfig.h>
32#include <stm32f4xx_rcc.h>
33#include <stm32f4xx_usart.h>
34#include <arch/arm/cm.h>
35
36void stm32_debug_early_init(void)
37{
38 uart_init_early();
39}
40
41/* later in the init process */
42void stm32_debug_init(void)
43{
44 uart_init();
45}
46
47#define ITM_STIM0 0xE0000000
48#define ITM_TCR 0xE0000E80
49
50void platform_dputc(char c)
51{
52 // if ITM is enabled, send character to STIM0
53 if (readl(ITM_TCR) & 1) {
54 while (!readl(ITM_STIM0)) ;
55 writeb(c, ITM_STIM0);
56 }
57
58 if (c == '\n')
59 uart_putc(DEBUG_UART, '\r');
60 uart_putc(DEBUG_UART, c);
61}
62
63int platform_dgetc(char *c, bool wait)
64{
65 int ret = uart_getc(DEBUG_UART, wait);
66 if (ret == -1)
67 return -1;
68 *c = ret;
69 return 0;
70}
71
72void __debugger_console_putc(char c);
73
74#define DCRDR 0xE000EDF8
75
76void _debugmonitor(void) {
77 u32 n;
78 arm_cm_irq_entry();
79 n = readl(DCRDR);
80 if (n & 0x80000000) {
81 switch (n >> 24) {
82 case 0x80: // write to console
83 __debugger_console_putc(n & 0xFF);
84 n = 0;
85 break;
86 default:
87 n = 0x01000000;
88 }
89 writel(n, DCRDR);
90 }
91 arm_cm_irq_exit(1);
92}