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192.168.1.100 / T103 / 1f884588077ad3476b9c91cbb0ee9ee0332bbb68 / . / src / bsp / lk / platform / stm32f7xx / CMSIS / stm32f745xx.h
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rjw1f884582022-01-06 17:20:42 +0800[diff] [blame^]1/**
2 ******************************************************************************
3 * @file stm32f745xx.h
4 * @author MCD Application Team
5 * @version V1.0.1
6 * @date 25-June-2015
7 * @brief CMSIS STM32F745xx Device Peripheral Access Layer Header File.
8 *
9 * This file contains:
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheralÂ’s registers hardware
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44/** @addtogroup CMSIS_Device
45 * @{
46 */
47
48/** @addtogroup stm32f745xx
49 * @{
50 */
51
52#ifndef __STM32F745xx_H
53#define __STM32F745xx_H
54
55#ifdef __cplusplus
56extern "C" {
57#endif /* __cplusplus */
58
59/** @addtogroup Configuration_section_for_CMSIS
60 * @{
61 */
62
63/**
64 * @brief STM32F7xx Interrupt Number Definition, according to the selected device
65 * in @ref Library_configuration_section
66 */
67typedef enum IRQn {
68 /****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
69 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
70 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */
71 BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */
72 UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */
73 SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */
74 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */
75 PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */
76 SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */
77 /****** STM32 specific Interrupt Numbers **********************************************************************/
78 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
79 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
80 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
81 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
82 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
83 RCC_IRQn = 5, /*!< RCC global Interrupt */
84 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
85 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
86 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
87 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
88 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
89 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
90 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
91 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
92 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
93 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
94 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
95 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
96 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
97 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
98 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
99 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
100 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
101 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
102 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
103 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
104 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
105 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
106 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
107 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
108 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
109 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
110 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
111 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
112 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
113 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
114 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
115 USART1_IRQn = 37, /*!< USART1 global Interrupt */
116 USART2_IRQn = 38, /*!< USART2 global Interrupt */
117 USART3_IRQn = 39, /*!< USART3 global Interrupt */
118 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
119 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
120 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
121 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
122 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
123 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
124 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
125 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
126 FMC_IRQn = 48, /*!< FMC global Interrupt */
127 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
128 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
129 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
130 UART4_IRQn = 52, /*!< UART4 global Interrupt */
131 UART5_IRQn = 53, /*!< UART5 global Interrupt */
132 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
133 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
134 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
135 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
136 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
137 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
138 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
139 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
140 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
141 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
142 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
143 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
144 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
145 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
146 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
147 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
148 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
149 USART6_IRQn = 71, /*!< USART6 global interrupt */
150 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
151 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
152 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
153 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
154 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
155 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
156 DCMI_IRQn = 78, /*!< DCMI global interrupt */
157 RNG_IRQn = 80, /*!< RNG global interrupt */
158 FPU_IRQn = 81, /*!< FPU global interrupt */
159 UART7_IRQn = 82, /*!< UART7 global interrupt */
160 UART8_IRQn = 83, /*!< UART8 global interrupt */
161 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
162 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
163 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
164 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
165 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
166 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
167 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
168 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
169 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
170 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
171 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
172 SPDIF_RX_IRQn = 97 /*!< SPDIF-RX global Interrupt */
173} IRQn_Type;
174
175/**
176 * @}
177 */
178
179/**
180 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
181 */
182#define __CM7_REV 0x0000 /*!< Cortex-M7 revision r0p1 */
183#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
184#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
185#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
186#define __FPU_PRESENT 1 /*!< FPU present */
187#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
188#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
189#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
190
191
192#include "system_stm32f7xx.h"
193#include <stdint.h>
194
195/** @addtogroup Peripheral_registers_structures
196 * @{
197 */
198
199/**
200 * @brief Analog to Digital Converter
201 */
202
203typedef struct {
204 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
205 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
206 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
207 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
208 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
209 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
210 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
211 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
212 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
213 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
214 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
215 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
216 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
217 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
218 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
219 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
220 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
221 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
222 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
223 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
224} ADC_TypeDef;
225
226typedef struct {
227 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
228 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
229 __IO uint32_t CDR; /*!< ADC common regular data register for dual
230 AND triple modes, Address offset: ADC1 base address + 0x308 */
231} ADC_Common_TypeDef;
232
233
234/**
235 * @brief Controller Area Network TxMailBox
236 */
237
238typedef struct {
239 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
240 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
241 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
242 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
243} CAN_TxMailBox_TypeDef;
244
245/**
246 * @brief Controller Area Network FIFOMailBox
247 */
248
249typedef struct {
250 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
251 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
252 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
253 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
254} CAN_FIFOMailBox_TypeDef;
255
256/**
257 * @brief Controller Area Network FilterRegister
258 */
259
260typedef struct {
261 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
262 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
263} CAN_FilterRegister_TypeDef;
264
265/**
266 * @brief Controller Area Network
267 */
268
269typedef struct {
270 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
271 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
272 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
273 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
274 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
275 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
276 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
277 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
278 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
279 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
280 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
281 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
282 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
283 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
284 uint32_t RESERVED2; /*!< Reserved, 0x208 */
285 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
286 uint32_t RESERVED3; /*!< Reserved, 0x210 */
287 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
288 uint32_t RESERVED4; /*!< Reserved, 0x218 */
289 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
290 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
291 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
292} CAN_TypeDef;
293
294/**
295 * @brief HDMI-CEC
296 */
297
298typedef struct {
299 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
300 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
301 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
302 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
303 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
304 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
305} CEC_TypeDef;
306
307
308/**
309 * @brief CRC calculation unit
310 */
311
312typedef struct {
313 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
314 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
315 uint8_t RESERVED0; /*!< Reserved, 0x05 */
316 uint16_t RESERVED1; /*!< Reserved, 0x06 */
317 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
318 uint32_t RESERVED2; /*!< Reserved, 0x0C */
319 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
320 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
321} CRC_TypeDef;
322
323/**
324 * @brief Digital to Analog Converter
325 */
326
327typedef struct {
328 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
329 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
330 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
331 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
332 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
333 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
334 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
335 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
336 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
337 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
338 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
339 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
340 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
341 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
342} DAC_TypeDef;
343
344/**
345 * @brief Debug MCU
346 */
347
348typedef struct {
349 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
350 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
351 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
352 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
353} DBGMCU_TypeDef;
354
355/**
356 * @brief DCMI
357 */
358
359typedef struct {
360 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
361 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
362 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
363 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
364 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
365 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
366 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
367 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
368 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
369 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
370 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
371} DCMI_TypeDef;
372
373/**
374 * @brief DMA Controller
375 */
376
377typedef struct {
378 __IO uint32_t CR; /*!< DMA stream x configuration register */
379 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
380 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
381 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
382 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
383 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
384} DMA_Stream_TypeDef;
385
386typedef struct {
387 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
388 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
389 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
390 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
391} DMA_TypeDef;
392
393
394/**
395 * @brief DMA2D Controller
396 */
397
398typedef struct {
399 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
400 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
401 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
402 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
403 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
404 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
405 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
406 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
407 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
408 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
409 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
410 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
411 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
412 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
413 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
414 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
415 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
416 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
417 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
418 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
419 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
420 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
421 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
422} DMA2D_TypeDef;
423
424
425/**
426 * @brief Ethernet MAC
427 */
428
429typedef struct {
430 __IO uint32_t MACCR;
431 __IO uint32_t MACFFR;
432 __IO uint32_t MACHTHR;
433 __IO uint32_t MACHTLR;
434 __IO uint32_t MACMIIAR;
435 __IO uint32_t MACMIIDR;
436 __IO uint32_t MACFCR;
437 __IO uint32_t MACVLANTR; /* 8 */
438 uint32_t RESERVED0[2];
439 __IO uint32_t MACRWUFFR; /* 11 */
440 __IO uint32_t MACPMTCSR;
441 uint32_t RESERVED1[2];
442 __IO uint32_t MACSR; /* 15 */
443 __IO uint32_t MACIMR;
444 __IO uint32_t MACA0HR;
445 __IO uint32_t MACA0LR;
446 __IO uint32_t MACA1HR;
447 __IO uint32_t MACA1LR;
448 __IO uint32_t MACA2HR;
449 __IO uint32_t MACA2LR;
450 __IO uint32_t MACA3HR;
451 __IO uint32_t MACA3LR; /* 24 */
452 uint32_t RESERVED2[40];
453 __IO uint32_t MMCCR; /* 65 */
454 __IO uint32_t MMCRIR;
455 __IO uint32_t MMCTIR;
456 __IO uint32_t MMCRIMR;
457 __IO uint32_t MMCTIMR; /* 69 */
458 uint32_t RESERVED3[14];
459 __IO uint32_t MMCTGFSCCR; /* 84 */
460 __IO uint32_t MMCTGFMSCCR;
461 uint32_t RESERVED4[5];
462 __IO uint32_t MMCTGFCR;
463 uint32_t RESERVED5[10];
464 __IO uint32_t MMCRFCECR;
465 __IO uint32_t MMCRFAECR;
466 uint32_t RESERVED6[10];
467 __IO uint32_t MMCRGUFCR;
468 uint32_t RESERVED7[334];
469 __IO uint32_t PTPTSCR;
470 __IO uint32_t PTPSSIR;
471 __IO uint32_t PTPTSHR;
472 __IO uint32_t PTPTSLR;
473 __IO uint32_t PTPTSHUR;
474 __IO uint32_t PTPTSLUR;
475 __IO uint32_t PTPTSAR;
476 __IO uint32_t PTPTTHR;
477 __IO uint32_t PTPTTLR;
478 __IO uint32_t RESERVED8;
479 __IO uint32_t PTPTSSR;
480 uint32_t RESERVED9[565];
481 __IO uint32_t DMABMR;
482 __IO uint32_t DMATPDR;
483 __IO uint32_t DMARPDR;
484 __IO uint32_t DMARDLAR;
485 __IO uint32_t DMATDLAR;
486 __IO uint32_t DMASR;
487 __IO uint32_t DMAOMR;
488 __IO uint32_t DMAIER;
489 __IO uint32_t DMAMFBOCR;
490 __IO uint32_t DMARSWTR;
491 uint32_t RESERVED10[8];
492 __IO uint32_t DMACHTDR;
493 __IO uint32_t DMACHRDR;
494 __IO uint32_t DMACHTBAR;
495 __IO uint32_t DMACHRBAR;
496} ETH_TypeDef;
497
498/**
499 * @brief External Interrupt/Event Controller
500 */
501
502typedef struct {
503 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
504 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
505 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
506 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
507 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
508 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
509} EXTI_TypeDef;
510
511/**
512 * @brief FLASH Registers
513 */
514
515typedef struct {
516 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
517 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
518 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
519 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
520 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
521 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
522 __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */
523} FLASH_TypeDef;
524
525
526
527/**
528 * @brief Flexible Memory Controller
529 */
530
531typedef struct {
532 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
533} FMC_Bank1_TypeDef;
534
535/**
536 * @brief Flexible Memory Controller Bank1E
537 */
538
539typedef struct {
540 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
541} FMC_Bank1E_TypeDef;
542
543/**
544 * @brief Flexible Memory Controller Bank3
545 */
546
547typedef struct {
548 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
549 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
550 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
551 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
552 uint32_t RESERVED0; /*!< Reserved, 0x90 */
553 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
554} FMC_Bank3_TypeDef;
555
556/**
557 * @brief Flexible Memory Controller Bank5_6
558 */
559
560typedef struct {
561 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
562 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
563 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
564 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
565 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
566} FMC_Bank5_6_TypeDef;
567
568
569/**
570 * @brief General Purpose I/O
571 */
572
573typedef struct {
574 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
575 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
576 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
577 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
578 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
579 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
580 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
581 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
582 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
583} GPIO_TypeDef;
584
585/**
586 * @brief System configuration controller
587 */
588
589typedef struct {
590 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
591 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
592 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
593 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
594 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
595} SYSCFG_TypeDef;
596
597/**
598 * @brief Inter-integrated Circuit Interface
599 */
600
601typedef struct {
602 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
603 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
604 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
605 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
606 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
607 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
608 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
609 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
610 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
611 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
612 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
613} I2C_TypeDef;
614
615/**
616 * @brief Independent WATCHDOG
617 */
618
619typedef struct {
620 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
621 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
622 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
623 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
624 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
625} IWDG_TypeDef;
626
627
628/**
629 * @brief Power Control
630 */
631
632typedef struct {
633 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
634 __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */
635 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
636 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */
637} PWR_TypeDef;
638
639
640/**
641 * @brief Reset and Clock Control
642 */
643
644typedef struct {
645 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
646 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
647 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
648 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
649 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
650 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
651 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
652 uint32_t RESERVED0; /*!< Reserved, 0x1C */
653 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
654 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
655 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
656 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
657 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
658 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
659 uint32_t RESERVED2; /*!< Reserved, 0x3C */
660 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
661 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
662 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
663 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
664 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
665 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
666 uint32_t RESERVED4; /*!< Reserved, 0x5C */
667 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
668 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
669 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
670 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
671 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
672 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
673 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
674 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
675 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
676 __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */
677 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */
678
679} RCC_TypeDef;
680
681/**
682 * @brief Real-Time Clock
683 */
684
685typedef struct {
686 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
687 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
688 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
689 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
690 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
691 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
692 uint32_t reserved; /*!< Reserved */
693 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
694 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
695 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
696 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
697 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
698 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
699 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
700 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
701 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
702 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
703 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
704 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
705 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
706 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
707 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
708 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
709 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
710 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
711 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
712 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
713 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
714 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
715 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
716 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
717 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
718 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
719 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
720 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
721 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
722 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
723 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
724 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
725 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
726 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
727 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
728 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
729 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
730 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
731 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
732 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
733 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
734 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
735 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
736 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
737 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
738} RTC_TypeDef;
739
740
741/**
742 * @brief Serial Audio Interface
743 */
744
745typedef struct {
746 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
747} SAI_TypeDef;
748
749typedef struct {
750 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
751 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
752 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
753 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
754 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
755 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
756 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
757 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
758} SAI_Block_TypeDef;
759
760/**
761 * @brief SPDIF-RX Interface
762 */
763
764typedef struct {
765 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
766 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
767 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
768 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
769 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
770 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
771 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
772} SPDIFRX_TypeDef;
773
774
775/**
776 * @brief SD host Interface
777 */
778
779typedef struct {
780 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
781 __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */
782 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
783 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
784 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
785 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
786 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
787 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
788 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
789 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
790 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
791 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
792 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
793 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
794 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
795 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
796 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
797 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
798 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
799 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
800} SDMMC_TypeDef;
801
802/**
803 * @brief Serial Peripheral Interface
804 */
805
806typedef struct {
807 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
808 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
809 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
810 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
811 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
812 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
813 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
814 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
815 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
816} SPI_TypeDef;
817
818/**
819 * @brief QUAD Serial Peripheral Interface
820 */
821
822typedef struct {
823 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
824 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
825 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
826 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
827 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
828 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
829 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
830 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
831 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
832 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
833 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
834 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
835 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
836} QUADSPI_TypeDef;
837
838/**
839 * @brief TIM
840 */
841
842typedef struct {
843 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
844 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
845 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
846 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
847 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
848 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
849 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
850 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
851 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
852 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
853 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
854 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
855 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
856 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
857 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
858 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
859 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
860 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
861 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
862 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
863 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
864 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
865 __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */
866 __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */
867
868} TIM_TypeDef;
869
870/**
871 * @brief LPTIMIMER
872 */
873typedef struct {
874 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
875 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
876 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
877 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
878 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
879 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
880 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
881 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
882 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
883} LPTIM_TypeDef;
884
885
886/**
887 * @brief Universal Synchronous Asynchronous Receiver Transmitter
888 */
889
890typedef struct {
891 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
892 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
893 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
894 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
895 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
896 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
897 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
898 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
899 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
900 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
901 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
902} USART_TypeDef;
903
904
905/**
906 * @brief Window WATCHDOG
907 */
908
909typedef struct {
910 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
911 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
912 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
913} WWDG_TypeDef;
914
915/**
916 * @brief RNG
917 */
918
919typedef struct {
920 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
921 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
922 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
923} RNG_TypeDef;
924
925/**
926 * @}
927 */
928
929/**
930 * @brief USB_OTG_Core_Registers
931 */
932typedef struct {
933 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
934 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
935 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
936 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
937 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
938 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
939 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
940 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
941 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
942 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
943 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
944 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
945 uint32_t Reserved30[2]; /*!< Reserved 030h */
946 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
947 __IO uint32_t CID; /*!< User ID Register 03Ch */
948 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
949 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
950 uint32_t Reserved6; /*!< Reserved 050h */
951 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
952 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
953 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
954 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
955 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
956 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
957 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
958} USB_OTG_GlobalTypeDef;
959
960
961/**
962 * @brief USB_OTG_device_Registers
963 */
964typedef struct {
965 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
966 __IO uint32_t DCTL; /*!< dev Control Register 804h */
967 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
968 uint32_t Reserved0C; /*!< Reserved 80Ch */
969 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
970 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
971 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
972 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
973 uint32_t Reserved20; /*!< Reserved 820h */
974 uint32_t Reserved9; /*!< Reserved 824h */
975 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
976 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
977 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
978 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
979 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
980 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
981 uint32_t Reserved40; /*!< dedicated EP mask 840h */
982 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
983 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
984 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
985} USB_OTG_DeviceTypeDef;
986
987
988/**
989 * @brief USB_OTG_IN_Endpoint-Specific_Register
990 */
991typedef struct {
992 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
993 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
994 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
995 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
996 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
997 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
998 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
999 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
1000} USB_OTG_INEndpointTypeDef;
1001
1002
1003/**
1004 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1005 */
1006typedef struct {
1007 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
1008 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
1009 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
1010 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
1011 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
1012 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
1013 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
1014} USB_OTG_OUTEndpointTypeDef;
1015
1016
1017/**
1018 * @brief USB_OTG_Host_Mode_Register_Structures
1019 */
1020typedef struct {
1021 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
1022 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
1023 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
1024 uint32_t Reserved40C; /*!< Reserved 40Ch */
1025 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
1026 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
1027 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
1028} USB_OTG_HostTypeDef;
1029
1030/**
1031 * @brief USB_OTG_Host_Channel_Specific_Registers
1032 */
1033typedef struct {
1034 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
1035 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
1036 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
1037 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
1038 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
1039 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
1040 uint32_t Reserved[2]; /*!< Reserved */
1041} USB_OTG_HostChannelTypeDef;
1042/**
1043 * @}
1044 */
1045
1046
1047/** @addtogroup Peripheral_memory_map
1048 * @{
1049 */
1050#define RAMITCM_BASE ((uint32_t)0x00000000) /*!< Base address of :16KB RAM reserved for CPU execution/instruction accessible over ITCM */
1051#define FLASHITCM_BASE ((uint32_t)0x00200000) /*!< Base address of :(up to 1 MB) embedded FLASH memory accessible over ITCM */
1052#define FLASHAXI_BASE ((uint32_t)0x08000000) /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */
1053#define RAMDTCM_BASE ((uint32_t)0x20000000) /*!< Base address of : 64KB system data RAM accessible over DTCM */
1054#define SRAM1_BASE ((uint32_t)0x20010000) /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */
1055#define SRAM2_BASE ((uint32_t)0x2004C000) /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
1056#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */
1057#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Base address of : Backup SRAM(4 KB) */
1058#define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */
1059#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< Base address of : FMC Control registers */
1060#define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< Base address of : QSPI Control registers */
1061#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
1062
1063/* Legacy define */
1064#define FLASH_BASE FLASHAXI_BASE
1065
1066/*!< Peripheral memory map */
1067#define APB1PERIPH_BASE PERIPH_BASE
1068#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
1069#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
1070#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
1071
1072/*!< APB1 peripherals */
1073#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
1074#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
1075#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
1076#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
1077#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
1078#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
1079#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
1080#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
1081#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
1082#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400)
1083#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
1084#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
1085#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
1086#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
1087#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
1088#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000)
1089#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
1090#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
1091#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
1092#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
1093#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
1094#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
1095#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
1096#define I2C4_BASE (APB1PERIPH_BASE + 0x6000)
1097#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
1098#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
1099#define CEC_BASE (APB1PERIPH_BASE + 0x6C00)
1100#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
1101#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
1102#define UART7_BASE (APB1PERIPH_BASE + 0x7800)
1103#define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
1104
1105/*!< APB2 peripherals */
1106#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
1107#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
1108#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
1109#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
1110#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
1111#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
1112#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
1113#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
1114#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00)
1115#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
1116#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
1117#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
1118#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
1119#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
1120#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
1121#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
1122#define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
1123#define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
1124#define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
1125#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00)
1126#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
1127#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
1128#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
1129#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
1130/*!< AHB1 peripherals */
1131#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
1132#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
1133#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
1134#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
1135#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
1136#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
1137#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
1138#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
1139#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
1140#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
1141#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
1142#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
1143#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
1144#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
1145#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
1146#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
1147#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
1148#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
1149#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
1150#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
1151#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
1152#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
1153#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
1154#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
1155#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
1156#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
1157#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
1158#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
1159#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
1160#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
1161#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
1162#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
1163#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
1164#define ETH_MAC_BASE (ETH_BASE)
1165#define ETH_MMC_BASE (ETH_BASE + 0x0100)
1166#define ETH_PTP_BASE (ETH_BASE + 0x0700)
1167#define ETH_DMA_BASE (ETH_BASE + 0x1000)
1168#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)
1169/*!< AHB2 peripherals */
1170#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
1171#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
1172/*!< FMC Bankx registers base address */
1173#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
1174#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
1175#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
1176#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
1177
1178/* Debug MCU registers base address */
1179#define DBGMCU_BASE ((uint32_t )0xE0042000)
1180
1181/*!< USB registers base address */
1182#define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
1183#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
1184
1185#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
1186#define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
1187#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
1188#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
1189#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
1190#define USB_OTG_HOST_BASE ((uint32_t )0x400)
1191#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
1192#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
1193#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
1194#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
1195#define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
1196#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
1197
1198/**
1199 * @}
1200 */
1201
1202/** @addtogroup Peripheral_declaration
1203 * @{
1204 */
1205#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1206#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1207#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1208#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1209#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1210#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1211#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1212#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1213#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1214#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1215#define RTC ((RTC_TypeDef *) RTC_BASE)
1216#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1217#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1218#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1219#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1220#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
1221#define USART2 ((USART_TypeDef *) USART2_BASE)
1222#define USART3 ((USART_TypeDef *) USART3_BASE)
1223#define UART4 ((USART_TypeDef *) UART4_BASE)
1224#define UART5 ((USART_TypeDef *) UART5_BASE)
1225#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1226#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1227#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1228#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
1229#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1230#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1231#define CEC ((CEC_TypeDef *) CEC_BASE)
1232#define PWR ((PWR_TypeDef *) PWR_BASE)
1233#define DAC ((DAC_TypeDef *) DAC_BASE)
1234#define UART7 ((USART_TypeDef *) UART7_BASE)
1235#define UART8 ((USART_TypeDef *) UART8_BASE)
1236#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1237#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1238#define USART1 ((USART_TypeDef *) USART1_BASE)
1239#define USART6 ((USART_TypeDef *) USART6_BASE)
1240#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1241#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1242#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1243#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1244#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1245#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1246#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1247#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1248#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1249#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1250#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1251#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1252#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1253#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1254#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1255#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1256#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1257#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1258#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1259#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1260#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1261#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1262#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1263#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1264#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1265#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1266#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1267#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1268#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1269#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1270#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1271#define CRC ((CRC_TypeDef *) CRC_BASE)
1272#define RCC ((RCC_TypeDef *) RCC_BASE)
1273#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1274#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1275#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1276#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1277#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1278#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1279#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1280#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1281#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1282#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1283#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1284#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1285#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1286#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1287#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1288#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1289#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1290#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1291#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1292#define ETH ((ETH_TypeDef *) ETH_BASE)
1293#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1294#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1295#define RNG ((RNG_TypeDef *) RNG_BASE)
1296#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1297#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1298#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1299#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1300#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1301#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1302#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1303#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1304
1305/**
1306 * @}
1307 */
1308
1309/** @addtogroup Exported_constants
1310 * @{
1311 */
1312
1313/** @addtogroup Peripheral_Registers_Bits_Definition
1314* @{
1315*/
1316
1317/******************************************************************************/
1318/* Peripheral Registers_Bits_Definition */
1319/******************************************************************************/
1320
1321/******************************************************************************/
1322/* */
1323/* Analog to Digital Converter */
1324/* */
1325/******************************************************************************/
1326/******************** Bit definition for ADC_SR register ********************/
1327#define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
1328#define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
1329#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
1330#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
1331#define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
1332#define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
1333
1334/******************* Bit definition for ADC_CR1 register ********************/
1335#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1336#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1337#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1338#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1339#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1340#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1341#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
1342#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
1343#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
1344#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
1345#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
1346#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
1347#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
1348#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
1349#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1350#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
1351#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
1352#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
1353#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
1354#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
1355#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
1356#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1357#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1358#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
1359
1360/******************* Bit definition for ADC_CR2 register ********************/
1361#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
1362#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
1363#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
1364#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
1365#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
1366#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
1367#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1368#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
1369#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
1370#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
1371#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
1372#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1373#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1374#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1375#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
1376#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1377#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1378#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1379#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
1380#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
1381#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1382#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
1383#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
1384#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
1385
1386/****************** Bit definition for ADC_SMPR1 register *******************/
1387#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1388#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1389#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1390#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1391#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1392#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
1393#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
1394#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
1395#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1396#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
1397#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
1398#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
1399#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1400#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
1401#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
1402#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
1403#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1404#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
1405#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
1406#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
1407#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1408#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1409#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1410#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1411#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1412#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
1413#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
1414#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
1415#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1416#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
1417#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
1418#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
1419#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1420#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1421#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1422#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
1423
1424/****************** Bit definition for ADC_SMPR2 register *******************/
1425#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1426#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1427#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1428#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1429#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1430#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
1431#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
1432#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
1433#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1434#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
1435#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
1436#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
1437#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1438#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
1439#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
1440#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
1441#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1442#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
1443#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
1444#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
1445#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1446#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1447#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1448#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1449#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1450#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
1451#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
1452#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
1453#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1454#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
1455#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
1456#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
1457#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1458#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1459#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1460#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
1461#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1462#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
1463#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
1464#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
1465
1466/****************** Bit definition for ADC_JOFR1 register *******************/
1467#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
1468
1469/****************** Bit definition for ADC_JOFR2 register *******************/
1470#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
1471
1472/****************** Bit definition for ADC_JOFR3 register *******************/
1473#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
1474
1475/****************** Bit definition for ADC_JOFR4 register *******************/
1476#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
1477
1478/******************* Bit definition for ADC_HTR register ********************/
1479#define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
1480
1481/******************* Bit definition for ADC_LTR register ********************/
1482#define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
1483
1484/******************* Bit definition for ADC_SQR1 register *******************/
1485#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1486#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1487#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1488#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1489#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1490#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1491#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1492#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1493#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1494#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1495#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1496#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1497#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1498#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1499#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1500#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1501#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1502#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1503#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1504#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1505#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1506#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1507#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1508#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1509#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
1510#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1511#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1512#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1513#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
1514
1515/******************* Bit definition for ADC_SQR2 register *******************/
1516#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1517#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1518#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1519#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1520#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1521#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1522#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1523#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1524#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1525#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1526#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1527#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1528#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1529#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1530#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1531#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1532#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1533#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1534#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1535#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1536#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1537#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1538#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1539#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1540#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1541#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1542#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1543#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1544#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
1545#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
1546#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1547#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
1548#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
1549#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
1550#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
1551#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
1552
1553/******************* Bit definition for ADC_SQR3 register *******************/
1554#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1555#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1556#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1557#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1558#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1559#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1560#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1561#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1562#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1563#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1564#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1565#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1566#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1567#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1568#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1569#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1570#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1571#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1572#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1573#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1574#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1575#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1576#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1577#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1578#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1579#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1580#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1581#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1582#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
1583#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
1584#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1585#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
1586#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
1587#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
1588#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
1589#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
1590
1591/******************* Bit definition for ADC_JSQR register *******************/
1592#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1593#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1594#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1595#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1596#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1597#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1598#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1599#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1600#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1601#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1602#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1603#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1604#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1605#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1606#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1607#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1608#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1609#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1610#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1611#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1612#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1613#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1614#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1615#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1616#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
1617#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1618#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1619
1620/******************* Bit definition for ADC_JDR1 register *******************/
1621#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
1622
1623/******************* Bit definition for ADC_JDR2 register *******************/
1624#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
1625
1626/******************* Bit definition for ADC_JDR3 register *******************/
1627#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
1628
1629/******************* Bit definition for ADC_JDR4 register *******************/
1630#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
1631
1632/******************** Bit definition for ADC_DR register ********************/
1633#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
1634#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
1635
1636/******************* Bit definition for ADC_CSR register ********************/
1637#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
1638#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
1639#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
1640#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
1641#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
1642#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
1643#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
1644#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
1645#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
1646#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
1647#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
1648#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
1649#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
1650#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
1651#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
1652#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
1653#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
1654#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
1655
1656/******************* Bit definition for ADC_CCR register ********************/
1657#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1658#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1659#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1660#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1661#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1662#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1663#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1664#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
1665#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
1666#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
1667#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
1668#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
1669#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1670#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
1671#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
1672#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
1673#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
1674#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
1675#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
1676#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
1677
1678/******************* Bit definition for ADC_CDR register ********************/
1679#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
1680#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
1681
1682/******************************************************************************/
1683/* */
1684/* Controller Area Network */
1685/* */
1686/******************************************************************************/
1687/*!<CAN control and status registers */
1688/******************* Bit definition for CAN_MCR register ********************/
1689#define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
1690#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
1691#define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
1692#define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
1693#define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
1694#define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
1695#define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
1696#define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
1697#define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
1698
1699/******************* Bit definition for CAN_MSR register ********************/
1700#define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
1701#define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
1702#define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
1703#define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
1704#define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
1705#define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
1706#define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
1707#define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
1708#define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
1709
1710/******************* Bit definition for CAN_TSR register ********************/
1711#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
1712#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
1713#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
1714#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
1715#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
1716#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
1717#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
1718#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
1719#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
1720#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
1721#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
1722#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
1723#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
1724#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
1725#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
1726#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
1727
1728#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
1729#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
1730#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
1731#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
1732
1733#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
1734#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
1735#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
1736#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
1737
1738/******************* Bit definition for CAN_RF0R register *******************/
1739#define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
1740#define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
1741#define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
1742#define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
1743
1744/******************* Bit definition for CAN_RF1R register *******************/
1745#define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
1746#define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
1747#define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
1748#define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
1749
1750/******************** Bit definition for CAN_IER register *******************/
1751#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
1752#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
1753#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
1754#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
1755#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
1756#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
1757#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
1758#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
1759#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
1760#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
1761#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
1762#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
1763#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
1764#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
1765
1766/******************** Bit definition for CAN_ESR register *******************/
1767#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
1768#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
1769#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
1770
1771#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
1772#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
1773#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
1774#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
1775
1776#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
1777#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
1778
1779/******************* Bit definition for CAN_BTR register ********************/
1780#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
1781#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
1782#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
1783#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
1784#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
1785#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
1786#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
1787#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1788#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1789#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1790#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
1791#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1792#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1793#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
1794#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
1795
1796/*!<Mailbox registers */
1797/****************** Bit definition for CAN_TI0R register ********************/
1798#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1799#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1800#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1801#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1802#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1803
1804/****************** Bit definition for CAN_TDT0R register *******************/
1805#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1806#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1807#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1808
1809/****************** Bit definition for CAN_TDL0R register *******************/
1810#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1811#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1812#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1813#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1814
1815/****************** Bit definition for CAN_TDH0R register *******************/
1816#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1817#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1818#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1819#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1820
1821/******************* Bit definition for CAN_TI1R register *******************/
1822#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1823#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1824#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1825#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1826#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1827
1828/******************* Bit definition for CAN_TDT1R register ******************/
1829#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1830#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1831#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1832
1833/******************* Bit definition for CAN_TDL1R register ******************/
1834#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1835#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1836#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1837#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1838
1839/******************* Bit definition for CAN_TDH1R register ******************/
1840#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1841#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1842#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1843#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1844
1845/******************* Bit definition for CAN_TI2R register *******************/
1846#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1847#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1848#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1849#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
1850#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1851
1852/******************* Bit definition for CAN_TDT2R register ******************/
1853#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1854#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1855#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1856
1857/******************* Bit definition for CAN_TDL2R register ******************/
1858#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1859#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1860#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1861#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1862
1863/******************* Bit definition for CAN_TDH2R register ******************/
1864#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1865#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1866#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1867#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1868
1869/******************* Bit definition for CAN_RI0R register *******************/
1870#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1871#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1872#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1873#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1874
1875/******************* Bit definition for CAN_RDT0R register ******************/
1876#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1877#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
1878#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1879
1880/******************* Bit definition for CAN_RDL0R register ******************/
1881#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1882#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1883#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1884#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1885
1886/******************* Bit definition for CAN_RDH0R register ******************/
1887#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1888#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1889#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1890#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1891
1892/******************* Bit definition for CAN_RI1R register *******************/
1893#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1894#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1895#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
1896#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1897
1898/******************* Bit definition for CAN_RDT1R register ******************/
1899#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1900#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
1901#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1902
1903/******************* Bit definition for CAN_RDL1R register ******************/
1904#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1905#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1906#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1907#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1908
1909/******************* Bit definition for CAN_RDH1R register ******************/
1910#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1911#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1912#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1913#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1914
1915/*!<CAN filter registers */
1916/******************* Bit definition for CAN_FMR register ********************/
1917#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
1918#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
1919
1920/******************* Bit definition for CAN_FM1R register *******************/
1921#define CAN_FM1R_FBM ((uint32_t)0x3FFF) /*!<Filter Mode */
1922#define CAN_FM1R_FBM0 ((uint32_t)0x0001) /*!<Filter Init Mode bit 0 */
1923#define CAN_FM1R_FBM1 ((uint32_t)0x0002) /*!<Filter Init Mode bit 1 */
1924#define CAN_FM1R_FBM2 ((uint32_t)0x0004) /*!<Filter Init Mode bit 2 */
1925#define CAN_FM1R_FBM3 ((uint32_t)0x0008) /*!<Filter Init Mode bit 3 */
1926#define CAN_FM1R_FBM4 ((uint32_t)0x0010) /*!<Filter Init Mode bit 4 */
1927#define CAN_FM1R_FBM5 ((uint32_t)0x0020) /*!<Filter Init Mode bit 5 */
1928#define CAN_FM1R_FBM6 ((uint32_t)0x0040) /*!<Filter Init Mode bit 6 */
1929#define CAN_FM1R_FBM7 ((uint32_t)0x0080) /*!<Filter Init Mode bit 7 */
1930#define CAN_FM1R_FBM8 ((uint32_t)0x0100) /*!<Filter Init Mode bit 8 */
1931#define CAN_FM1R_FBM9 ((uint32_t)0x0200) /*!<Filter Init Mode bit 9 */
1932#define CAN_FM1R_FBM10 ((uint32_t)0x0400) /*!<Filter Init Mode bit 10 */
1933#define CAN_FM1R_FBM11 ((uint32_t)0x0800) /*!<Filter Init Mode bit 11 */
1934#define CAN_FM1R_FBM12 ((uint32_t)0x1000) /*!<Filter Init Mode bit 12 */
1935#define CAN_FM1R_FBM13 ((uint32_t)0x2000) /*!<Filter Init Mode bit 13 */
1936
1937/******************* Bit definition for CAN_FS1R register *******************/
1938#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
1939#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
1940#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
1941#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
1942#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
1943#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
1944#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
1945#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
1946#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
1947#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
1948#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
1949#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
1950#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
1951#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
1952#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
1953
1954/****************** Bit definition for CAN_FFA1R register *******************/
1955#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
1956#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
1957#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
1958#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
1959#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
1960#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
1961#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
1962#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
1963#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
1964#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
1965#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
1966#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
1967#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
1968#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
1969#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
1970
1971/******************* Bit definition for CAN_FA1R register *******************/
1972#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
1973#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
1974#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
1975#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
1976#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
1977#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
1978#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
1979#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
1980#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
1981#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
1982#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
1983#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
1984#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
1985#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
1986#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
1987
1988/******************* Bit definition for CAN_F0R1 register *******************/
1989#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
1990#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
1991#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
1992#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
1993#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
1994#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
1995#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
1996#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
1997#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
1998#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
1999#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2000#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2001#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2002#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2003#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2004#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2005#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2006#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2007#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2008#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2009#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2010#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2011#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2012#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2013#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2014#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2015#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2016#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2017#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2018#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2019#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2020#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2021
2022/******************* Bit definition for CAN_F1R1 register *******************/
2023#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2024#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2025#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2026#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2027#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2028#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2029#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2030#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2031#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2032#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2033#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2034#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2035#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2036#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2037#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2038#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2039#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2040#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2041#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2042#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2043#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2044#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2045#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2046#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2047#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2048#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2049#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2050#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2051#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2052#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2053#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2054#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2055
2056/******************* Bit definition for CAN_F2R1 register *******************/
2057#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2058#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2059#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2060#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2061#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2062#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2063#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2064#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2065#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2066#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2067#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2068#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2069#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2070#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2071#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2072#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2073#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2074#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2075#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2076#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2077#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2078#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2079#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2080#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2081#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2082#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2083#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2084#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2085#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2086#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2087#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2088#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2089
2090/******************* Bit definition for CAN_F3R1 register *******************/
2091#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2092#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2093#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2094#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2095#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2096#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2097#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2098#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2099#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2100#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2101#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2102#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2103#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2104#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2105#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2106#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2107#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2108#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2109#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2110#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2111#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2112#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2113#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2114#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2115#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2116#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2117#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2118#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2119#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2120#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2121#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2122#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2123
2124/******************* Bit definition for CAN_F4R1 register *******************/
2125#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2126#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2127#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2128#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2129#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2130#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2131#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2132#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2133#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2134#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2135#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2136#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2137#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2138#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2139#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2140#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2141#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2142#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2143#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2144#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2145#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2146#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2147#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2148#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2149#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2150#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2151#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2152#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2153#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2154#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2155#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2156#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2157
2158/******************* Bit definition for CAN_F5R1 register *******************/
2159#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2160#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2161#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2162#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2163#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2164#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2165#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2166#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2167#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2168#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2169#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2170#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2171#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2172#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2173#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2174#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2175#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2176#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2177#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2178#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2179#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2180#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2181#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2182#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2183#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2184#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2185#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2186#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2187#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2188#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2189#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2190#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2191
2192/******************* Bit definition for CAN_F6R1 register *******************/
2193#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2194#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2195#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2196#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2197#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2198#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2199#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2200#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2201#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2202#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2203#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2204#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2205#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2206#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2207#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2208#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2209#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2210#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2211#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2212#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2213#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2214#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2215#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2216#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2217#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2218#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2219#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2220#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2221#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2222#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2223#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2224#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2225
2226/******************* Bit definition for CAN_F7R1 register *******************/
2227#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2228#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2229#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2230#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2231#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2232#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2233#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2234#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2235#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2236#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2237#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2238#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2239#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2240#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2241#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2242#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2243#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2244#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2245#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2246#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2247#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2248#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2249#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2250#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2251#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2252#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2253#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2254#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2255#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2256#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2257#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2258#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2259
2260/******************* Bit definition for CAN_F8R1 register *******************/
2261#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2262#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2263#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2264#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2265#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2266#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2267#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2268#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2269#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2270#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2271#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2272#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2273#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2274#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2275#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2276#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2277#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2278#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2279#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2280#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2281#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2282#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2283#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2284#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2285#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2286#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2287#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2288#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2289#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2290#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2291#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2292#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2293
2294/******************* Bit definition for CAN_F9R1 register *******************/
2295#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2296#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2297#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2298#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2299#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2300#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2301#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2302#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2303#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2304#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2305#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2306#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2307#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2308#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2309#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2310#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2311#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2312#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2313#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2314#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2315#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2316#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2317#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2318#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2319#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2320#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2321#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2322#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2323#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2324#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2325#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2326#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2327
2328/******************* Bit definition for CAN_F10R1 register ******************/
2329#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2330#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2331#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2332#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2333#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2334#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2335#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2336#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2337#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2338#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2339#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2340#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2341#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2342#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2343#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2344#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2345#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2346#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2347#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2348#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2349#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2350#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2351#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2352#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2353#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2354#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2355#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2356#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2357#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2358#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2359#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2360#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2361
2362/******************* Bit definition for CAN_F11R1 register ******************/
2363#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2364#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2365#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2366#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2367#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2368#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2369#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2370#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2371#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2372#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2373#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2374#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2375#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2376#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2377#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2378#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2379#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2380#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2381#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2382#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2383#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2384#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2385#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2386#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2387#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2388#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2389#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2390#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2391#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2392#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2393#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2394#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2395
2396/******************* Bit definition for CAN_F12R1 register ******************/
2397#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2398#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2399#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2400#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2401#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2402#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2403#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2404#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2405#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2406#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2407#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2408#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2409#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2410#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2411#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2412#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2413#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2414#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2415#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2416#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2417#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2418#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2419#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2420#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2421#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2422#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2423#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2424#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2425#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2426#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2427#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2428#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2429
2430/******************* Bit definition for CAN_F13R1 register ******************/
2431#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2432#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2433#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2434#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2435#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2436#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2437#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2438#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2439#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2440#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2441#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2442#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2443#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2444#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2445#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2446#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2447#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2448#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2449#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2450#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2451#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2452#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2453#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2454#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2455#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2456#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2457#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2458#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2459#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2460#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2461#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2462#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2463
2464/******************* Bit definition for CAN_F0R2 register *******************/
2465#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2466#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2467#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2468#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2469#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2470#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2471#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2472#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2473#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2474#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2475#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2476#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2477#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2478#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2479#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2480#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2481#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2482#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2483#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2484#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2485#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2486#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2487#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2488#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2489#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2490#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2491#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2492#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2493#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2494#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2495#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2496#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2497
2498/******************* Bit definition for CAN_F1R2 register *******************/
2499#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2500#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2501#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2502#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2503#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2504#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2505#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2506#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2507#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2508#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2509#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2510#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2511#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2512#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2513#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2514#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2515#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2516#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2517#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2518#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2519#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2520#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2521#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2522#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2523#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2524#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2525#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2526#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2527#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2528#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2529#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2530#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2531
2532/******************* Bit definition for CAN_F2R2 register *******************/
2533#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2534#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2535#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2536#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2537#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2538#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2539#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2540#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2541#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2542#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2543#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2544#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2545#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2546#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2547#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2548#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2549#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2550#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2551#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2552#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2553#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2554#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2555#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2556#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2557#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2558#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2559#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2560#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2561#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2562#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2563#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2564#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2565
2566/******************* Bit definition for CAN_F3R2 register *******************/
2567#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2568#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2569#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2570#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2571#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2572#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2573#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2574#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2575#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2576#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2577#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2578#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2579#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2580#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2581#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2582#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2583#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2584#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2585#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2586#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2587#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2588#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2589#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2590#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2591#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2592#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2593#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2594#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2595#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2596#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2597#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2598#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2599
2600/******************* Bit definition for CAN_F4R2 register *******************/
2601#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2602#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2603#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2604#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2605#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2606#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2607#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2608#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2609#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2610#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2611#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2612#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2613#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2614#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2615#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2616#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2617#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2618#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2619#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2620#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2621#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2622#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2623#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2624#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2625#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2626#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2627#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2628#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2629#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2630#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2631#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2632#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2633
2634/******************* Bit definition for CAN_F5R2 register *******************/
2635#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2636#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2637#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2638#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2639#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2640#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2641#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2642#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2643#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2644#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2645#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2646#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2647#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2648#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2649#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2650#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2651#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2652#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2653#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2654#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2655#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2656#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2657#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2658#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2659#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2660#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2661#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2662#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2663#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2664#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2665#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2666#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2667
2668/******************* Bit definition for CAN_F6R2 register *******************/
2669#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2670#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2671#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2672#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2673#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2674#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2675#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2676#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2677#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2678#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2679#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2680#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2681#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2682#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2683#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2684#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2685#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2686#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2687#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2688#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2689#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2690#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2691#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2692#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2693#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2694#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2695#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2696#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2697#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2698#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2699#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2700#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2701
2702/******************* Bit definition for CAN_F7R2 register *******************/
2703#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2704#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2705#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2706#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2707#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2708#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2709#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2710#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2711#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2712#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2713#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2714#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2715#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2716#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2717#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2718#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2719#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2720#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2721#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2722#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2723#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2724#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2725#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2726#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2727#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2728#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2729#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2730#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2731#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2732#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2733#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2734#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2735
2736/******************* Bit definition for CAN_F8R2 register *******************/
2737#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2738#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2739#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2740#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2741#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2742#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2743#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2744#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2745#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2746#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2747#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2748#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2749#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2750#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2751#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2752#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2753#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2754#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2755#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2756#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2757#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2758#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2759#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2760#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2761#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2762#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2763#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2764#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2765#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2766#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2767#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2768#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2769
2770/******************* Bit definition for CAN_F9R2 register *******************/
2771#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2772#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2773#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2774#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2775#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2776#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2777#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2778#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2779#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2780#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2781#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2782#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2783#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2784#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2785#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2786#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2787#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2788#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2789#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2790#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2791#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2792#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2793#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2794#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2795#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2796#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2797#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2798#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2799#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2800#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2801#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2802#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2803
2804/******************* Bit definition for CAN_F10R2 register ******************/
2805#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2806#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2807#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2808#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2809#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2810#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2811#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2812#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2813#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2814#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2815#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2816#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2817#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2818#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2819#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2820#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2821#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2822#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2823#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2824#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2825#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2826#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2827#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2828#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2829#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2830#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2831#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2832#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2833#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2834#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2835#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2836#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2837
2838/******************* Bit definition for CAN_F11R2 register ******************/
2839#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2840#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2841#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2842#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2843#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2844#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2845#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2846#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2847#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2848#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2849#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2850#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2851#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2852#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2853#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2854#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2855#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2856#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2857#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2858#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2859#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2860#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2861#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2862#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2863#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2864#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2865#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2866#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2867#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2868#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2869#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2870#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2871
2872/******************* Bit definition for CAN_F12R2 register ******************/
2873#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2874#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2875#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2876#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2877#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2878#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2879#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2880#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2881#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2882#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2883#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2884#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2885#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2886#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2887#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2888#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2889#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2890#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2891#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2892#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2893#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2894#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2895#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2896#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2897#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2898#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2899#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2900#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2901#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2902#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2903#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2904#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2905
2906/******************* Bit definition for CAN_F13R2 register ******************/
2907#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2908#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2909#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2910#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2911#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2912#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2913#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2914#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2915#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2916#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2917#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2918#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2919#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2920#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2921#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2922#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2923#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2924#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2925#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2926#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2927#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2928#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2929#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2930#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2931#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2932#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2933#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2934#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2935#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2936#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2937#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2938#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2939
2940/******************************************************************************/
2941/* */
2942/* HDMI-CEC (CEC) */
2943/* */
2944/******************************************************************************/
2945
2946/******************* Bit definition for CEC_CR register *********************/
2947#define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
2948#define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
2949#define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
2950
2951/******************* Bit definition for CEC_CFGR register *******************/
2952#define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
2953#define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
2954#define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
2955#define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
2956#define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Period Error generation */
2957#define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast no Error generation */
2958#define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
2959#define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
2960#define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
2961
2962/******************* Bit definition for CEC_TXDR register *******************/
2963#define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
2964
2965/******************* Bit definition for CEC_RXDR register *******************/
2966#define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
2967
2968/******************* Bit definition for CEC_ISR register ********************/
2969#define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
2970#define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
2971#define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
2972#define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
2973#define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
2974#define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
2975#define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
2976#define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
2977#define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
2978#define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
2979#define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
2980#define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
2981#define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
2982
2983/******************* Bit definition for CEC_IER register ********************/
2984#define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
2985#define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
2986#define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
2987#define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
2988#define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/
2989#define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
2990#define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
2991#define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
2992#define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
2993#define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
2994#define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
2995#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
2996#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
2997
2998/******************************************************************************/
2999/* */
3000/* CRC calculation unit */
3001/* */
3002/******************************************************************************/
3003/******************* Bit definition for CRC_DR register *********************/
3004#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
3005
3006/******************* Bit definition for CRC_IDR register ********************/
3007#define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */
3008
3009/******************** Bit definition for CRC_CR register ********************/
3010#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
3011#define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
3012#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
3013#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
3014#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
3015#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
3016#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
3017#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
3018
3019/******************* Bit definition for CRC_INIT register *******************/
3020#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
3021
3022/******************* Bit definition for CRC_POL register ********************/
3023#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
3024
3025/******************************************************************************/
3026/* */
3027/* Digital to Analog Converter */
3028/* */
3029/******************************************************************************/
3030/******************** Bit definition for DAC_CR register ********************/
3031#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
3032#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
3033#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
3034
3035#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
3036#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
3037#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
3038#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
3039
3040#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
3041#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
3042#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
3043
3044#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
3045#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3046#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3047#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3048#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3049
3050#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
3051#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
3052#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
3053#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
3054
3055#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
3056#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
3057#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
3058#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
3059
3060#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
3061#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
3062#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
3063
3064#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
3065#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3066#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3067#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3068#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3069
3070#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
3071
3072/***************** Bit definition for DAC_SWTRIGR register ******************/
3073#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
3074#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
3075
3076/***************** Bit definition for DAC_DHR12R1 register ******************/
3077#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
3078
3079/***************** Bit definition for DAC_DHR12L1 register ******************/
3080#define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
3081
3082/****************** Bit definition for DAC_DHR8R1 register ******************/
3083#define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
3084
3085/***************** Bit definition for DAC_DHR12R2 register ******************/
3086#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
3087
3088/***************** Bit definition for DAC_DHR12L2 register ******************/
3089#define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
3090
3091/****************** Bit definition for DAC_DHR8R2 register ******************/
3092#define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
3093
3094/***************** Bit definition for DAC_DHR12RD register ******************/
3095#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
3096#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
3097
3098/***************** Bit definition for DAC_DHR12LD register ******************/
3099#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
3100#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
3101
3102/****************** Bit definition for DAC_DHR8RD register ******************/
3103#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
3104#define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
3105
3106/******************* Bit definition for DAC_DOR1 register *******************/
3107#define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
3108
3109/******************* Bit definition for DAC_DOR2 register *******************/
3110#define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
3111
3112/******************** Bit definition for DAC_SR register ********************/
3113#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
3114#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
3115
3116/******************************************************************************/
3117/* */
3118/* Debug MCU */
3119/* */
3120/******************************************************************************/
3121
3122/******************************************************************************/
3123/* */
3124/* DCMI */
3125/* */
3126/******************************************************************************/
3127/******************** Bits definition for DCMI_CR register ******************/
3128#define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
3129#define DCMI_CR_CM ((uint32_t)0x00000002)
3130#define DCMI_CR_CROP ((uint32_t)0x00000004)
3131#define DCMI_CR_JPEG ((uint32_t)0x00000008)
3132#define DCMI_CR_ESS ((uint32_t)0x00000010)
3133#define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
3134#define DCMI_CR_HSPOL ((uint32_t)0x00000040)
3135#define DCMI_CR_VSPOL ((uint32_t)0x00000080)
3136#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
3137#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
3138#define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
3139#define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
3140#define DCMI_CR_CRE ((uint32_t)0x00001000)
3141#define DCMI_CR_ENABLE ((uint32_t)0x00004000)
3142#define DCMI_CR_BSM ((uint32_t)0x00030000)
3143#define DCMI_CR_BSM_0 ((uint32_t)0x00010000)
3144#define DCMI_CR_BSM_1 ((uint32_t)0x00020000)
3145#define DCMI_CR_OEBS ((uint32_t)0x00040000)
3146#define DCMI_CR_LSM ((uint32_t)0x00080000)
3147#define DCMI_CR_OELS ((uint32_t)0x00100000)
3148
3149/******************** Bits definition for DCMI_SR register ******************/
3150#define DCMI_SR_HSYNC ((uint32_t)0x00000001)
3151#define DCMI_SR_VSYNC ((uint32_t)0x00000002)
3152#define DCMI_SR_FNE ((uint32_t)0x00000004)
3153
3154/******************** Bits definition for DCMI_RISR register ****************/
3155#define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
3156#define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
3157#define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
3158#define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
3159#define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
3160
3161/******************** Bits definition for DCMI_IER register *****************/
3162#define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
3163#define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
3164#define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
3165#define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
3166#define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
3167
3168/******************** Bits definition for DCMI_MISR register ****************/
3169#define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
3170#define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
3171#define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
3172#define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
3173#define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
3174
3175/******************** Bits definition for DCMI_ICR register *****************/
3176#define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
3177#define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
3178#define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
3179#define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
3180#define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
3181
3182/******************************************************************************/
3183/* */
3184/* DMA Controller */
3185/* */
3186/******************************************************************************/
3187/******************** Bits definition for DMA_SxCR register *****************/
3188#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
3189#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
3190#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
3191#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
3192#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
3193#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
3194#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
3195#define DMA_SxCR_PBURST ((uint32_t)0x00600000)
3196#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
3197#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
3198#define DMA_SxCR_ACK ((uint32_t)0x00100000)
3199#define DMA_SxCR_CT ((uint32_t)0x00080000)
3200#define DMA_SxCR_DBM ((uint32_t)0x00040000)
3201#define DMA_SxCR_PL ((uint32_t)0x00030000)
3202#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
3203#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
3204#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
3205#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
3206#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
3207#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
3208#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
3209#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
3210#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
3211#define DMA_SxCR_MINC ((uint32_t)0x00000400)
3212#define DMA_SxCR_PINC ((uint32_t)0x00000200)
3213#define DMA_SxCR_CIRC ((uint32_t)0x00000100)
3214#define DMA_SxCR_DIR ((uint32_t)0x000000C0)
3215#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
3216#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
3217#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
3218#define DMA_SxCR_TCIE ((uint32_t)0x00000010)
3219#define DMA_SxCR_HTIE ((uint32_t)0x00000008)
3220#define DMA_SxCR_TEIE ((uint32_t)0x00000004)
3221#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
3222#define DMA_SxCR_EN ((uint32_t)0x00000001)
3223
3224/******************** Bits definition for DMA_SxCNDTR register **************/
3225#define DMA_SxNDT ((uint32_t)0x0000FFFF)
3226#define DMA_SxNDT_0 ((uint32_t)0x00000001)
3227#define DMA_SxNDT_1 ((uint32_t)0x00000002)
3228#define DMA_SxNDT_2 ((uint32_t)0x00000004)
3229#define DMA_SxNDT_3 ((uint32_t)0x00000008)
3230#define DMA_SxNDT_4 ((uint32_t)0x00000010)
3231#define DMA_SxNDT_5 ((uint32_t)0x00000020)
3232#define DMA_SxNDT_6 ((uint32_t)0x00000040)
3233#define DMA_SxNDT_7 ((uint32_t)0x00000080)
3234#define DMA_SxNDT_8 ((uint32_t)0x00000100)
3235#define DMA_SxNDT_9 ((uint32_t)0x00000200)
3236#define DMA_SxNDT_10 ((uint32_t)0x00000400)
3237#define DMA_SxNDT_11 ((uint32_t)0x00000800)
3238#define DMA_SxNDT_12 ((uint32_t)0x00001000)
3239#define DMA_SxNDT_13 ((uint32_t)0x00002000)
3240#define DMA_SxNDT_14 ((uint32_t)0x00004000)
3241#define DMA_SxNDT_15 ((uint32_t)0x00008000)
3242
3243/******************** Bits definition for DMA_SxFCR register ****************/
3244#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
3245#define DMA_SxFCR_FS ((uint32_t)0x00000038)
3246#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
3247#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
3248#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
3249#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
3250#define DMA_SxFCR_FTH ((uint32_t)0x00000003)
3251#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
3252#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
3253
3254/******************** Bits definition for DMA_LISR register *****************/
3255#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
3256#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
3257#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
3258#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
3259#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
3260#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
3261#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
3262#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
3263#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
3264#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
3265#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
3266#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
3267#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
3268#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
3269#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
3270#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
3271#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
3272#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
3273#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
3274#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
3275
3276/******************** Bits definition for DMA_HISR register *****************/
3277#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
3278#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
3279#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
3280#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
3281#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
3282#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
3283#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
3284#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
3285#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
3286#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
3287#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
3288#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
3289#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
3290#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
3291#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
3292#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
3293#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
3294#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
3295#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
3296#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
3297
3298/******************** Bits definition for DMA_LIFCR register ****************/
3299#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
3300#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
3301#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
3302#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
3303#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
3304#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
3305#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
3306#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
3307#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
3308#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
3309#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
3310#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
3311#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
3312#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
3313#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
3314#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
3315#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
3316#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
3317#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
3318#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
3319
3320/******************** Bits definition for DMA_HIFCR register ****************/
3321#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
3322#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
3323#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
3324#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
3325#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
3326#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
3327#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
3328#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
3329#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
3330#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
3331#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
3332#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
3333#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
3334#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
3335#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
3336#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
3337#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
3338#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
3339#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
3340#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
3341
3342/******************************************************************************/
3343/* */
3344/* AHB Master DMA2D Controller (DMA2D) */
3345/* */
3346/******************************************************************************/
3347
3348/******************** Bit definition for DMA2D_CR register ******************/
3349
3350#define DMA2D_CR_START ((uint32_t)0x00000001) /*!< Start transfer */
3351#define DMA2D_CR_SUSP ((uint32_t)0x00000002) /*!< Suspend transfer */
3352#define DMA2D_CR_ABORT ((uint32_t)0x00000004) /*!< Abort transfer */
3353#define DMA2D_CR_TEIE ((uint32_t)0x00000100) /*!< Transfer Error Interrupt Enable */
3354#define DMA2D_CR_TCIE ((uint32_t)0x00000200) /*!< Transfer Complete Interrupt Enable */
3355#define DMA2D_CR_TWIE ((uint32_t)0x00000400) /*!< Transfer Watermark Interrupt Enable */
3356#define DMA2D_CR_CAEIE ((uint32_t)0x00000800) /*!< CLUT Access Error Interrupt Enable */
3357#define DMA2D_CR_CTCIE ((uint32_t)0x00001000) /*!< CLUT Transfer Complete Interrupt Enable */
3358#define DMA2D_CR_CEIE ((uint32_t)0x00002000) /*!< Configuration Error Interrupt Enable */
3359#define DMA2D_CR_MODE ((uint32_t)0x00030000) /*!< DMA2D Mode */
3360
3361/******************** Bit definition for DMA2D_ISR register *****************/
3362
3363#define DMA2D_ISR_TEIF ((uint32_t)0x00000001) /*!< Transfer Error Interrupt Flag */
3364#define DMA2D_ISR_TCIF ((uint32_t)0x00000002) /*!< Transfer Complete Interrupt Flag */
3365#define DMA2D_ISR_TWIF ((uint32_t)0x00000004) /*!< Transfer Watermark Interrupt Flag */
3366#define DMA2D_ISR_CAEIF ((uint32_t)0x00000008) /*!< CLUT Access Error Interrupt Flag */
3367#define DMA2D_ISR_CTCIF ((uint32_t)0x00000010) /*!< CLUT Transfer Complete Interrupt Flag */
3368#define DMA2D_ISR_CEIF ((uint32_t)0x00000020) /*!< Configuration Error Interrupt Flag */
3369
3370/******************** Bit definition for DMA2D_IFSR register ****************/
3371
3372#define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001) /*!< Clears Transfer Error Interrupt Flag */
3373#define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002) /*!< Clears Transfer Complete Interrupt Flag */
3374#define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004) /*!< Clears Transfer Watermark Interrupt Flag */
3375#define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008) /*!< Clears CLUT Access Error Interrupt Flag */
3376#define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010) /*!< Clears CLUT Transfer Complete Interrupt Flag */
3377#define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020) /*!< Clears Configuration Error Interrupt Flag */
3378
3379/******************** Bit definition for DMA2D_FGMAR register ***************/
3380
3381#define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
3382
3383/******************** Bit definition for DMA2D_FGOR register ****************/
3384
3385#define DMA2D_FGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
3386
3387/******************** Bit definition for DMA2D_BGMAR register ***************/
3388
3389#define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
3390
3391/******************** Bit definition for DMA2D_BGOR register ****************/
3392
3393#define DMA2D_BGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
3394
3395/******************** Bit definition for DMA2D_FGPFCCR register *************/
3396
3397#define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
3398#define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
3399#define DMA2D_FGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
3400#define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
3401#define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha mode */
3402#define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
3403
3404/******************** Bit definition for DMA2D_FGCOLR register **************/
3405
3406#define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
3407#define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
3408#define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
3409
3410/******************** Bit definition for DMA2D_BGPFCCR register *************/
3411
3412#define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
3413#define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
3414#define DMA2D_BGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
3415#define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
3416#define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha Mode */
3417#define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
3418
3419/******************** Bit definition for DMA2D_BGCOLR register **************/
3420
3421#define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
3422#define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
3423#define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
3424
3425/******************** Bit definition for DMA2D_FGCMAR register **************/
3426
3427#define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
3428
3429/******************** Bit definition for DMA2D_BGCMAR register **************/
3430
3431#define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
3432
3433/******************** Bit definition for DMA2D_OPFCCR register **************/
3434
3435#define DMA2D_OPFCCR_CM ((uint32_t)0x00000007) /*!< Color mode */
3436
3437/******************** Bit definition for DMA2D_OCOLR register ***************/
3438
3439/*!<Mode_ARGB8888/RGB888 */
3440
3441#define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) /*!< BLUE Value */
3442#define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) /*!< GREEN Value */
3443#define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) /*!< Red Value */
3444#define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /*!< Alpha Channel Value */
3445
3446/*!<Mode_RGB565 */
3447#define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) /*!< BLUE Value */
3448#define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) /*!< GREEN Value */
3449#define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) /*!< Red Value */
3450
3451/*!<Mode_ARGB1555 */
3452#define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) /*!< BLUE Value */
3453#define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) /*!< GREEN Value */
3454#define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) /*!< Red Value */
3455#define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) /*!< Alpha Channel Value */
3456
3457/*!<Mode_ARGB4444 */
3458#define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) /*!< BLUE Value */
3459#define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) /*!< GREEN Value */
3460#define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) /*!< Red Value */
3461#define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) /*!< Alpha Channel Value */
3462
3463/******************** Bit definition for DMA2D_OMAR register ****************/
3464
3465#define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
3466
3467/******************** Bit definition for DMA2D_OOR register *****************/
3468
3469#define DMA2D_OOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
3470
3471/******************** Bit definition for DMA2D_NLR register *****************/
3472
3473#define DMA2D_NLR_NL ((uint32_t)0x0000FFFF) /*!< Number of Lines */
3474#define DMA2D_NLR_PL ((uint32_t)0x3FFF0000) /*!< Pixel per Lines */
3475
3476/******************** Bit definition for DMA2D_LWR register *****************/
3477
3478#define DMA2D_LWR_LW ((uint32_t)0x0000FFFF) /*!< Line Watermark */
3479
3480/******************** Bit definition for DMA2D_AMTCR register ***************/
3481
3482#define DMA2D_AMTCR_EN ((uint32_t)0x00000001) /*!< Enable */
3483#define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) /*!< Dead Time */
3484
3485
3486
3487/******************** Bit definition for DMA2D_FGCLUT register **************/
3488
3489/******************** Bit definition for DMA2D_BGCLUT register **************/
3490
3491
3492/******************************************************************************/
3493/* */
3494/* External Interrupt/Event Controller */
3495/* */
3496/******************************************************************************/
3497/******************* Bit definition for EXTI_IMR register *******************/
3498#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
3499#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
3500#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
3501#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
3502#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
3503#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
3504#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
3505#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
3506#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
3507#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
3508#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
3509#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
3510#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
3511#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
3512#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
3513#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
3514#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
3515#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
3516#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
3517#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
3518#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
3519#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
3520#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
3521#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
3522
3523/******************* Bit definition for EXTI_EMR register *******************/
3524#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
3525#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
3526#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
3527#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
3528#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
3529#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
3530#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
3531#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
3532#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
3533#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
3534#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
3535#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
3536#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
3537#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
3538#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
3539#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
3540#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
3541#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
3542#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
3543#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
3544#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
3545#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
3546#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
3547#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
3548
3549/****************** Bit definition for EXTI_RTSR register *******************/
3550#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
3551#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
3552#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
3553#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
3554#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
3555#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
3556#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
3557#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
3558#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
3559#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
3560#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
3561#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
3562#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
3563#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
3564#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
3565#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
3566#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
3567#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
3568#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
3569#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
3570#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
3571#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
3572#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
3573#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
3574
3575/****************** Bit definition for EXTI_FTSR register *******************/
3576#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
3577#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
3578#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
3579#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
3580#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
3581#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
3582#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
3583#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
3584#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
3585#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
3586#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
3587#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
3588#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
3589#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
3590#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
3591#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
3592#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
3593#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
3594#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
3595#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
3596#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
3597#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
3598#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
3599#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
3600
3601/****************** Bit definition for EXTI_SWIER register ******************/
3602#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
3603#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
3604#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
3605#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
3606#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
3607#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
3608#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
3609#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
3610#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
3611#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
3612#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
3613#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
3614#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
3615#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
3616#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
3617#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
3618#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
3619#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
3620#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
3621#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
3622#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
3623#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
3624#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
3625#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
3626
3627/******************* Bit definition for EXTI_PR register ********************/
3628#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
3629#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
3630#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
3631#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
3632#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
3633#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
3634#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
3635#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
3636#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
3637#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
3638#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
3639#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
3640#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
3641#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
3642#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
3643#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
3644#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
3645#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
3646#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
3647#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
3648#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
3649#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
3650#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
3651#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
3652
3653/******************************************************************************/
3654/* */
3655/* FLASH */
3656/* */
3657/******************************************************************************/
3658/******************* Bits definition for FLASH_ACR register *****************/
3659#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
3660#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
3661#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
3662#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
3663#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
3664#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
3665#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
3666#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
3667#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
3668#define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)
3669#define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)
3670#define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)
3671#define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)
3672#define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)
3673#define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)
3674#define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)
3675#define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)
3676#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
3677#define FLASH_ACR_ARTEN ((uint32_t)0x00000200)
3678#define FLASH_ACR_ARTRST ((uint32_t)0x00000800)
3679
3680/******************* Bits definition for FLASH_SR register ******************/
3681#define FLASH_SR_EOP ((uint32_t)0x00000001)
3682#define FLASH_SR_OPERR ((uint32_t)0x00000002)
3683#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
3684#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
3685#define FLASH_SR_PGPERR ((uint32_t)0x00000040)
3686#define FLASH_SR_ERSERR ((uint32_t)0x00000080)
3687#define FLASH_SR_BSY ((uint32_t)0x00010000)
3688
3689/******************* Bits definition for FLASH_CR register ******************/
3690#define FLASH_CR_PG ((uint32_t)0x00000001)
3691#define FLASH_CR_SER ((uint32_t)0x00000002)
3692#define FLASH_CR_MER ((uint32_t)0x00000004)
3693#define FLASH_CR_SNB ((uint32_t)0x00000078)
3694#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
3695#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
3696#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
3697#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
3698#define FLASH_CR_PSIZE ((uint32_t)0x00000300)
3699#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
3700#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
3701#define FLASH_CR_STRT ((uint32_t)0x00010000)
3702#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
3703#define FLASH_CR_ERRIE ((uint32_t)0x02000000)
3704#define FLASH_CR_LOCK ((uint32_t)0x80000000)
3705
3706/******************* Bits definition for FLASH_OPTCR register ***************/
3707#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
3708#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
3709#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
3710#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
3711#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
3712#define FLASH_OPTCR_WWDG_SW ((uint32_t)0x00000010)
3713#define FLASH_OPTCR_IWDG_SW ((uint32_t)0x00000020)
3714#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
3715#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
3716#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
3717#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
3718#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
3719#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
3720#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
3721#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
3722#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
3723#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
3724#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
3725#define FLASH_OPTCR_nWRP ((uint32_t)0x00FF0000)
3726#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
3727#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
3728#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
3729#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
3730#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
3731#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
3732#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
3733#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
3734#define FLASH_OPTCR_IWDG_STDBY ((uint32_t)0x40000000)
3735#define FLASH_OPTCR_IWDG_STOP ((uint32_t)0x80000000)
3736
3737/******************* Bits definition for FLASH_OPTCR1 register ***************/
3738#define FLASH_OPTCR1_BOOT_ADD0 ((uint32_t)0x0000FFFF)
3739#define FLASH_OPTCR1_BOOT_ADD1 ((uint32_t)0xFFFF0000)
3740
3741
3742
3743/******************************************************************************/
3744/* */
3745/* Flexible Memory Controller */
3746/* */
3747/******************************************************************************/
3748/****************** Bit definition for FMC_BCR1 register *******************/
3749#define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3750#define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3751
3752#define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3753#define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3754#define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3755
3756#define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3757#define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3758#define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3759
3760#define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3761#define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3762#define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3763#define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3764#define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3765#define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3766#define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3767#define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3768#define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3769#define FMC_BCR1_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
3770#define FMC_BCR1_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3771#define FMC_BCR1_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3772#define FMC_BCR1_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3773#define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3774#define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */
3775#define FMC_BCR1_WFDIS ((uint32_t)0x00200000) /*!<Write FIFO Disable */
3776
3777/****************** Bit definition for FMC_BCR2 register *******************/
3778#define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3779#define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3780
3781#define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3782#define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3783#define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3784
3785#define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3786#define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3787#define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3788
3789#define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3790#define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3791#define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3792#define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3793#define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3794#define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3795#define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3796#define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3797#define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3798#define FMC_BCR2_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
3799#define FMC_BCR2_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3800#define FMC_BCR2_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3801#define FMC_BCR2_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3802#define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3803
3804/****************** Bit definition for FMC_BCR3 register *******************/
3805#define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3806#define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3807
3808#define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3809#define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3810#define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3811
3812#define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3813#define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3814#define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3815
3816#define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3817#define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3818#define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3819#define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3820#define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3821#define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3822#define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3823#define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3824#define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3825#define FMC_BCR3_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
3826#define FMC_BCR3_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3827#define FMC_BCR3_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3828#define FMC_BCR3_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3829#define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3830
3831/****************** Bit definition for FMC_BCR4 register *******************/
3832#define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3833#define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3834
3835#define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3836#define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3837#define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3838
3839#define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3840#define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3841#define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3842
3843#define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3844#define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3845#define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3846#define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3847#define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3848#define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3849#define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3850#define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3851#define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3852#define FMC_BCR4_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
3853#define FMC_BCR4_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3854#define FMC_BCR4_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3855#define FMC_BCR4_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3856#define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3857
3858/****************** Bit definition for FMC_BTR1 register ******************/
3859#define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3860#define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3861#define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3862#define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3863#define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3864
3865#define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3866#define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3867#define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3868#define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3869#define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3870
3871#define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3872#define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3873#define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3874#define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3875#define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3876#define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3877#define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3878#define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3879#define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3880
3881#define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3882#define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3883#define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3884#define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3885#define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3886
3887#define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3888#define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3889#define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3890#define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3891#define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3892
3893#define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3894#define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3895#define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3896#define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3897#define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3898
3899#define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3900#define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3901#define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3902
3903/****************** Bit definition for FMC_BTR2 register *******************/
3904#define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3905#define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3906#define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3907#define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3908#define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3909
3910#define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3911#define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3912#define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3913#define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3914#define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3915
3916#define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3917#define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3918#define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3919#define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3920#define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3921#define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3922#define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3923#define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3924#define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3925
3926#define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3927#define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3928#define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3929#define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3930#define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3931
3932#define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3933#define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3934#define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3935#define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3936#define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3937
3938#define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3939#define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3940#define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3941#define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3942#define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3943
3944#define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3945#define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3946#define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3947
3948/******************* Bit definition for FMC_BTR3 register *******************/
3949#define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3950#define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3951#define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3952#define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3953#define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3954
3955#define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3956#define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3957#define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3958#define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3959#define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3960
3961#define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3962#define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3963#define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3964#define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3965#define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3966#define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3967#define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3968#define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3969#define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3970
3971#define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3972#define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3973#define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3974#define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3975#define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3976
3977#define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3978#define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3979#define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3980#define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3981#define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3982
3983#define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3984#define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3985#define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3986#define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3987#define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3988
3989#define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3990#define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3991#define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3992
3993/****************** Bit definition for FMC_BTR4 register *******************/
3994#define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3995#define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3996#define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3997#define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3998#define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3999
4000#define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4001#define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4002#define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4003#define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4004#define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4005
4006#define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4007#define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4008#define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4009#define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4010#define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4011#define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4012#define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4013#define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4014#define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4015
4016#define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4017#define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4018#define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4019#define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4020#define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4021
4022#define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4023#define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4024#define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4025#define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4026#define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4027
4028#define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4029#define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4030#define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4031#define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4032#define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4033
4034#define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4035#define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4036#define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4037
4038/****************** Bit definition for FMC_BWTR1 register ******************/
4039#define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4040#define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4041#define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4042#define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4043#define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4044
4045#define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4046#define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4047#define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4048#define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4049#define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4050
4051#define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4052#define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4053#define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4054#define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4055#define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4056#define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4057#define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4058#define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4059#define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4060
4061#define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4062#define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4063#define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4064#define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4065#define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4066
4067#define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4068#define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4069#define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4070
4071/****************** Bit definition for FMC_BWTR2 register ******************/
4072#define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4073#define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4074#define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4075#define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4076#define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4077
4078#define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4079#define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4080#define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4081#define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4082#define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4083
4084#define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4085#define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4086#define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4087#define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4088#define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4089#define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4090#define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4091#define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4092#define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4093
4094#define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4095#define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4096#define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4097#define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4098#define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4099
4100#define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4101#define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4102#define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4103
4104/****************** Bit definition for FMC_BWTR3 register ******************/
4105#define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4106#define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4107#define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4108#define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4109#define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4110
4111#define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4112#define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4113#define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4114#define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4115#define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4116
4117#define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4118#define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4119#define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4120#define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4121#define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4122#define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4123#define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4124#define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4125#define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4126
4127#define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4128#define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4129#define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4130#define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4131#define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4132
4133#define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4134#define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4135#define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4136
4137/****************** Bit definition for FMC_BWTR4 register ******************/
4138#define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4139#define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4140#define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4141#define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4142#define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4143
4144#define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4145#define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4146#define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4147#define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4148#define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4149
4150#define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4151#define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4152#define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4153#define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4154#define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4155#define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4156#define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4157#define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4158#define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4159
4160#define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4161#define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4162#define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4163#define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4164#define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4165
4166#define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4167#define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4168#define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4169
4170/****************** Bit definition for FMC_PCR register *******************/
4171#define FMC_PCR_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
4172#define FMC_PCR_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
4173#define FMC_PCR_PTYP ((uint32_t)0x00000008) /*!<Memory type */
4174
4175#define FMC_PCR_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
4176#define FMC_PCR_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4177#define FMC_PCR_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4178
4179#define FMC_PCR_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
4180
4181#define FMC_PCR_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
4182#define FMC_PCR_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4183#define FMC_PCR_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4184#define FMC_PCR_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
4185#define FMC_PCR_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
4186
4187#define FMC_PCR_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
4188#define FMC_PCR_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
4189#define FMC_PCR_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
4190#define FMC_PCR_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
4191#define FMC_PCR_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
4192
4193#define FMC_PCR_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
4194#define FMC_PCR_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
4195#define FMC_PCR_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
4196#define FMC_PCR_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
4197
4198/******************* Bit definition for FMC_SR register *******************/
4199#define FMC_SR_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
4200#define FMC_SR_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
4201#define FMC_SR_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
4202#define FMC_SR_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
4203#define FMC_SR_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
4204#define FMC_SR_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
4205#define FMC_SR_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
4206
4207/****************** Bit definition for FMC_PMEM register ******************/
4208#define FMC_PMEM_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
4209#define FMC_PMEM_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4210#define FMC_PMEM_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4211#define FMC_PMEM_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4212#define FMC_PMEM_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4213#define FMC_PMEM_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4214#define FMC_PMEM_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4215#define FMC_PMEM_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4216#define FMC_PMEM_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4217
4218#define FMC_PMEM_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
4219#define FMC_PMEM_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4220#define FMC_PMEM_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4221#define FMC_PMEM_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4222#define FMC_PMEM_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4223#define FMC_PMEM_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4224#define FMC_PMEM_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4225#define FMC_PMEM_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4226#define FMC_PMEM_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4227
4228#define FMC_PMEM_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
4229#define FMC_PMEM_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4230#define FMC_PMEM_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4231#define FMC_PMEM_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4232#define FMC_PMEM_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4233#define FMC_PMEM_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4234#define FMC_PMEM_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4235#define FMC_PMEM_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4236#define FMC_PMEM_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4237
4238#define FMC_PMEM_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
4239#define FMC_PMEM_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4240#define FMC_PMEM_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4241#define FMC_PMEM_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4242#define FMC_PMEM_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4243#define FMC_PMEM_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4244#define FMC_PMEM_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4245#define FMC_PMEM_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4246#define FMC_PMEM_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4247
4248/****************** Bit definition for FMC_PATT register ******************/
4249#define FMC_PATT_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
4250#define FMC_PATT_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4251#define FMC_PATT_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4252#define FMC_PATT_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4253#define FMC_PATT_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4254#define FMC_PATT_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4255#define FMC_PATT_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4256#define FMC_PATT_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4257#define FMC_PATT_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4258
4259#define FMC_PATT_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
4260#define FMC_PATT_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4261#define FMC_PATT_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4262#define FMC_PATT_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4263#define FMC_PATT_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4264#define FMC_PATT_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4265#define FMC_PATT_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4266#define FMC_PATT_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4267#define FMC_PATT_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4268
4269#define FMC_PATT_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
4270#define FMC_PATT_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4271#define FMC_PATT_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4272#define FMC_PATT_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4273#define FMC_PATT_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4274#define FMC_PATT_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4275#define FMC_PATT_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4276#define FMC_PATT_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4277#define FMC_PATT_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4278
4279#define FMC_PATT_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
4280#define FMC_PATT_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4281#define FMC_PATT_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4282#define FMC_PATT_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4283#define FMC_PATT_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4284#define FMC_PATT_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4285#define FMC_PATT_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4286#define FMC_PATT_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4287#define FMC_PATT_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4288
4289/****************** Bit definition for FMC_ECCR register ******************/
4290#define FMC_ECCR_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
4291
4292/****************** Bit definition for FMC_SDCR1 register ******************/
4293#define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
4294#define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4295#define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4296
4297#define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
4298#define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4299#define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4300
4301#define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
4302#define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4303#define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4304
4305#define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
4306
4307#define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
4308#define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
4309#define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
4310
4311#define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */
4312
4313#define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */
4314#define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
4315#define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
4316
4317#define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */
4318
4319#define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */
4320#define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
4321#define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
4322
4323/****************** Bit definition for FMC_SDCR2 register ******************/
4324#define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
4325#define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4326#define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4327
4328#define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
4329#define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4330#define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4331
4332#define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
4333#define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4334#define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4335
4336#define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
4337
4338#define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
4339#define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
4340#define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
4341
4342#define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */
4343
4344#define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */
4345#define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
4346#define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
4347
4348#define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */
4349
4350#define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */
4351#define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
4352#define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
4353
4354/****************** Bit definition for FMC_SDTR1 register ******************/
4355#define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
4356#define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4357#define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4358#define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4359#define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4360
4361#define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
4362#define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4363#define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4364#define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4365#define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4366
4367#define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
4368#define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4369#define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4370#define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4371#define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4372
4373#define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
4374#define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4375#define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4376#define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
4377
4378#define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
4379#define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4380#define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4381#define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4382
4383#define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
4384#define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4385#define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4386#define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4387
4388#define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
4389#define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4390#define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4391#define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4392
4393/****************** Bit definition for FMC_SDTR2 register ******************/
4394#define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
4395#define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4396#define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4397#define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4398#define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4399
4400#define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
4401#define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4402#define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4403#define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4404#define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4405
4406#define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
4407#define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4408#define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4409#define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4410#define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4411
4412#define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
4413#define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4414#define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4415#define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
4416
4417#define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
4418#define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4419#define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4420#define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4421
4422#define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
4423#define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4424#define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4425#define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4426
4427#define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
4428#define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4429#define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4430#define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4431
4432/****************** Bit definition for FMC_SDCMR register ******************/
4433#define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
4434#define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4435#define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4436#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */
4437
4438#define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
4439
4440#define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */
4441
4442#define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */
4443#define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
4444#define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
4445#define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
4446#define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */
4447
4448#define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */
4449
4450/****************** Bit definition for FMC_SDRTR register ******************/
4451#define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */
4452
4453#define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */
4454
4455#define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */
4456
4457/****************** Bit definition for FMC_SDSR register ******************/
4458#define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */
4459
4460#define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */
4461#define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */
4462#define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */
4463
4464#define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */
4465#define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */
4466#define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */
4467
4468#define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */
4469
4470/******************************************************************************/
4471/* */
4472/* General Purpose I/O */
4473/* */
4474/******************************************************************************/
4475/****************** Bits definition for GPIO_MODER register *****************/
4476#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
4477#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
4478#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
4479
4480#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
4481#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
4482#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
4483
4484#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
4485#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
4486#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
4487
4488#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
4489#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
4490#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
4491
4492#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
4493#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
4494#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
4495
4496#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
4497#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
4498#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
4499
4500#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
4501#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
4502#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
4503
4504#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
4505#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
4506#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
4507
4508#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
4509#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
4510#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
4511
4512#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
4513#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
4514#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
4515
4516#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
4517#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
4518#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
4519
4520#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
4521#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
4522#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
4523
4524#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
4525#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
4526#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
4527
4528#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
4529#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
4530#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
4531
4532#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
4533#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
4534#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
4535
4536#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
4537#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
4538#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
4539
4540/****************** Bits definition for GPIO_OTYPER register ****************/
4541#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
4542#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
4543#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
4544#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
4545#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
4546#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
4547#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
4548#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
4549#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
4550#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
4551#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
4552#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
4553#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
4554#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
4555#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
4556#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
4557
4558/****************** Bits definition for GPIO_OSPEEDR register ***************/
4559#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
4560#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
4561#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
4562
4563#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
4564#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
4565#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
4566
4567#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
4568#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
4569#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
4570
4571#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
4572#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
4573#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
4574
4575#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
4576#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
4577#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
4578
4579#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
4580#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
4581#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
4582
4583#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
4584#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
4585#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
4586
4587#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
4588#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
4589#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
4590
4591#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
4592#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
4593#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
4594
4595#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
4596#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
4597#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
4598
4599#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
4600#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
4601#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
4602
4603#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
4604#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
4605#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
4606
4607#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
4608#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
4609#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
4610
4611#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
4612#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
4613#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
4614
4615#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
4616#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
4617#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
4618
4619#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
4620#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
4621#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
4622
4623/****************** Bits definition for GPIO_PUPDR register *****************/
4624#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
4625#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
4626#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
4627
4628#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
4629#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
4630#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
4631
4632#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
4633#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
4634#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
4635
4636#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
4637#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
4638#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
4639
4640#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
4641#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
4642#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
4643
4644#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
4645#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
4646#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
4647
4648#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
4649#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
4650#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
4651
4652#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
4653#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
4654#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
4655
4656#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
4657#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
4658#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
4659
4660#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
4661#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
4662#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
4663
4664#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
4665#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
4666#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
4667
4668#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
4669#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
4670#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
4671
4672#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
4673#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
4674#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
4675
4676#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
4677#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
4678#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
4679
4680#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
4681#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
4682#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
4683
4684#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
4685#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
4686#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
4687
4688/****************** Bits definition for GPIO_IDR register *******************/
4689#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
4690#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
4691#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
4692#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
4693#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
4694#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
4695#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
4696#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
4697#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
4698#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
4699#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
4700#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
4701#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
4702#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
4703#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
4704#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
4705
4706/****************** Bits definition for GPIO_ODR register *******************/
4707#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
4708#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
4709#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
4710#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
4711#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
4712#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
4713#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
4714#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
4715#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
4716#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
4717#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
4718#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
4719#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
4720#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
4721#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
4722#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
4723
4724/****************** Bits definition for GPIO_BSRR register ******************/
4725#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
4726#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
4727#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
4728#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
4729#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
4730#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
4731#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
4732#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
4733#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
4734#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
4735#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
4736#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
4737#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
4738#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
4739#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
4740#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
4741#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
4742#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
4743#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
4744#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
4745#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
4746#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
4747#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
4748#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
4749#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
4750#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
4751#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
4752#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
4753#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
4754#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
4755#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
4756#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
4757
4758/****************** Bit definition for GPIO_LCKR register *********************/
4759#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
4760#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
4761#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
4762#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
4763#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
4764#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
4765#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
4766#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
4767#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
4768#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
4769#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
4770#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
4771#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
4772#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
4773#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
4774#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
4775#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
4776
4777/******************************************************************************/
4778/* */
4779/* Inter-integrated Circuit Interface (I2C) */
4780/* */
4781/******************************************************************************/
4782/******************* Bit definition for I2C_CR1 register *******************/
4783#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
4784#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
4785#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
4786#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
4787#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
4788#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
4789#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
4790#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
4791#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
4792#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
4793#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
4794#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
4795#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
4796#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
4797#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
4798#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
4799#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
4800#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
4801#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
4802#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
4803#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
4804
4805/****************** Bit definition for I2C_CR2 register ********************/
4806#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
4807#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
4808#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
4809#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
4810#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
4811#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
4812#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
4813#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
4814#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
4815#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
4816#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
4817
4818/******************* Bit definition for I2C_OAR1 register ******************/
4819#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
4820#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
4821#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
4822
4823/******************* Bit definition for I2C_OAR2 register ******************/
4824#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
4825#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
4826#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
4827#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
4828#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
4829#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
4830#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
4831#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
4832#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
4833#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
4834#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
4835
4836/******************* Bit definition for I2C_TIMINGR register *******************/
4837#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
4838#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
4839#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
4840#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
4841#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
4842
4843/******************* Bit definition for I2C_TIMEOUTR register *******************/
4844#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
4845#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
4846#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
4847#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B */
4848#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
4849
4850/****************** Bit definition for I2C_ISR register *********************/
4851#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
4852#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
4853#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
4854#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode) */
4855#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
4856#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
4857#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
4858#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
4859#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
4860#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
4861#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
4862#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
4863#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
4864#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
4865#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
4866#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
4867#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
4868
4869/****************** Bit definition for I2C_ICR register *********************/
4870#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
4871#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
4872#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
4873#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
4874#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
4875#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
4876#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
4877#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
4878#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
4879
4880/****************** Bit definition for I2C_PECR register *********************/
4881#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
4882
4883/****************** Bit definition for I2C_RXDR register *********************/
4884#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
4885
4886/****************** Bit definition for I2C_TXDR register *********************/
4887#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
4888
4889
4890/******************************************************************************/
4891/* */
4892/* Independent WATCHDOG */
4893/* */
4894/******************************************************************************/
4895/******************* Bit definition for IWDG_KR register ********************/
4896#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
4897
4898/******************* Bit definition for IWDG_PR register ********************/
4899#define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
4900#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
4901#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
4902#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
4903
4904/******************* Bit definition for IWDG_RLR register *******************/
4905#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
4906
4907/******************* Bit definition for IWDG_SR register ********************/
4908#define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
4909#define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
4910#define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
4911
4912/******************* Bit definition for IWDG_KR register ********************/
4913#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
4914
4915/******************************************************************************/
4916/* */
4917/* Power Control */
4918/* */
4919/******************************************************************************/
4920/******************** Bit definition for PWR_CR1 register ********************/
4921#define PWR_CR1_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
4922#define PWR_CR1_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
4923#define PWR_CR1_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
4924#define PWR_CR1_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
4925
4926#define PWR_CR1_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
4927#define PWR_CR1_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
4928#define PWR_CR1_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
4929#define PWR_CR1_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
4930
4931/*!< PVD level configuration */
4932#define PWR_CR1_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
4933#define PWR_CR1_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
4934#define PWR_CR1_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
4935#define PWR_CR1_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
4936#define PWR_CR1_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
4937#define PWR_CR1_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
4938#define PWR_CR1_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
4939#define PWR_CR1_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
4940
4941#define PWR_CR1_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
4942#define PWR_CR1_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
4943
4944#define PWR_CR1_LPUDS ((uint32_t)0x00000400) /*!< Low-power regulator in deepsleep under-drive mode */
4945#define PWR_CR1_MRUDS ((uint32_t)0x00000800) /*!< Main regulator in deepsleep under-drive mode */
4946
4947#define PWR_CR1_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
4948
4949#define PWR_CR1_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
4950#define PWR_CR1_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
4951#define PWR_CR1_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
4952
4953#define PWR_CR1_ODEN ((uint32_t)0x00010000) /*!< Over Drive enable */
4954#define PWR_CR1_ODSWEN ((uint32_t)0x00020000) /*!< Over Drive switch enabled */
4955#define PWR_CR1_UDEN ((uint32_t)0x000C0000) /*!< Under Drive enable in stop mode */
4956#define PWR_CR1_UDEN_0 ((uint32_t)0x00040000) /*!< Bit 0 */
4957#define PWR_CR1_UDEN_1 ((uint32_t)0x00080000) /*!< Bit 1 */
4958
4959/******************* Bit definition for PWR_CSR1 register ********************/
4960#define PWR_CSR1_WUIF ((uint32_t)0x00000001) /*!< Wake up internal Flag */
4961#define PWR_CSR1_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
4962#define PWR_CSR1_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
4963#define PWR_CSR1_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
4964#define PWR_CSR1_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
4965#define PWR_CSR1_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
4966
4967#define PWR_CSR1_ODRDY ((uint32_t)0x00010000) /*!< Over Drive generator ready */
4968#define PWR_CSR1_ODSWRDY ((uint32_t)0x00020000) /*!< Over Drive Switch ready */
4969#define PWR_CSR1_UDSWRDY ((uint32_t)0x000C0000) /*!< Under Drive ready */
4970
4971/******************** Bit definition for PWR_CR2 register ********************/
4972#define PWR_CR2_CWUPF1 ((uint32_t)0x00000001) /*!< Clear Wakeup Pin Flag for PA0 */
4973#define PWR_CR2_CWUPF2 ((uint32_t)0x00000002) /*!< Clear Wakeup Pin Flag for PA2 */
4974#define PWR_CR2_CWUPF3 ((uint32_t)0x00000004) /*!< Clear Wakeup Pin Flag for PC1 */
4975#define PWR_CR2_CWUPF4 ((uint32_t)0x00000008) /*!< Clear Wakeup Pin Flag for PC13 */
4976#define PWR_CR2_CWUPF5 ((uint32_t)0x00000010) /*!< Clear Wakeup Pin Flag for PI8 */
4977#define PWR_CR2_CWUPF6 ((uint32_t)0x00000020) /*!< Clear Wakeup Pin Flag for PI11 */
4978
4979#define PWR_CR2_WUPP1 ((uint32_t)0x00000100) /*!< Wakeup Pin Polarity bit for PA0 */
4980#define PWR_CR2_WUPP2 ((uint32_t)0x00000200) /*!< Wakeup Pin Polarity bit for PA2 */
4981#define PWR_CR2_WUPP3 ((uint32_t)0x00000400) /*!< Wakeup Pin Polarity bit for PC1 */
4982#define PWR_CR2_WUPP4 ((uint32_t)0x00000800) /*!< Wakeup Pin Polarity bit for PC13 */
4983#define PWR_CR2_WUPP5 ((uint32_t)0x00001000) /*!< Wakeup Pin Polarity bit for PI8 */
4984#define PWR_CR2_WUPP6 ((uint32_t)0x00002000) /*!< Wakeup Pin Polarity bit for PI11 */
4985
4986/******************* Bit definition for PWR_CSR2 register ********************/
4987#define PWR_CSR2_WUPF1 ((uint32_t)0x00000001) /*!< Wakeup Pin Flag for PA0 */
4988#define PWR_CSR2_WUPF2 ((uint32_t)0x00000002) /*!< Wakeup Pin Flag for PA2 */
4989#define PWR_CSR2_WUPF3 ((uint32_t)0x00000004) /*!< Wakeup Pin Flag for PC1 */
4990#define PWR_CSR2_WUPF4 ((uint32_t)0x00000008) /*!< Wakeup Pin Flag for PC13 */
4991#define PWR_CSR2_WUPF5 ((uint32_t)0x00000010) /*!< Wakeup Pin Flag for PI8 */
4992#define PWR_CSR2_WUPF6 ((uint32_t)0x00000020) /*!< Wakeup Pin Flag for PI11 */
4993
4994#define PWR_CSR2_EWUP1 ((uint32_t)0x00000100) /*!< Enable Wakeup Pin PA0 */
4995#define PWR_CSR2_EWUP2 ((uint32_t)0x00000200) /*!< Enable Wakeup Pin PA2 */
4996#define PWR_CSR2_EWUP3 ((uint32_t)0x00000400) /*!< Enable Wakeup Pin PC1 */
4997#define PWR_CSR2_EWUP4 ((uint32_t)0x00000800) /*!< Enable Wakeup Pin PC13 */
4998#define PWR_CSR2_EWUP5 ((uint32_t)0x00001000) /*!< Enable Wakeup Pin PI8 */
4999#define PWR_CSR2_EWUP6 ((uint32_t)0x00002000) /*!< Enable Wakeup Pin PI11 */
5000
5001/******************************************************************************/
5002/* */
5003/* QUADSPI */
5004/* */
5005/******************************************************************************/
5006/***************** Bit definition for QUADSPI_CR register *******************/
5007#define QUADSPI_CR_EN ((uint32_t)0x00000001) /*!< Enable */
5008#define QUADSPI_CR_ABORT ((uint32_t)0x00000002) /*!< Abort request */
5009#define QUADSPI_CR_DMAEN ((uint32_t)0x00000004) /*!< DMA Enable */
5010#define QUADSPI_CR_TCEN ((uint32_t)0x00000008) /*!< Timeout Counter Enable */
5011#define QUADSPI_CR_SSHIFT ((uint32_t)0x00000010) /*!< Sample Shift */
5012#define QUADSPI_CR_DFM ((uint32_t)0x00000040) /*!< Dual Flash Mode */
5013#define QUADSPI_CR_FSEL ((uint32_t)0x00000080) /*!< Flash Select */
5014#define QUADSPI_CR_FTHRES ((uint32_t)0x00000F00) /*!< FTHRES[3:0] FIFO Level */
5015#define QUADSPI_CR_FTHRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */
5016#define QUADSPI_CR_FTHRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */
5017#define QUADSPI_CR_FTHRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */
5018#define QUADSPI_CR_FTHRES_3 ((uint32_t)0x00000800) /*!< Bit 3 */
5019#define QUADSPI_CR_TEIE ((uint32_t)0x00010000) /*!< Transfer Error Interrupt Enable */
5020#define QUADSPI_CR_TCIE ((uint32_t)0x00020000) /*!< Transfer Complete Interrupt Enable */
5021#define QUADSPI_CR_FTIE ((uint32_t)0x00040000) /*!< FIFO Threshold Interrupt Enable */
5022#define QUADSPI_CR_SMIE ((uint32_t)0x00080000) /*!< Status Match Interrupt Enable */
5023#define QUADSPI_CR_TOIE ((uint32_t)0x00100000) /*!< TimeOut Interrupt Enable */
5024#define QUADSPI_CR_APMS ((uint32_t)0x00400000) /*!< Bit 1 */
5025#define QUADSPI_CR_PMM ((uint32_t)0x00800000) /*!< Polling Match Mode */
5026#define QUADSPI_CR_PRESCALER ((uint32_t)0xFF000000) /*!< PRESCALER[7:0] Clock prescaler */
5027#define QUADSPI_CR_PRESCALER_0 ((uint32_t)0x01000000) /*!< Bit 0 */
5028#define QUADSPI_CR_PRESCALER_1 ((uint32_t)0x02000000) /*!< Bit 1 */
5029#define QUADSPI_CR_PRESCALER_2 ((uint32_t)0x04000000) /*!< Bit 2 */
5030#define QUADSPI_CR_PRESCALER_3 ((uint32_t)0x08000000) /*!< Bit 3 */
5031#define QUADSPI_CR_PRESCALER_4 ((uint32_t)0x10000000) /*!< Bit 4 */
5032#define QUADSPI_CR_PRESCALER_5 ((uint32_t)0x20000000) /*!< Bit 5 */
5033#define QUADSPI_CR_PRESCALER_6 ((uint32_t)0x40000000) /*!< Bit 6 */
5034#define QUADSPI_CR_PRESCALER_7 ((uint32_t)0x80000000) /*!< Bit 7 */
5035
5036/***************** Bit definition for QUADSPI_DCR register ******************/
5037#define QUADSPI_DCR_CKMODE ((uint32_t)0x00000001) /*!< Mode 0 / Mode 3 */
5038#define QUADSPI_DCR_CSHT ((uint32_t)0x00000700) /*!< CSHT[2:0]: ChipSelect High Time */
5039#define QUADSPI_DCR_CSHT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
5040#define QUADSPI_DCR_CSHT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
5041#define QUADSPI_DCR_CSHT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
5042#define QUADSPI_DCR_FSIZE ((uint32_t)0x001F0000) /*!< FSIZE[4:0]: Flash Size */
5043#define QUADSPI_DCR_FSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
5044#define QUADSPI_DCR_FSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
5045#define QUADSPI_DCR_FSIZE_2 ((uint32_t)0x00040000) /*!< Bit 2 */
5046#define QUADSPI_DCR_FSIZE_3 ((uint32_t)0x00080000) /*!< Bit 3 */
5047#define QUADSPI_DCR_FSIZE_4 ((uint32_t)0x00100000) /*!< Bit 4 */
5048
5049/****************** Bit definition for QUADSPI_SR register *******************/
5050#define QUADSPI_SR_TEF ((uint32_t)0x00000001) /*!< Transfer Error Flag */
5051#define QUADSPI_SR_TCF ((uint32_t)0x00000002) /*!< Transfer Complete Flag */
5052#define QUADSPI_SR_FTF ((uint32_t)0x00000004) /*!< FIFO Threshlod Flag */
5053#define QUADSPI_SR_SMF ((uint32_t)0x00000008) /*!< Status Match Flag */
5054#define QUADSPI_SR_TOF ((uint32_t)0x00000010) /*!< Timeout Flag */
5055#define QUADSPI_SR_BUSY ((uint32_t)0x00000020) /*!< Busy */
5056#define QUADSPI_SR_FLEVEL ((uint32_t)0x00001F00) /*!< FIFO Threshlod Flag */
5057#define QUADSPI_SR_FLEVEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
5058#define QUADSPI_SR_FLEVEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
5059#define QUADSPI_SR_FLEVEL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
5060#define QUADSPI_SR_FLEVEL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
5061#define QUADSPI_SR_FLEVEL_4 ((uint32_t)0x00001000) /*!< Bit 4 */
5062
5063/****************** Bit definition for QUADSPI_FCR register ******************/
5064#define QUADSPI_FCR_CTEF ((uint32_t)0x00000001) /*!< Clear Transfer Error Flag */
5065#define QUADSPI_FCR_CTCF ((uint32_t)0x00000002) /*!< Clear Transfer Complete Flag */
5066#define QUADSPI_FCR_CSMF ((uint32_t)0x00000008) /*!< Clear Status Match Flag */
5067#define QUADSPI_FCR_CTOF ((uint32_t)0x00000010) /*!< Clear Timeout Flag */
5068
5069/****************** Bit definition for QUADSPI_DLR register ******************/
5070#define QUADSPI_DLR_DL ((uint32_t)0xFFFFFFFF) /*!< DL[31:0]: Data Length */
5071
5072/****************** Bit definition for QUADSPI_CCR register ******************/
5073#define QUADSPI_CCR_INSTRUCTION ((uint32_t)0x000000FF) /*!< INSTRUCTION[7:0]: Instruction */
5074#define QUADSPI_CCR_INSTRUCTION_0 ((uint32_t)0x00000001) /*!< Bit 0 */
5075#define QUADSPI_CCR_INSTRUCTION_1 ((uint32_t)0x00000002) /*!< Bit 1 */
5076#define QUADSPI_CCR_INSTRUCTION_2 ((uint32_t)0x00000004) /*!< Bit 2 */
5077#define QUADSPI_CCR_INSTRUCTION_3 ((uint32_t)0x00000008) /*!< Bit 3 */
5078#define QUADSPI_CCR_INSTRUCTION_4 ((uint32_t)0x00000010) /*!< Bit 4 */
5079#define QUADSPI_CCR_INSTRUCTION_5 ((uint32_t)0x00000020) /*!< Bit 5 */
5080#define QUADSPI_CCR_INSTRUCTION_6 ((uint32_t)0x00000040) /*!< Bit 6 */
5081#define QUADSPI_CCR_INSTRUCTION_7 ((uint32_t)0x00000080) /*!< Bit 7 */
5082#define QUADSPI_CCR_IMODE ((uint32_t)0x00000300) /*!< IMODE[1:0]: Instruction Mode */
5083#define QUADSPI_CCR_IMODE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
5084#define QUADSPI_CCR_IMODE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
5085#define QUADSPI_CCR_ADMODE ((uint32_t)0x00000C00) /*!< ADMODE[1:0]: Address Mode */
5086#define QUADSPI_CCR_ADMODE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5087#define QUADSPI_CCR_ADMODE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5088#define QUADSPI_CCR_ADSIZE ((uint32_t)0x00003000) /*!< ADSIZE[1:0]: Address Size */
5089#define QUADSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000) /*!< Bit 0 */
5090#define QUADSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000) /*!< Bit 1 */
5091#define QUADSPI_CCR_ABMODE ((uint32_t)0x0000C000) /*!< ABMODE[1:0]: Alternate Bytes Mode */
5092#define QUADSPI_CCR_ABMODE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
5093#define QUADSPI_CCR_ABMODE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
5094#define QUADSPI_CCR_ABSIZE ((uint32_t)0x00030000) /*!< ABSIZE[1:0]: Instruction Mode */
5095#define QUADSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
5096#define QUADSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
5097#define QUADSPI_CCR_DCYC ((uint32_t)0x007C0000) /*!< DCYC[4:0]: Dummy Cycles */
5098#define QUADSPI_CCR_DCYC_0 ((uint32_t)0x00040000) /*!< Bit 0 */
5099#define QUADSPI_CCR_DCYC_1 ((uint32_t)0x00080000) /*!< Bit 1 */
5100#define QUADSPI_CCR_DCYC_2 ((uint32_t)0x00100000) /*!< Bit 2 */
5101#define QUADSPI_CCR_DCYC_3 ((uint32_t)0x00200000) /*!< Bit 3 */
5102#define QUADSPI_CCR_DCYC_4 ((uint32_t)0x00400000) /*!< Bit 4 */
5103#define QUADSPI_CCR_DMODE ((uint32_t)0x03000000) /*!< DMODE[1:0]: Data Mode */
5104#define QUADSPI_CCR_DMODE_0 ((uint32_t)0x01000000) /*!< Bit 0 */
5105#define QUADSPI_CCR_DMODE_1 ((uint32_t)0x02000000) /*!< Bit 1 */
5106#define QUADSPI_CCR_FMODE ((uint32_t)0x0C000000) /*!< FMODE[1:0]: Functional Mode */
5107#define QUADSPI_CCR_FMODE_0 ((uint32_t)0x04000000) /*!< Bit 0 */
5108#define QUADSPI_CCR_FMODE_1 ((uint32_t)0x08000000) /*!< Bit 1 */
5109#define QUADSPI_CCR_SIOO ((uint32_t)0x10000000) /*!< SIOO: Send Instruction Only Once Mode */
5110#define QUADSPI_CCR_DHHC ((uint32_t)0x40000000) /*!< DHHC: Delay Half Hclk Cycle */
5111#define QUADSPI_CCR_DDRM ((uint32_t)0x80000000) /*!< DDRM: Double Data Rate Mode */
5112/****************** Bit definition for QUADSPI_AR register *******************/
5113#define QUADSPI_AR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< ADDRESS[31:0]: Address */
5114
5115/****************** Bit definition for QUADSPI_ABR register ******************/
5116#define QUADSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFF) /*!< ALTERNATE[31:0]: Alternate Bytes */
5117
5118/****************** Bit definition for QUADSPI_DR register *******************/
5119#define QUADSPI_DR_DATA ((uint32_t)0xFFFFFFFF) /*!< DATA[31:0]: Data */
5120
5121/****************** Bit definition for QUADSPI_PSMKR register ****************/
5122#define QUADSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFF) /*!< MASK[31:0]: Status Mask */
5123
5124/****************** Bit definition for QUADSPI_PSMAR register ****************/
5125#define QUADSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFF) /*!< MATCH[31:0]: Status Match */
5126
5127/****************** Bit definition for QUADSPI_PIR register *****************/
5128#define QUADSPI_PIR_INTERVAL ((uint32_t)0x0000FFFF) /*!< INTERVAL[15:0]: Polling Interval */
5129
5130/****************** Bit definition for QUADSPI_LPTR register *****************/
5131#define QUADSPI_LPTR_TIMEOUT ((uint32_t)0x0000FFFF) /*!< TIMEOUT[15:0]: Timeout period */
5132
5133/******************************************************************************/
5134/* */
5135/* Reset and Clock Control */
5136/* */
5137/******************************************************************************/
5138/******************** Bit definition for RCC_CR register ********************/
5139#define RCC_CR_HSION ((uint32_t)0x00000001)
5140#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
5141
5142#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
5143#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
5144#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
5145#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
5146#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
5147#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
5148
5149#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
5150#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5151#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5152#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5153#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5154#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5155#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5156#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5157#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5158
5159#define RCC_CR_HSEON ((uint32_t)0x00010000)
5160#define RCC_CR_HSERDY ((uint32_t)0x00020000)
5161#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
5162#define RCC_CR_CSSON ((uint32_t)0x00080000)
5163#define RCC_CR_PLLON ((uint32_t)0x01000000)
5164#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
5165#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
5166#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
5167#define RCC_CR_PLLSAION ((uint32_t)0x10000000)
5168#define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
5169
5170/******************** Bit definition for RCC_PLLCFGR register ***************/
5171#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
5172#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
5173#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
5174#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
5175#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
5176#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
5177#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
5178
5179#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
5180#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
5181#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
5182#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
5183#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
5184#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
5185#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
5186#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
5187#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
5188#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
5189
5190#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
5191#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
5192#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
5193
5194#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
5195#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
5196#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
5197
5198#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
5199#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
5200#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
5201#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
5202#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
5203
5204/******************** Bit definition for RCC_CFGR register ******************/
5205/*!< SW configuration */
5206#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
5207#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
5208#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
5209
5210#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
5211#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
5212#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
5213
5214/*!< SWS configuration */
5215#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
5216#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
5217#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
5218
5219#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
5220#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
5221#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
5222
5223/*!< HPRE configuration */
5224#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
5225#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
5226#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
5227#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
5228#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
5229
5230#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
5231#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
5232#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
5233#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
5234#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
5235#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
5236#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
5237#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
5238#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
5239
5240/*!< PPRE1 configuration */
5241#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
5242#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5243#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5244#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
5245
5246#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
5247#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
5248#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
5249#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
5250#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
5251
5252/*!< PPRE2 configuration */
5253#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
5254#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
5255#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
5256#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
5257
5258#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
5259#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
5260#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
5261#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
5262#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
5263
5264/*!< RTCPRE configuration */
5265#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
5266#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
5267#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
5268#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
5269#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
5270#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
5271
5272/*!< MCO1 configuration */
5273#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
5274#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
5275#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
5276
5277#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
5278
5279#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
5280#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
5281#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
5282#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
5283
5284#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
5285#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
5286#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
5287#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
5288
5289#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
5290#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
5291#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
5292
5293/******************** Bit definition for RCC_CIR register *******************/
5294#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
5295#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
5296#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
5297#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
5298#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
5299#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
5300#define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)
5301#define RCC_CIR_CSSF ((uint32_t)0x00000080)
5302#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
5303#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
5304#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
5305#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
5306#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
5307#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
5308#define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
5309#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
5310#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
5311#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
5312#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
5313#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
5314#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
5315#define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)
5316#define RCC_CIR_CSSC ((uint32_t)0x00800000)
5317
5318/******************** Bit definition for RCC_AHB1RSTR register **************/
5319#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
5320#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
5321#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
5322#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
5323#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
5324#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
5325#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
5326#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
5327#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
5328#define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)
5329#define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)
5330#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
5331#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
5332#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
5333#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
5334#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
5335#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
5336
5337/******************** Bit definition for RCC_AHB2RSTR register **************/
5338#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
5339#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
5340#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
5341
5342/******************** Bit definition for RCC_AHB3RSTR register **************/
5343
5344#define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
5345#define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000002)
5346
5347/******************** Bit definition for RCC_APB1RSTR register **************/
5348#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
5349#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
5350#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
5351#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
5352#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
5353#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
5354#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
5355#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
5356#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
5357#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x00000200)
5358#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
5359#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
5360#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
5361#define RCC_APB1RSTR_SPDIFRXRST ((uint32_t)0x00010000)
5362#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
5363#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
5364#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
5365#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
5366#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
5367#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
5368#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
5369#define RCC_APB1RSTR_I2C4RST ((uint32_t)0x01000000)
5370#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
5371#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
5372#define RCC_APB1RSTR_CECRST ((uint32_t)0x08000000)
5373#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
5374#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
5375#define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
5376#define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
5377
5378/******************** Bit definition for RCC_APB2RSTR register **************/
5379#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
5380#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
5381#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
5382#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
5383#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
5384#define RCC_APB2RSTR_SDMMC1RST ((uint32_t)0x00000800)
5385#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
5386#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
5387#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
5388#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
5389#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
5390#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
5391#define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
5392#define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
5393#define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
5394#define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00800000)
5395
5396/******************** Bit definition for RCC_AHB1ENR register ***************/
5397#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
5398#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
5399#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
5400#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
5401#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
5402#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
5403#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
5404#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
5405#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
5406#define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)
5407#define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)
5408#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
5409#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
5410#define RCC_AHB1ENR_DTCMRAMEN ((uint32_t)0x00100000)
5411#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
5412#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
5413#define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)
5414#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
5415#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
5416#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
5417#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
5418#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
5419#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
5420
5421/******************** Bit definition for RCC_AHB2ENR register ***************/
5422#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
5423#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
5424#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
5425
5426/******************** Bit definition for RCC_AHB3ENR register ***************/
5427
5428#define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
5429#define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000002)
5430
5431/******************** Bit definition for RCC_APB1ENR register ***************/
5432#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
5433#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
5434#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
5435#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
5436#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
5437#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
5438#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
5439#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
5440#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
5441#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x00000200)
5442#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
5443#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
5444#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
5445#define RCC_APB1ENR_SPDIFRXEN ((uint32_t)0x00010000)
5446#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
5447#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
5448#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
5449#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
5450#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
5451#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
5452#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
5453#define RCC_APB1ENR_I2C4EN ((uint32_t)0x01000000)
5454#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
5455#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
5456#define RCC_APB1ENR_CECEN ((uint32_t)0x08000000)
5457#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
5458#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
5459#define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)
5460#define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
5461
5462/******************** Bit definition for RCC_APB2ENR register ***************/
5463#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
5464#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
5465#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
5466#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
5467#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
5468#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
5469#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
5470#define RCC_APB2ENR_SDMMC1EN ((uint32_t)0x00000800)
5471#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
5472#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
5473#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
5474#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
5475#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
5476#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
5477#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
5478#define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
5479#define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)
5480#define RCC_APB2ENR_SAI2EN ((uint32_t)0x00800000)
5481
5482/******************** Bit definition for RCC_AHB1LPENR register *************/
5483#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
5484#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
5485#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
5486#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
5487#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
5488#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
5489#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
5490#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
5491#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
5492#define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
5493#define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)
5494
5495#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
5496#define RCC_AHB1LPENR_AXILPEN ((uint32_t)0x00002000)
5497#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
5498#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
5499#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
5500#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
5501#define RCC_AHB1LPENR_DTCMLPEN ((uint32_t)0x00100000)
5502#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
5503#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
5504#define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)
5505#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
5506#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
5507#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
5508#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
5509#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
5510#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
5511
5512/******************** Bit definition for RCC_AHB2LPENR register *************/
5513#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
5514#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
5515#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
5516
5517/******************** Bit definition for RCC_AHB3LPENR register *************/
5518#define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
5519#define RCC_AHB3LPENR_QSPILPEN ((uint32_t)0x00000002)
5520/******************** Bit definition for RCC_APB1LPENR register *************/
5521#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
5522#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
5523#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
5524#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
5525#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
5526#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
5527#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
5528#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
5529#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
5530#define RCC_APB1LPENR_LPTIM1LPEN ((uint32_t)0x00000200)
5531#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
5532#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
5533#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
5534#define RCC_APB1LPENR_SPDIFRXLPEN ((uint32_t)0x00010000)
5535#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
5536#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
5537#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
5538#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
5539#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
5540#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
5541#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
5542#define RCC_APB1LPENR_I2C4LPEN ((uint32_t)0x01000000)
5543#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
5544#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
5545#define RCC_APB1LPENR_CECLPEN ((uint32_t)0x08000000)
5546#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
5547#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
5548#define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
5549#define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
5550
5551/******************** Bit definition for RCC_APB2LPENR register *************/
5552#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
5553#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
5554#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
5555#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
5556#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
5557#define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
5558#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
5559#define RCC_APB2LPENR_SDMMC1LPEN ((uint32_t)0x00000800)
5560#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
5561#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
5562#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
5563#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
5564#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
5565#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
5566#define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
5567#define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
5568#define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)
5569#define RCC_APB2LPENR_SAI2LPEN ((uint32_t)0x00800000)
5570
5571/******************** Bit definition for RCC_BDCR register ******************/
5572#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
5573#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
5574#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
5575#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018)
5576#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008)
5577#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010)
5578#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
5579#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
5580#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
5581#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
5582#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
5583
5584/******************** Bit definition for RCC_CSR register *******************/
5585#define RCC_CSR_LSION ((uint32_t)0x00000001)
5586#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
5587#define RCC_CSR_RMVF ((uint32_t)0x01000000)
5588#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
5589#define RCC_CSR_PINRSTF ((uint32_t)0x04000000)
5590#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
5591#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
5592#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000)
5593#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
5594#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
5595
5596/******************** Bit definition for RCC_SSCGR register *****************/
5597#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
5598#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
5599#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
5600#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
5601
5602/******************** Bit definition for RCC_PLLI2SCFGR register ************/
5603#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
5604#define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
5605#define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
5606#define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
5607#define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
5608#define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
5609#define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
5610#define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
5611#define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
5612#define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
5613
5614#define RCC_PLLI2SCFGR_PLLI2SP ((uint32_t)0x00030000)
5615#define RCC_PLLI2SCFGR_PLLI2SP_0 ((uint32_t)0x00010000)
5616#define RCC_PLLI2SCFGR_PLLI2SP_1 ((uint32_t)0x00020000)
5617
5618#define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
5619#define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)
5620#define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)
5621#define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)
5622#define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)
5623
5624#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
5625#define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
5626#define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
5627#define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
5628
5629/******************** Bit definition for RCC_PLLSAICFGR register ************/
5630#define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)
5631#define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)
5632#define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)
5633#define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)
5634#define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)
5635#define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400)
5636#define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)
5637#define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)
5638#define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)
5639#define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)
5640
5641#define RCC_PLLSAICFGR_PLLSAIP ((uint32_t)0x00030000)
5642#define RCC_PLLSAICFGR_PLLSAIP_0 ((uint32_t)0x00010000)
5643#define RCC_PLLSAICFGR_PLLSAIP_1 ((uint32_t)0x00020000)
5644
5645#define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)
5646#define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)
5647#define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)
5648#define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000)
5649#define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)
5650
5651#define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000)
5652#define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000)
5653#define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000)
5654#define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000)
5655
5656/******************** Bit definition for RCC_DCKCFGR1 register ***************/
5657#define RCC_DCKCFGR1_PLLI2SDIVQ ((uint32_t)0x0000001F)
5658#define RCC_DCKCFGR1_PLLI2SDIVQ_0 ((uint32_t)0x00000001)
5659#define RCC_DCKCFGR1_PLLI2SDIVQ_1 ((uint32_t)0x00000002)
5660#define RCC_DCKCFGR1_PLLI2SDIVQ_2 ((uint32_t)0x00000004)
5661#define RCC_DCKCFGR1_PLLI2SDIVQ_3 ((uint32_t)0x00000008)
5662#define RCC_DCKCFGR1_PLLI2SDIVQ_4 ((uint32_t)0x00000010)
5663
5664#define RCC_DCKCFGR1_PLLSAIDIVQ ((uint32_t)0x00001F00)
5665#define RCC_DCKCFGR1_PLLSAIDIVQ_0 ((uint32_t)0x00000100)
5666#define RCC_DCKCFGR1_PLLSAIDIVQ_1 ((uint32_t)0x00000200)
5667#define RCC_DCKCFGR1_PLLSAIDIVQ_2 ((uint32_t)0x00000400)
5668#define RCC_DCKCFGR1_PLLSAIDIVQ_3 ((uint32_t)0x00000800)
5669#define RCC_DCKCFGR1_PLLSAIDIVQ_4 ((uint32_t)0x00001000)
5670
5671#define RCC_DCKCFGR1_PLLSAIDIVR ((uint32_t)0x00030000)
5672#define RCC_DCKCFGR1_PLLSAIDIVR_0 ((uint32_t)0x00010000)
5673#define RCC_DCKCFGR1_PLLSAIDIVR_1 ((uint32_t)0x00020000)
5674
5675#define RCC_DCKCFGR1_SAI1SEL ((uint32_t)0x00300000)
5676#define RCC_DCKCFGR1_SAI1SEL_0 ((uint32_t)0x00100000)
5677#define RCC_DCKCFGR1_SAI1SEL_1 ((uint32_t)0x00200000)
5678
5679#define RCC_DCKCFGR1_SAI2SEL ((uint32_t)0x00C00000)
5680#define RCC_DCKCFGR1_SAI2SEL_0 ((uint32_t)0x00400000)
5681#define RCC_DCKCFGR1_SAI2SEL_1 ((uint32_t)0x00800000)
5682
5683#define RCC_DCKCFGR1_TIMPRE ((uint32_t)0x01000000)
5684
5685/******************** Bit definition for RCC_DCKCFGR2 register ***************/
5686#define RCC_DCKCFGR2_USART1SEL ((uint32_t)0x00000003)
5687#define RCC_DCKCFGR2_USART1SEL_0 ((uint32_t)0x00000001)
5688#define RCC_DCKCFGR2_USART1SEL_1 ((uint32_t)0x00000002)
5689#define RCC_DCKCFGR2_USART2SEL ((uint32_t)0x0000000C)
5690#define RCC_DCKCFGR2_USART2SEL_0 ((uint32_t)0x00000004)
5691#define RCC_DCKCFGR2_USART2SEL_1 ((uint32_t)0x00000008)
5692#define RCC_DCKCFGR2_USART3SEL ((uint32_t)0x00000030)
5693#define RCC_DCKCFGR2_USART3SEL_0 ((uint32_t)0x00000010)
5694#define RCC_DCKCFGR2_USART3SEL_1 ((uint32_t)0x00000020)
5695#define RCC_DCKCFGR2_UART4SEL ((uint32_t)0x000000C0)
5696#define RCC_DCKCFGR2_UART4SEL_0 ((uint32_t)0x00000040)
5697#define RCC_DCKCFGR2_UART4SEL_1 ((uint32_t)0x00000080)
5698#define RCC_DCKCFGR2_UART5SEL ((uint32_t)0x00000300)
5699#define RCC_DCKCFGR2_UART5SEL_0 ((uint32_t)0x00000100)
5700#define RCC_DCKCFGR2_UART5SEL_1 ((uint32_t)0x00000200)
5701#define RCC_DCKCFGR2_USART6SEL ((uint32_t)0x00000C00)
5702#define RCC_DCKCFGR2_USART6SEL_0 ((uint32_t)0x00000400)
5703#define RCC_DCKCFGR2_USART6SEL_1 ((uint32_t)0x00000800)
5704#define RCC_DCKCFGR2_UART7SEL ((uint32_t)0x00003000)
5705#define RCC_DCKCFGR2_UART7SEL_0 ((uint32_t)0x00001000)
5706#define RCC_DCKCFGR2_UART7SEL_1 ((uint32_t)0x00002000)
5707#define RCC_DCKCFGR2_UART8SEL ((uint32_t)0x0000C000)
5708#define RCC_DCKCFGR2_UART8SEL_0 ((uint32_t)0x00004000)
5709#define RCC_DCKCFGR2_UART8SEL_1 ((uint32_t)0x00008000)
5710#define RCC_DCKCFGR2_I2C1SEL ((uint32_t)0x00030000)
5711#define RCC_DCKCFGR2_I2C1SEL_0 ((uint32_t)0x00010000)
5712#define RCC_DCKCFGR2_I2C1SEL_1 ((uint32_t)0x00020000)
5713#define RCC_DCKCFGR2_I2C2SEL ((uint32_t)0x000C0000)
5714#define RCC_DCKCFGR2_I2C2SEL_0 ((uint32_t)0x00040000)
5715#define RCC_DCKCFGR2_I2C2SEL_1 ((uint32_t)0x00080000)
5716#define RCC_DCKCFGR2_I2C3SEL ((uint32_t)0x00300000)
5717#define RCC_DCKCFGR2_I2C3SEL_0 ((uint32_t)0x00100000)
5718#define RCC_DCKCFGR2_I2C3SEL_1 ((uint32_t)0x00200000)
5719#define RCC_DCKCFGR2_I2C4SEL ((uint32_t)0x00C00000)
5720#define RCC_DCKCFGR2_I2C4SEL_0 ((uint32_t)0x00400000)
5721#define RCC_DCKCFGR2_I2C4SEL_1 ((uint32_t)0x00800000)
5722#define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0x03000000)
5723#define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x01000000)
5724#define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x02000000)
5725#define RCC_DCKCFGR2_CECSEL ((uint32_t)0x04000000)
5726#define RCC_DCKCFGR2_CK48MSEL ((uint32_t)0x08000000)
5727#define RCC_DCKCFGR2_SDMMC1SEL ((uint32_t)0x10000000)
5728
5729/******************************************************************************/
5730/* */
5731/* RNG */
5732/* */
5733/******************************************************************************/
5734/******************** Bits definition for RNG_CR register *******************/
5735#define RNG_CR_RNGEN ((uint32_t)0x00000004)
5736#define RNG_CR_IE ((uint32_t)0x00000008)
5737
5738/******************** Bits definition for RNG_SR register *******************/
5739#define RNG_SR_DRDY ((uint32_t)0x00000001)
5740#define RNG_SR_CECS ((uint32_t)0x00000002)
5741#define RNG_SR_SECS ((uint32_t)0x00000004)
5742#define RNG_SR_CEIS ((uint32_t)0x00000020)
5743#define RNG_SR_SEIS ((uint32_t)0x00000040)
5744
5745/******************************************************************************/
5746/* */
5747/* Real-Time Clock (RTC) */
5748/* */
5749/******************************************************************************/
5750/******************** Bits definition for RTC_TR register *******************/
5751#define RTC_TR_PM ((uint32_t)0x00400000)
5752#define RTC_TR_HT ((uint32_t)0x00300000)
5753#define RTC_TR_HT_0 ((uint32_t)0x00100000)
5754#define RTC_TR_HT_1 ((uint32_t)0x00200000)
5755#define RTC_TR_HU ((uint32_t)0x000F0000)
5756#define RTC_TR_HU_0 ((uint32_t)0x00010000)
5757#define RTC_TR_HU_1 ((uint32_t)0x00020000)
5758#define RTC_TR_HU_2 ((uint32_t)0x00040000)
5759#define RTC_TR_HU_3 ((uint32_t)0x00080000)
5760#define RTC_TR_MNT ((uint32_t)0x00007000)
5761#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
5762#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
5763#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
5764#define RTC_TR_MNU ((uint32_t)0x00000F00)
5765#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
5766#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
5767#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
5768#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
5769#define RTC_TR_ST ((uint32_t)0x00000070)
5770#define RTC_TR_ST_0 ((uint32_t)0x00000010)
5771#define RTC_TR_ST_1 ((uint32_t)0x00000020)
5772#define RTC_TR_ST_2 ((uint32_t)0x00000040)
5773#define RTC_TR_SU ((uint32_t)0x0000000F)
5774#define RTC_TR_SU_0 ((uint32_t)0x00000001)
5775#define RTC_TR_SU_1 ((uint32_t)0x00000002)
5776#define RTC_TR_SU_2 ((uint32_t)0x00000004)
5777#define RTC_TR_SU_3 ((uint32_t)0x00000008)
5778
5779/******************** Bits definition for RTC_DR register *******************/
5780#define RTC_DR_YT ((uint32_t)0x00F00000)
5781#define RTC_DR_YT_0 ((uint32_t)0x00100000)
5782#define RTC_DR_YT_1 ((uint32_t)0x00200000)
5783#define RTC_DR_YT_2 ((uint32_t)0x00400000)
5784#define RTC_DR_YT_3 ((uint32_t)0x00800000)
5785#define RTC_DR_YU ((uint32_t)0x000F0000)
5786#define RTC_DR_YU_0 ((uint32_t)0x00010000)
5787#define RTC_DR_YU_1 ((uint32_t)0x00020000)
5788#define RTC_DR_YU_2 ((uint32_t)0x00040000)
5789#define RTC_DR_YU_3 ((uint32_t)0x00080000)
5790#define RTC_DR_WDU ((uint32_t)0x0000E000)
5791#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
5792#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
5793#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
5794#define RTC_DR_MT ((uint32_t)0x00001000)
5795#define RTC_DR_MU ((uint32_t)0x00000F00)
5796#define RTC_DR_MU_0 ((uint32_t)0x00000100)
5797#define RTC_DR_MU_1 ((uint32_t)0x00000200)
5798#define RTC_DR_MU_2 ((uint32_t)0x00000400)
5799#define RTC_DR_MU_3 ((uint32_t)0x00000800)
5800#define RTC_DR_DT ((uint32_t)0x00000030)
5801#define RTC_DR_DT_0 ((uint32_t)0x00000010)
5802#define RTC_DR_DT_1 ((uint32_t)0x00000020)
5803#define RTC_DR_DU ((uint32_t)0x0000000F)
5804#define RTC_DR_DU_0 ((uint32_t)0x00000001)
5805#define RTC_DR_DU_1 ((uint32_t)0x00000002)
5806#define RTC_DR_DU_2 ((uint32_t)0x00000004)
5807#define RTC_DR_DU_3 ((uint32_t)0x00000008)
5808
5809/******************** Bits definition for RTC_CR register *******************/
5810#define RTC_CR_ITSE ((uint32_t)0x01000000)
5811#define RTC_CR_COE ((uint32_t)0x00800000)
5812#define RTC_CR_OSEL ((uint32_t)0x00600000)
5813#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
5814#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
5815#define RTC_CR_POL ((uint32_t)0x00100000)
5816#define RTC_CR_COSEL ((uint32_t)0x00080000)
5817#define RTC_CR_BCK ((uint32_t)0x00040000)
5818#define RTC_CR_SUB1H ((uint32_t)0x00020000)
5819#define RTC_CR_ADD1H ((uint32_t)0x00010000)
5820#define RTC_CR_TSIE ((uint32_t)0x00008000)
5821#define RTC_CR_WUTIE ((uint32_t)0x00004000)
5822#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
5823#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
5824#define RTC_CR_TSE ((uint32_t)0x00000800)
5825#define RTC_CR_WUTE ((uint32_t)0x00000400)
5826#define RTC_CR_ALRBE ((uint32_t)0x00000200)
5827#define RTC_CR_ALRAE ((uint32_t)0x00000100)
5828#define RTC_CR_FMT ((uint32_t)0x00000040)
5829#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
5830#define RTC_CR_REFCKON ((uint32_t)0x00000010)
5831#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
5832#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
5833#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
5834#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
5835#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
5836
5837/******************** Bits definition for RTC_ISR register ******************/
5838#define RTC_ISR_ITSF ((uint32_t)0x00020000)
5839#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
5840#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
5841#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
5842#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
5843#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
5844#define RTC_ISR_TSF ((uint32_t)0x00000800)
5845#define RTC_ISR_WUTF ((uint32_t)0x00000400)
5846#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
5847#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
5848#define RTC_ISR_INIT ((uint32_t)0x00000080)
5849#define RTC_ISR_INITF ((uint32_t)0x00000040)
5850#define RTC_ISR_RSF ((uint32_t)0x00000020)
5851#define RTC_ISR_INITS ((uint32_t)0x00000010)
5852#define RTC_ISR_SHPF ((uint32_t)0x00000008)
5853#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
5854#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
5855#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
5856
5857/******************** Bits definition for RTC_PRER register *****************/
5858#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
5859#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
5860
5861/******************** Bits definition for RTC_WUTR register *****************/
5862#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
5863
5864/******************** Bits definition for RTC_ALRMAR register ***************/
5865#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
5866#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
5867#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
5868#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
5869#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
5870#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
5871#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
5872#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
5873#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
5874#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
5875#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
5876#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
5877#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
5878#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
5879#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
5880#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
5881#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
5882#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
5883#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
5884#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
5885#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
5886#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
5887#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
5888#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
5889#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
5890#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
5891#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
5892#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
5893#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
5894#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
5895#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
5896#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
5897#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
5898#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
5899#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
5900#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
5901#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
5902#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
5903#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
5904#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
5905
5906/******************** Bits definition for RTC_ALRMBR register ***************/
5907#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
5908#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
5909#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
5910#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
5911#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
5912#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
5913#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
5914#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
5915#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
5916#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
5917#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
5918#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
5919#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
5920#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
5921#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
5922#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
5923#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
5924#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
5925#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
5926#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
5927#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
5928#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
5929#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
5930#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
5931#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
5932#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
5933#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
5934#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
5935#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
5936#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
5937#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
5938#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
5939#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
5940#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
5941#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
5942#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
5943#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
5944#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
5945#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
5946#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
5947
5948/******************** Bits definition for RTC_WPR register ******************/
5949#define RTC_WPR_KEY ((uint32_t)0x000000FF)
5950
5951/******************** Bits definition for RTC_SSR register ******************/
5952#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
5953
5954/******************** Bits definition for RTC_SHIFTR register ***************/
5955#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
5956#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
5957
5958/******************** Bits definition for RTC_TSTR register *****************/
5959#define RTC_TSTR_PM ((uint32_t)0x00400000)
5960#define RTC_TSTR_HT ((uint32_t)0x00300000)
5961#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
5962#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
5963#define RTC_TSTR_HU ((uint32_t)0x000F0000)
5964#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
5965#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
5966#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
5967#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
5968#define RTC_TSTR_MNT ((uint32_t)0x00007000)
5969#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
5970#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
5971#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
5972#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
5973#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
5974#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
5975#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
5976#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
5977#define RTC_TSTR_ST ((uint32_t)0x00000070)
5978#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
5979#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
5980#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
5981#define RTC_TSTR_SU ((uint32_t)0x0000000F)
5982#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
5983#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
5984#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
5985#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
5986
5987/******************** Bits definition for RTC_TSDR register *****************/
5988#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
5989#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
5990#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
5991#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
5992#define RTC_TSDR_MT ((uint32_t)0x00001000)
5993#define RTC_TSDR_MU ((uint32_t)0x00000F00)
5994#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
5995#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
5996#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
5997#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
5998#define RTC_TSDR_DT ((uint32_t)0x00000030)
5999#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
6000#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
6001#define RTC_TSDR_DU ((uint32_t)0x0000000F)
6002#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
6003#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
6004#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
6005#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
6006
6007/******************** Bits definition for RTC_TSSSR register ****************/
6008#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
6009
6010/******************** Bits definition for RTC_CAL register *****************/
6011#define RTC_CALR_CALP ((uint32_t)0x00008000)
6012#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
6013#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
6014#define RTC_CALR_CALM ((uint32_t)0x000001FF)
6015#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
6016#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
6017#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
6018#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
6019#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
6020#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
6021#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
6022#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
6023#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
6024
6025/******************** Bits definition for RTC_TAMPCR register ****************/
6026#define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000)
6027#define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000)
6028#define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000)
6029#define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000)
6030#define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000)
6031#define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000)
6032#define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000)
6033#define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000)
6034#define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000)
6035#define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000)
6036#define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000)
6037#define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000)
6038#define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000)
6039#define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800)
6040#define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800)
6041#define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000)
6042#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700)
6043#define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100)
6044#define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200)
6045#define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400)
6046#define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080)
6047#define RTC_TAMPCR_TAMP3_TRG ((uint32_t)0x00000040)
6048#define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020)
6049#define RTC_TAMPCR_TAMP2_TRG ((uint32_t)0x00000010)
6050#define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008)
6051#define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004)
6052#define RTC_TAMPCR_TAMP1_TRG ((uint32_t)0x00000002)
6053#define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001)
6054
6055/******************** Bits definition for RTC_ALRMASSR register *************/
6056#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
6057#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
6058#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
6059#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
6060#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
6061#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
6062
6063/******************** Bits definition for RTC_ALRMBSSR register *************/
6064#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
6065#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
6066#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
6067#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
6068#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
6069#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
6070
6071/******************** Bits definition for RTC_OR register ****************/
6072#define RTC_OR_TSINSEL ((uint32_t)0x00000006)
6073#define RTC_OR_TSINSEL_0 ((uint32_t)0x00000002)
6074#define RTC_OR_TSINSEL_1 ((uint32_t)0x00000004)
6075#define RTC_OR_ALARMTYPE ((uint32_t)0x00000008)
6076
6077
6078/******************** Bits definition for RTC_BKP0R register ****************/
6079#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
6080
6081/******************** Bits definition for RTC_BKP1R register ****************/
6082#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
6083
6084/******************** Bits definition for RTC_BKP2R register ****************/
6085#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
6086
6087/******************** Bits definition for RTC_BKP3R register ****************/
6088#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
6089
6090/******************** Bits definition for RTC_BKP4R register ****************/
6091#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
6092
6093/******************** Bits definition for RTC_BKP5R register ****************/
6094#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
6095
6096/******************** Bits definition for RTC_BKP6R register ****************/
6097#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
6098
6099/******************** Bits definition for RTC_BKP7R register ****************/
6100#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
6101
6102/******************** Bits definition for RTC_BKP8R register ****************/
6103#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
6104
6105/******************** Bits definition for RTC_BKP9R register ****************/
6106#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
6107
6108/******************** Bits definition for RTC_BKP10R register ***************/
6109#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
6110
6111/******************** Bits definition for RTC_BKP11R register ***************/
6112#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
6113
6114/******************** Bits definition for RTC_BKP12R register ***************/
6115#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
6116
6117/******************** Bits definition for RTC_BKP13R register ***************/
6118#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
6119
6120/******************** Bits definition for RTC_BKP14R register ***************/
6121#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
6122
6123/******************** Bits definition for RTC_BKP15R register ***************/
6124#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
6125
6126/******************** Bits definition for RTC_BKP16R register ***************/
6127#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
6128
6129/******************** Bits definition for RTC_BKP17R register ***************/
6130#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
6131
6132/******************** Bits definition for RTC_BKP18R register ***************/
6133#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
6134
6135/******************** Bits definition for RTC_BKP19R register ***************/
6136#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
6137
6138/******************** Bits definition for RTC_BKP20R register ***************/
6139#define RTC_BKP20R ((uint32_t)0xFFFFFFFF)
6140
6141/******************** Bits definition for RTC_BKP21R register ***************/
6142#define RTC_BKP21R ((uint32_t)0xFFFFFFFF)
6143
6144/******************** Bits definition for RTC_BKP22R register ***************/
6145#define RTC_BKP22R ((uint32_t)0xFFFFFFFF)
6146
6147/******************** Bits definition for RTC_BKP23R register ***************/
6148#define RTC_BKP23R ((uint32_t)0xFFFFFFFF)
6149
6150/******************** Bits definition for RTC_BKP24R register ***************/
6151#define RTC_BKP24R ((uint32_t)0xFFFFFFFF)
6152
6153/******************** Bits definition for RTC_BKP25R register ***************/
6154#define RTC_BKP25R ((uint32_t)0xFFFFFFFF)
6155
6156/******************** Bits definition for RTC_BKP26R register ***************/
6157#define RTC_BKP26R ((uint32_t)0xFFFFFFFF)
6158
6159/******************** Bits definition for RTC_BKP27R register ***************/
6160#define RTC_BKP27R ((uint32_t)0xFFFFFFFF)
6161
6162/******************** Bits definition for RTC_BKP28R register ***************/
6163#define RTC_BKP28R ((uint32_t)0xFFFFFFFF)
6164
6165/******************** Bits definition for RTC_BKP29R register ***************/
6166#define RTC_BKP29R ((uint32_t)0xFFFFFFFF)
6167
6168/******************** Bits definition for RTC_BKP30R register ***************/
6169#define RTC_BKP30R ((uint32_t)0xFFFFFFFF)
6170
6171/******************** Bits definition for RTC_BKP31R register ***************/
6172#define RTC_BKP31R ((uint32_t)0xFFFFFFFF)
6173
6174/******************** Number of backup registers ******************************/
6175#define RTC_BKP_NUMBER ((uint32_t)0x00000020)
6176
6177
6178/******************************************************************************/
6179/* */
6180/* Serial Audio Interface */
6181/* */
6182/******************************************************************************/
6183/******************** Bit definition for SAI_GCR register *******************/
6184#define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
6185#define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /*!<Bit 0 */
6186#define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /*!<Bit 1 */
6187
6188#define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
6189#define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /*!<Bit 0 */
6190#define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /*!<Bit 1 */
6191
6192/******************* Bit definition for SAI_xCR1 register *******************/
6193#define SAI_xCR1_MODE ((uint32_t)0x00000003) /*!<MODE[1:0] bits (Audio Block Mode) */
6194#define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
6195#define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
6196
6197#define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /*!<PRTCFG[1:0] bits (Protocol Configuration) */
6198#define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /*!<Bit 0 */
6199#define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /*!<Bit 1 */
6200
6201#define SAI_xCR1_DS ((uint32_t)0x000000E0) /*!<DS[1:0] bits (Data Size) */
6202#define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
6203#define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
6204#define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
6205
6206#define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /*!<LSB First Configuration */
6207#define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /*!<ClocK STRobing edge */
6208
6209#define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /*!<SYNCEN[1:0](SYNChronization ENable) */
6210#define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /*!<Bit 0 */
6211#define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /*!<Bit 1 */
6212
6213#define SAI_xCR1_MONO ((uint32_t)0x00001000) /*!<Mono mode */
6214#define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /*!<Output Drive */
6215#define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /*!<Audio Block enable */
6216#define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
6217#define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
6218
6219#define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
6220#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
6221#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
6222#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
6223#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
6224
6225/******************* Bit definition for SAI_xCR2 register *******************/
6226#define SAI_xCR2_FTH ((uint32_t)0x00000007) /*!<FTH[2:0](Fifo THreshold) */
6227#define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
6228#define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
6229#define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
6230
6231#define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
6232#define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
6233#define SAI_xCR2_MUTE ((uint32_t)0x00000020) /*!<Mute mode */
6234#define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /*!<Muate value */
6235
6236#define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /*!<MUTECNT[5:0] (MUTE counter) */
6237#define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /*!<Bit 0 */
6238#define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /*!<Bit 1 */
6239#define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /*!<Bit 2 */
6240#define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /*!<Bit 3 */
6241#define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */
6242#define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */
6243
6244#define SAI_xCR2_CPL ((uint32_t)0x00080000) /*!< Complement Bit */
6245
6246#define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */
6247#define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */
6248#define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /*!<Bit 1 */
6249
6250/****************** Bit definition for SAI_xFRCR register *******************/
6251#define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /*!<FRL[1:0](Frame length) */
6252#define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
6253#define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
6254#define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
6255#define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /*!<Bit 3 */
6256#define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /*!<Bit 4 */
6257#define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /*!<Bit 5 */
6258#define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /*!<Bit 6 */
6259#define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /*!<Bit 7 */
6260
6261#define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /*!<FRL[1:0] (Frame synchronization active level length) */
6262#define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
6263#define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
6264#define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
6265#define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
6266#define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
6267#define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
6268#define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
6269
6270#define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /*!< Frame Synchronization Definition */
6271#define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /*!<Frame Synchronization POLarity */
6272#define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /*!<Frame Synchronization OFFset */
6273
6274/****************** Bit definition for SAI_xSLOTR register *******************/
6275#define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /*!<FRL[4:0](First Bit Offset) */
6276#define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /*!<Bit 0 */
6277#define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /*!<Bit 1 */
6278#define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /*!<Bit 2 */
6279#define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /*!<Bit 3 */
6280#define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /*!<Bit 4 */
6281
6282#define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /*!<SLOTSZ[1:0] (Slot size) */
6283#define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /*!<Bit 0 */
6284#define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /*!<Bit 1 */
6285
6286#define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
6287#define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /*!<Bit 0 */
6288#define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /*!<Bit 1 */
6289#define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /*!<Bit 2 */
6290#define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /*!<Bit 3 */
6291
6292#define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /*!<SLOTEN[15:0] (Slot Enable) */
6293
6294/******************* Bit definition for SAI_xIMR register *******************/
6295#define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /*!<Overrun underrun interrupt enable */
6296#define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /*!<Mute detection interrupt enable */
6297#define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /*!<Wrong Clock Configuration interrupt enable */
6298#define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /*!<FIFO request interrupt enable */
6299#define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /*!<Codec not ready interrupt enable */
6300#define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection interrupt enable */
6301#define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /*!<Late frame synchronization detection interrupt enable */
6302
6303/******************** Bit definition for SAI_xSR register *******************/
6304#define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /*!<Overrun underrun */
6305#define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /*!<Mute detection */
6306#define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /*!<Wrong Clock Configuration */
6307#define SAI_xSR_FREQ ((uint32_t)0x00000008) /*!<FIFO request */
6308#define SAI_xSR_CNRDY ((uint32_t)0x00000010) /*!<Codec not ready */
6309#define SAI_xSR_AFSDET ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection */
6310#define SAI_xSR_LFSDET ((uint32_t)0x00000040) /*!<Late frame synchronization detection */
6311
6312#define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
6313#define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
6314#define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
6315#define SAI_xSR_FLVL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
6316
6317/****************** Bit definition for SAI_xCLRFR register ******************/
6318#define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */
6319#define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /*!<Clear Mute detection */
6320#define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /*!<Clear Wrong Clock Configuration */
6321#define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /*!<Clear FIFO request */
6322#define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /*!<Clear Codec not ready */
6323#define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /*!<Clear Anticipated frame synchronization detection */
6324#define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /*!<Clear Late frame synchronization detection */
6325
6326/****************** Bit definition for SAI_xDR register *********************/
6327#define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF)
6328
6329/******************************************************************************/
6330/* */
6331/* SPDIF-RX Interface */
6332/* */
6333/******************************************************************************/
6334/******************** Bit definition for SPDIF_CR register *******************/
6335#define SPDIFRX_CR_SPDIFEN ((uint32_t)0x00000003) /*!<Peripheral Block Enable */
6336#define SPDIFRX_CR_RXDMAEN ((uint32_t)0x00000004) /*!<Receiver DMA Enable for data flow */
6337#define SPDIFRX_CR_RXSTEO ((uint32_t)0x00000008) /*!<Stereo Mode */
6338#define SPDIFRX_CR_DRFMT ((uint32_t)0x00000030) /*!<RX Data format */
6339#define SPDIFRX_CR_PMSK ((uint32_t)0x00000040) /*!<Mask Parity error bit */
6340#define SPDIFRX_CR_VMSK ((uint32_t)0x00000080) /*!<Mask of Validity bit */
6341#define SPDIFRX_CR_CUMSK ((uint32_t)0x00000100) /*!<Mask of channel status and user bits */
6342#define SPDIFRX_CR_PTMSK ((uint32_t)0x00000200) /*!<Mask of Preamble Type bits */
6343#define SPDIFRX_CR_CBDMAEN ((uint32_t)0x00000400) /*!<Control Buffer DMA ENable for control flow */
6344#define SPDIFRX_CR_CHSEL ((uint32_t)0x00000800) /*!<Channel Selection */
6345#define SPDIFRX_CR_NBTR ((uint32_t)0x00003000) /*!<Maximum allowed re-tries during synchronization phase */
6346#define SPDIFRX_CR_WFA ((uint32_t)0x00004000) /*!<Wait For Activity */
6347#define SPDIFRX_CR_INSEL ((uint32_t)0x00070000) /*!<SPDIF input selection */
6348
6349/******************* Bit definition for SPDIFRX_IMR register *******************/
6350#define SPDIFRX_IMR_RXNEIE ((uint32_t)0x00000001) /*!<RXNE interrupt enable */
6351#define SPDIFRX_IMR_CSRNEIE ((uint32_t)0x00000002) /*!<Control Buffer Ready Interrupt Enable */
6352#define SPDIFRX_IMR_PERRIE ((uint32_t)0x00000004) /*!<Parity error interrupt enable */
6353#define SPDIFRX_IMR_OVRIE ((uint32_t)0x00000008) /*!<Overrun error Interrupt Enable */
6354#define SPDIFRX_IMR_SBLKIE ((uint32_t)0x00000010) /*!<Synchronization Block Detected Interrupt Enable */
6355#define SPDIFRX_IMR_SYNCDIE ((uint32_t)0x00000020) /*!<Synchronization Done */
6356#define SPDIFRX_IMR_IFEIE ((uint32_t)0x00000040) /*!<Serial Interface Error Interrupt Enable */
6357
6358/******************* Bit definition for SPDIFRX_SR register *******************/
6359#define SPDIFRX_SR_RXNE ((uint32_t)0x00000001) /*!<Read data register not empty */
6360#define SPDIFRX_SR_CSRNE ((uint32_t)0x00000002) /*!<The Control Buffer register is not empty */
6361#define SPDIFRX_SR_PERR ((uint32_t)0x00000004) /*!<Parity error */
6362#define SPDIFRX_SR_OVR ((uint32_t)0x00000008) /*!<Overrun error */
6363#define SPDIFRX_SR_SBD ((uint32_t)0x00000010) /*!<Synchronization Block Detected */
6364#define SPDIFRX_SR_SYNCD ((uint32_t)0x00000020) /*!<Synchronization Done */
6365#define SPDIFRX_SR_FERR ((uint32_t)0x00000040) /*!<Framing error */
6366#define SPDIFRX_SR_SERR ((uint32_t)0x00000080) /*!<Synchronization error */
6367#define SPDIFRX_SR_TERR ((uint32_t)0x00000100) /*!<Time-out error */
6368#define SPDIFRX_SR_WIDTH5 ((uint32_t)0x7FFF0000) /*!<Duration of 5 symbols counted with spdif_clk */
6369
6370/******************* Bit definition for SPDIFRX_IFCR register *******************/
6371#define SPDIFRX_IFCR_PERRCF ((uint32_t)0x00000004) /*!<Clears the Parity error flag */
6372#define SPDIFRX_IFCR_OVRCF ((uint32_t)0x00000008) /*!<Clears the Overrun error flag */
6373#define SPDIFRX_IFCR_SBDCF ((uint32_t)0x00000010) /*!<Clears the Synchronization Block Detected flag */
6374#define SPDIFRX_IFCR_SYNCDCF ((uint32_t)0x00000020) /*!<Clears the Synchronization Done flag */
6375
6376/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
6377#define SPDIFRX_DR0_DR ((uint32_t)0x00FFFFFF) /*!<Data value */
6378#define SPDIFRX_DR0_PE ((uint32_t)0x01000000) /*!<Parity Error bit */
6379#define SPDIFRX_DR0_V ((uint32_t)0x02000000) /*!<Validity bit */
6380#define SPDIFRX_DR0_U ((uint32_t)0x04000000) /*!<User bit */
6381#define SPDIFRX_DR0_C ((uint32_t)0x08000000) /*!<Channel Status bit */
6382#define SPDIFRX_DR0_PT ((uint32_t)0x30000000) /*!<Preamble Type */
6383
6384/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
6385#define SPDIFRX_DR1_DR ((uint32_t)0xFFFFFF00) /*!<Data value */
6386#define SPDIFRX_DR1_PT ((uint32_t)0x00000030) /*!<Preamble Type */
6387#define SPDIFRX_DR1_C ((uint32_t)0x00000008) /*!<Channel Status bit */
6388#define SPDIFRX_DR1_U ((uint32_t)0x00000004) /*!<User bit */
6389#define SPDIFRX_DR1_V ((uint32_t)0x00000002) /*!<Validity bit */
6390#define SPDIFRX_DR1_PE ((uint32_t)0x00000001) /*!<Parity Error bit */
6391
6392/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
6393#define SPDIFRX_DR1_DRNL1 ((uint32_t)0xFFFF0000) /*!<Data value Channel B */
6394#define SPDIFRX_DR1_DRNL2 ((uint32_t)0x0000FFFF) /*!<Data value Channel A */
6395
6396/******************* Bit definition for SPDIFRX_CSR register *******************/
6397#define SPDIFRX_CSR_USR ((uint32_t)0x0000FFFF) /*!<User data information */
6398#define SPDIFRX_CSR_CS ((uint32_t)0x00FF0000) /*!<Channel A status information */
6399#define SPDIFRX_CSR_SOB ((uint32_t)0x01000000) /*!<Start Of Block */
6400
6401/******************* Bit definition for SPDIFRX_DIR register *******************/
6402#define SPDIFRX_DIR_THI ((uint32_t)0x000013FF) /*!<Threshold LOW */
6403#define SPDIFRX_DIR_TLO ((uint32_t)0x1FFF0000) /*!<Threshold HIGH */
6404
6405
6406/******************************************************************************/
6407/* */
6408/* SD host Interface */
6409/* */
6410/******************************************************************************/
6411/****************** Bit definition for SDMMC_POWER register ******************/
6412#define SDMMC_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
6413#define SDMMC_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
6414#define SDMMC_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
6415
6416/****************** Bit definition for SDMMC_CLKCR register ******************/
6417#define SDMMC_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
6418#define SDMMC_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
6419#define SDMMC_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
6420#define SDMMC_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
6421
6422#define SDMMC_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
6423#define SDMMC_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
6424#define SDMMC_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
6425
6426#define SDMMC_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDMMC_CK dephasing selection bit */
6427#define SDMMC_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
6428
6429/******************* Bit definition for SDMMC_ARG register *******************/
6430#define SDMMC_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
6431
6432/******************* Bit definition for SDMMC_CMD register *******************/
6433#define SDMMC_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
6434
6435#define SDMMC_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
6436#define SDMMC_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
6437#define SDMMC_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
6438
6439#define SDMMC_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
6440#define SDMMC_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
6441#define SDMMC_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
6442#define SDMMC_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
6443
6444/***************** Bit definition for SDMMC_RESPCMD register *****************/
6445#define SDMMC_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
6446
6447/****************** Bit definition for SDMMC_RESP0 register ******************/
6448#define SDMMC_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
6449
6450/****************** Bit definition for SDMMC_RESP1 register ******************/
6451#define SDMMC_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
6452
6453/****************** Bit definition for SDMMC_RESP2 register ******************/
6454#define SDMMC_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
6455
6456/****************** Bit definition for SDMMC_RESP3 register ******************/
6457#define SDMMC_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
6458
6459/****************** Bit definition for SDMMC_RESP4 register ******************/
6460#define SDMMC_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
6461
6462/****************** Bit definition for SDMMC_DTIMER register *****************/
6463#define SDMMC_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
6464
6465/****************** Bit definition for SDMMC_DLEN register *******************/
6466#define SDMMC_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
6467
6468/****************** Bit definition for SDMMC_DCTRL register ******************/
6469#define SDMMC_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
6470#define SDMMC_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
6471#define SDMMC_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
6472#define SDMMC_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
6473
6474#define SDMMC_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
6475#define SDMMC_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
6476#define SDMMC_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
6477#define SDMMC_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
6478#define SDMMC_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
6479
6480#define SDMMC_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
6481#define SDMMC_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
6482#define SDMMC_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
6483#define SDMMC_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
6484
6485/****************** Bit definition for SDMMC_DCOUNT register *****************/
6486#define SDMMC_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
6487
6488/****************** Bit definition for SDMMC_STA register ********************/
6489#define SDMMC_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
6490#define SDMMC_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
6491#define SDMMC_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
6492#define SDMMC_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
6493#define SDMMC_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
6494#define SDMMC_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
6495#define SDMMC_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
6496#define SDMMC_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
6497#define SDMMC_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
6498#define SDMMC_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
6499#define SDMMC_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
6500#define SDMMC_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
6501#define SDMMC_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
6502#define SDMMC_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
6503#define SDMMC_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
6504#define SDMMC_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
6505#define SDMMC_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
6506#define SDMMC_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
6507#define SDMMC_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
6508#define SDMMC_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
6509#define SDMMC_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
6510#define SDMMC_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDMMC interrupt received */
6511
6512/******************* Bit definition for SDMMC_ICR register *******************/
6513#define SDMMC_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
6514#define SDMMC_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
6515#define SDMMC_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
6516#define SDMMC_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
6517#define SDMMC_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
6518#define SDMMC_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
6519#define SDMMC_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
6520#define SDMMC_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
6521#define SDMMC_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
6522#define SDMMC_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
6523#define SDMMC_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDMMCIT flag clear bit */
6524
6525/****************** Bit definition for SDMMC_MASK register *******************/
6526#define SDMMC_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
6527#define SDMMC_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
6528#define SDMMC_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
6529#define SDMMC_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
6530#define SDMMC_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
6531#define SDMMC_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
6532#define SDMMC_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
6533#define SDMMC_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
6534#define SDMMC_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
6535#define SDMMC_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
6536#define SDMMC_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
6537#define SDMMC_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
6538#define SDMMC_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
6539#define SDMMC_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
6540#define SDMMC_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
6541#define SDMMC_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
6542#define SDMMC_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
6543#define SDMMC_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
6544#define SDMMC_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
6545#define SDMMC_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
6546#define SDMMC_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
6547#define SDMMC_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDMMC Mode Interrupt Received interrupt Enable */
6548
6549/***************** Bit definition for SDMMC_FIFOCNT register *****************/
6550#define SDMMC_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
6551
6552/****************** Bit definition for SDMMC_FIFO register *******************/
6553#define SDMMC_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
6554
6555/******************************************************************************/
6556/* */
6557/* Serial Peripheral Interface (SPI) */
6558/* */
6559/******************************************************************************/
6560/******************* Bit definition for SPI_CR1 register ********************/
6561#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
6562#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
6563#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
6564#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
6565#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
6566#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
6567#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
6568#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
6569#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
6570#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
6571#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
6572#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
6573#define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
6574#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
6575#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
6576#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
6577#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
6578
6579/******************* Bit definition for SPI_CR2 register ********************/
6580#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
6581#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
6582#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
6583#define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
6584#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
6585#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
6586#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
6587#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
6588#define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
6589#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
6590#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
6591#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
6592#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
6593#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
6594#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
6595#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
6596
6597/******************** Bit definition for SPI_SR register ********************/
6598#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
6599#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
6600#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
6601#define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
6602#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
6603#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
6604#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
6605#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
6606#define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
6607#define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
6608#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
6609#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
6610#define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
6611#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
6612#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
6613
6614/******************** Bit definition for SPI_DR register ********************/
6615#define SPI_DR_DR ((uint32_t)0xFFFF) /*!< Data Register */
6616
6617/******************* Bit definition for SPI_CRCPR register ******************/
6618#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFF) /*!< CRC polynomial register */
6619
6620/****************** Bit definition for SPI_RXCRCR register ******************/
6621#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFF) /*!< Rx CRC Register */
6622
6623/****************** Bit definition for SPI_TXCRCR register ******************/
6624#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFF) /*!< Tx CRC Register */
6625
6626/****************** Bit definition for SPI_I2SCFGR register *****************/
6627#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
6628#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
6629#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
6630#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
6631#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
6632#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
6633#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
6634#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
6635#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
6636#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
6637#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
6638#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
6639#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
6640#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
6641#define SPI_I2SCFGR_ASTRTEN ((uint32_t)0x00001000) /*!<Asynchronous start enable */
6642
6643/****************** Bit definition for SPI_I2SPR register *******************/
6644#define SPI_I2SPR_I2SDIV ((uint32_t)0x00FF) /*!<I2S Linear prescaler */
6645#define SPI_I2SPR_ODD ((uint32_t)0x0100) /*!<Odd factor for the prescaler */
6646#define SPI_I2SPR_MCKOE ((uint32_t)0x0200) /*!<Master Clock Output Enable */
6647
6648
6649/******************************************************************************/
6650/* */
6651/* SYSCFG */
6652/* */
6653/******************************************************************************/
6654/****************** Bit definition for SYSCFG_MEMRMP register ***************/
6655#define SYSCFG_MEMRMP_MEM_BOOT ((uint32_t)0x00000001) /*!< Boot information after Reset */
6656
6657#define SYSCFG_MEMRMP_SWP_FMC ((uint32_t)0x00000C00) /*!< FMC Memory Mapping swapping */
6658#define SYSCFG_MEMRMP_SWP_FMC_0 ((uint32_t)0x00000400)
6659#define SYSCFG_MEMRMP_SWP_FMC_1 ((uint32_t)0x00000800)
6660
6661/****************** Bit definition for SYSCFG_PMC register ******************/
6662#define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */
6663#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
6664#define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */
6665#define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */
6666
6667#define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
6668
6669/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
6670#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
6671#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
6672#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
6673#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
6674/**
6675 * @brief EXTI0 configuration
6676 */
6677#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
6678#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
6679#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
6680#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
6681#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
6682#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
6683#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
6684#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
6685#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
6686#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x0009) /*!<PJ[0] pin */
6687#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x000A) /*!<PK[0] pin */
6688
6689/**
6690 * @brief EXTI1 configuration
6691 */
6692#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
6693#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
6694#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
6695#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
6696#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
6697#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
6698#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
6699#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
6700#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
6701#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x0090) /*!<PJ[1] pin */
6702#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x00A0) /*!<PK[1] pin */
6703
6704/**
6705 * @brief EXTI2 configuration
6706 */
6707#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
6708#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
6709#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
6710#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
6711#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
6712#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
6713#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
6714#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
6715#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
6716#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x0900) /*!<PJ[2] pin */
6717#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x0A00) /*!<PK[2] pin */
6718
6719/**
6720 * @brief EXTI3 configuration
6721 */
6722#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
6723#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
6724#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
6725#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
6726#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
6727#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
6728#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
6729#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
6730#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
6731#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x9000) /*!<PJ[3] pin */
6732#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0xA000) /*!<PK[3] pin */
6733
6734/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
6735#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
6736#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
6737#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
6738#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
6739/**
6740 * @brief EXTI4 configuration
6741 */
6742#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
6743#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
6744#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
6745#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
6746#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
6747#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
6748#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
6749#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
6750#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
6751#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x0009) /*!<PJ[4] pin */
6752#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x000A) /*!<PK[4] pin */
6753
6754/**
6755 * @brief EXTI5 configuration
6756 */
6757#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
6758#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
6759#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
6760#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
6761#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
6762#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
6763#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
6764#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
6765#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
6766#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x0090) /*!<PJ[5] pin */
6767#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x00A0) /*!<PK[5] pin */
6768
6769/**
6770 * @brief EXTI6 configuration
6771 */
6772#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
6773#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
6774#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
6775#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
6776#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
6777#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
6778#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
6779#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
6780#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
6781#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x0900) /*!<PJ[6] pin */
6782#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x0A00) /*!<PK[6] pin */
6783
6784/**
6785 * @brief EXTI7 configuration
6786 */
6787#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
6788#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
6789#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
6790#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
6791#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
6792#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
6793#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
6794#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
6795#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
6796#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x9000) /*!<PJ[7] pin */
6797#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0xA000) /*!<PK[7] pin */
6798
6799/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
6800#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
6801#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
6802#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
6803#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
6804
6805/**
6806 * @brief EXTI8 configuration
6807 */
6808#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
6809#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
6810#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
6811#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
6812#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
6813#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
6814#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
6815#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
6816#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
6817#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x0009) /*!<PJ[8] pin */
6818
6819/**
6820 * @brief EXTI9 configuration
6821 */
6822#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
6823#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
6824#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
6825#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
6826#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
6827#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
6828#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
6829#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
6830#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
6831#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x0090) /*!<PJ[9] pin */
6832
6833/**
6834 * @brief EXTI10 configuration
6835 */
6836#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
6837#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
6838#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
6839#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
6840#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
6841#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
6842#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
6843#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
6844#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
6845#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x0900) /*!<PJ[10] pin */
6846
6847/**
6848 * @brief EXTI11 configuration
6849 */
6850#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
6851#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
6852#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
6853#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
6854#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
6855#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
6856#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
6857#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
6858#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
6859#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x9000) /*!<PJ[11] pin */
6860
6861
6862/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
6863#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
6864#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
6865#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
6866#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
6867/**
6868 * @brief EXTI12 configuration
6869 */
6870#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
6871#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
6872#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
6873#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
6874#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
6875#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
6876#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
6877#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
6878#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x0008) /*!<PI[12] pin */
6879#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x0009) /*!<PJ[12] pin */
6880
6881/**
6882 * @brief EXTI13 configuration
6883 */
6884#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
6885#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
6886#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
6887#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
6888#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
6889#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
6890#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
6891#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
6892#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x0008) /*!<PI[13] pin */
6893#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x0009) /*!<PJ[13] pin */
6894
6895/**
6896 * @brief EXTI14 configuration
6897 */
6898#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
6899#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
6900#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
6901#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
6902#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
6903#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
6904#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
6905#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
6906#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x0800) /*!<PI[14] pin */
6907#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x0900) /*!<PJ[14] pin */
6908
6909/**
6910 * @brief EXTI15 configuration
6911 */
6912#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
6913#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
6914#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
6915#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
6916#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
6917#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
6918#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
6919#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
6920#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x8000) /*!<PI[15] pin */
6921#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x9000) /*!<PJ[15] pin */
6922
6923/****************** Bit definition for SYSCFG_CMPCR register ****************/
6924#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell power-down */
6925#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell ready flag*/
6926
6927/******************************************************************************/
6928/* */
6929/* TIM */
6930/* */
6931/******************************************************************************/
6932/******************* Bit definition for TIM_CR1 register ********************/
6933#define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
6934#define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
6935#define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
6936#define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
6937#define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
6938
6939#define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
6940#define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
6941#define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
6942
6943#define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
6944
6945#define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
6946#define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
6947#define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
6948#define TIM_CR1_UIFREMAP ((uint32_t)0x0800) /*!<UIF status bit */
6949
6950/******************* Bit definition for TIM_CR2 register ********************/
6951#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
6952#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
6953#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
6954
6955#define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */
6956#define TIM_CR2_OIS6 ((uint32_t)0x00040000) /*!<Output Idle state 4 (OC4 output) */
6957
6958#define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
6959#define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
6960#define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
6961#define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
6962
6963#define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */
6964#define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
6965#define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
6966#define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
6967#define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */
6968
6969#define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
6970#define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
6971#define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
6972#define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
6973#define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
6974#define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
6975#define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
6976#define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
6977
6978/******************* Bit definition for TIM_SMCR register *******************/
6979#define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */
6980#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
6981#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
6982#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
6983#define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */
6984#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
6985
6986#define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
6987#define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
6988#define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
6989#define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
6990
6991#define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
6992
6993#define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
6994#define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
6995#define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
6996#define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
6997#define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
6998
6999#define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
7000#define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
7001#define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
7002
7003
7004#define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
7005#define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
7006
7007/******************* Bit definition for TIM_DIER register *******************/
7008#define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
7009#define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
7010#define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
7011#define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
7012#define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
7013#define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
7014#define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
7015#define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
7016#define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
7017#define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
7018#define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
7019#define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
7020#define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
7021#define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
7022#define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
7023
7024/******************** Bit definition for TIM_SR register ********************/
7025#define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
7026#define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
7027#define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
7028#define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
7029#define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
7030#define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
7031#define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
7032#define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
7033#define TIM_SR_B2IF ((uint32_t)0x0100) /*!<Break2 interrupt Flag */
7034#define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
7035#define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
7036#define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
7037#define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
7038
7039/******************* Bit definition for TIM_EGR register ********************/
7040#define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
7041#define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
7042#define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
7043#define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
7044#define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
7045#define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
7046#define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
7047#define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
7048#define TIM_EGR_B2G ((uint32_t)0x00000100) /*!<Break2 Generation */
7049
7050/****************** Bit definition for TIM_CCMR1 register *******************/
7051#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
7052#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
7053#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
7054
7055#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
7056#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
7057
7058#define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
7059#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
7060#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
7061#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
7062#define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
7063
7064#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
7065
7066#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
7067#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
7068#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
7069
7070#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
7071#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
7072
7073#define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
7074#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
7075#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
7076#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
7077#define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
7078
7079#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
7080
7081/*----------------------------------------------------------------------------*/
7082
7083#define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
7084#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
7085#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
7086
7087#define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
7088#define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
7089#define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
7090#define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
7091#define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
7092
7093#define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
7094#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
7095#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
7096
7097#define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
7098#define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
7099#define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
7100#define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
7101#define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
7102
7103/****************** Bit definition for TIM_CCMR2 register *******************/
7104#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
7105#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
7106#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
7107
7108#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
7109#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
7110
7111#define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
7112#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
7113#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
7114#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
7115#define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
7116
7117
7118
7119#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
7120
7121#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
7122#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
7123#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
7124
7125#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
7126#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
7127
7128#define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
7129#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
7130#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
7131#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
7132#define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
7133
7134#define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
7135
7136/*----------------------------------------------------------------------------*/
7137
7138#define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
7139#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
7140#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
7141
7142#define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
7143#define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
7144#define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
7145#define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
7146#define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
7147
7148#define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
7149#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
7150#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
7151
7152#define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
7153#define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
7154#define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
7155#define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
7156#define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
7157
7158/******************* Bit definition for TIM_CCER register *******************/
7159#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
7160#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
7161#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
7162#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
7163#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
7164#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
7165#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
7166#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
7167#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
7168#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
7169#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
7170#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
7171#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
7172#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
7173#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
7174#define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */
7175#define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */
7176#define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */
7177#define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */
7178
7179
7180/******************* Bit definition for TIM_CNT register ********************/
7181#define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
7182
7183/******************* Bit definition for TIM_PSC register ********************/
7184#define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
7185
7186/******************* Bit definition for TIM_ARR register ********************/
7187#define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
7188
7189/******************* Bit definition for TIM_RCR register ********************/
7190#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
7191
7192/******************* Bit definition for TIM_CCR1 register *******************/
7193#define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
7194
7195/******************* Bit definition for TIM_CCR2 register *******************/
7196#define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
7197
7198/******************* Bit definition for TIM_CCR3 register *******************/
7199#define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
7200
7201/******************* Bit definition for TIM_CCR4 register *******************/
7202#define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
7203
7204/******************* Bit definition for TIM_BDTR register *******************/
7205#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
7206#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
7207#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
7208#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
7209#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
7210#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
7211#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
7212#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
7213#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
7214
7215#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
7216#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
7217#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
7218
7219#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
7220#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
7221#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
7222#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
7223#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
7224#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
7225#define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */
7226#define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */
7227#define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */
7228#define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */
7229
7230/******************* Bit definition for TIM_DCR register ********************/
7231#define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
7232#define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
7233#define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
7234#define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
7235#define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
7236#define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
7237
7238#define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
7239#define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
7240#define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
7241#define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
7242#define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
7243#define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
7244
7245/******************* Bit definition for TIM_DMAR register *******************/
7246#define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
7247
7248/******************* Bit definition for TIM_OR register *********************/
7249#define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
7250#define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
7251#define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
7252#define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
7253#define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
7254#define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
7255
7256/****************** Bit definition for TIM_CCMR3 register *******************/
7257#define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */
7258#define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */
7259
7260#define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
7261#define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
7262#define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
7263#define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
7264#define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
7265
7266#define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */
7267
7268#define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
7269#define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
7270
7271#define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
7272#define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
7273#define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
7274#define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
7275#define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
7276
7277#define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
7278
7279/******************* Bit definition for TIM_CCR5 register *******************/
7280#define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */
7281#define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */
7282#define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */
7283#define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */
7284
7285/******************* Bit definition for TIM_CCR6 register *******************/
7286#define TIM_CCR6_CCR6 ((uint16_t)0xFFFF) /*!<Capture/Compare 6 Value */
7287
7288/******************************************************************************/
7289/* */
7290/* Low Power Timer (LPTIM) */
7291/* */
7292/******************************************************************************/
7293/****************** Bit definition for LPTIM_ISR register *******************/
7294#define LPTIM_ISR_CMPM ((uint32_t)0x00000001) /*!< Compare match */
7295#define LPTIM_ISR_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */
7296#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */
7297#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) /*!< Compare register update OK */
7298#define LPTIM_ISR_ARROK ((uint32_t)0x00000010) /*!< Autoreload register update OK */
7299#define LPTIM_ISR_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */
7300#define LPTIM_ISR_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */
7301
7302/****************** Bit definition for LPTIM_ICR register *******************/
7303#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */
7304#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */
7305#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */
7306#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */
7307#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */
7308#define LPTIM_ICR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */
7309#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */
7310
7311/****************** Bit definition for LPTIM_IER register ********************/
7312#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */
7313#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */
7314#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */
7315#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */
7316#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */
7317#define LPTIM_IER_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */
7318#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */
7319
7320/****************** Bit definition for LPTIM_CFGR register *******************/
7321#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) /*!< Clock selector */
7322
7323#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) /*!< CKPOL[1:0] bits (Clock polarity) */
7324#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002) /*!< Bit 0 */
7325#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004) /*!< Bit 1 */
7326
7327#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
7328#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008) /*!< Bit 0 */
7329#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010) /*!< Bit 1 */
7330
7331#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
7332#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040) /*!< Bit 0 */
7333#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080) /*!< Bit 1 */
7334
7335#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) /*!< PRESC[2:0] bits (Clock prescaler) */
7336#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200) /*!< Bit 0 */
7337#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400) /*!< Bit 1 */
7338#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800) /*!< Bit 2 */
7339
7340#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
7341#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000) /*!< Bit 0 */
7342#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000) /*!< Bit 1 */
7343#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000) /*!< Bit 2 */
7344
7345#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
7346#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000) /*!< Bit 0 */
7347#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000) /*!< Bit 1 */
7348
7349#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) /*!< Timout enable */
7350#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */
7351#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */
7352#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) /*!< Reg update mode */
7353#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000) /*!< Counter mode enable */
7354#define LPTIM_CFGR_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */
7355
7356/****************** Bit definition for LPTIM_CR register ********************/
7357#define LPTIM_CR_ENABLE ((uint32_t)0x00000001) /*!< LPTIMer enable */
7358#define LPTIM_CR_SNGSTRT ((uint32_t)0x00080002) /*!< Timer start in single mode */
7359#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) /*!< Timer start in continuous mode */
7360
7361/****************** Bit definition for LPTIM_CMP register *******************/
7362#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFF) /*!< Compare register */
7363
7364/****************** Bit definition for LPTIM_ARR register *******************/
7365#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!< Auto reload register */
7366
7367/****************** Bit definition for LPTIM_CNT register *******************/
7368#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!< Counter register */
7369/******************************************************************************/
7370/* */
7371/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
7372/* */
7373/******************************************************************************/
7374/****************** Bit definition for USART_CR1 register *******************/
7375#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
7376#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
7377#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
7378#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
7379#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
7380#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
7381#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
7382#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
7383#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
7384#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
7385#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
7386#define USART_CR1_M ((uint32_t)0x10001000) /*!< Word length */
7387#define USART_CR1_M_0 ((uint32_t)0x00001000) /*!< Word length - Bit 0 */
7388#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
7389#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
7390#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
7391#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
7392#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
7393#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
7394#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
7395#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
7396#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
7397#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
7398#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
7399#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
7400#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
7401#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
7402#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
7403#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
7404#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
7405#define USART_CR1_M_1 ((uint32_t)0x10000000) /*!< Word length - Bit 1 */
7406
7407/****************** Bit definition for USART_CR2 register *******************/
7408#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
7409#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
7410#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
7411#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
7412#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
7413#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
7414#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
7415#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
7416#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
7417#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
7418#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
7419#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
7420#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
7421#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
7422#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
7423#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
7424#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable */
7425#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
7426#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
7427#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
7428#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
7429#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
7430
7431/****************** Bit definition for USART_CR3 register *******************/
7432#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
7433#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
7434#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
7435#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
7436#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
7437#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
7438#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
7439#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
7440#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
7441#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
7442#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
7443#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
7444#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
7445#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
7446#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
7447#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
7448#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
7449#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
7450#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
7451#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
7452
7453/****************** Bit definition for USART_BRR register *******************/
7454#define USART_BRR_DIV_FRACTION ((uint32_t)0x000F) /*!< Fraction of USARTDIV */
7455#define USART_BRR_DIV_MANTISSA ((uint32_t)0xFFF0) /*!< Mantissa of USARTDIV */
7456
7457/****************** Bit definition for USART_GTPR register ******************/
7458#define USART_GTPR_PSC ((uint32_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
7459#define USART_GTPR_GT ((uint32_t)0xFF00) /*!< GT[7:0] bits (Guard time value) */
7460
7461
7462/******************* Bit definition for USART_RTOR register *****************/
7463#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
7464#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
7465
7466/******************* Bit definition for USART_RQR register ******************/
7467#define USART_RQR_ABRRQ ((uint32_t)0x0001) /*!< Auto-Baud Rate Request */
7468#define USART_RQR_SBKRQ ((uint32_t)0x0002) /*!< Send Break Request */
7469#define USART_RQR_MMRQ ((uint32_t)0x0004) /*!< Mute Mode Request */
7470#define USART_RQR_RXFRQ ((uint32_t)0x0008) /*!< Receive Data flush Request */
7471#define USART_RQR_TXFRQ ((uint32_t)0x0010) /*!< Transmit data flush Request */
7472
7473/******************* Bit definition for USART_ISR register ******************/
7474#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
7475#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
7476#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
7477#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
7478#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
7479#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
7480#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
7481#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
7482#define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
7483#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
7484#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
7485#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
7486#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
7487#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
7488#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
7489#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
7490#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
7491#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
7492#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
7493#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
7494#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
7495#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
7496
7497/******************* Bit definition for USART_ICR register ******************/
7498#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
7499#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
7500#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
7501#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
7502#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
7503#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
7504#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
7505#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
7506#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
7507#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
7508#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
7509#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
7510
7511/******************* Bit definition for USART_RDR register ******************/
7512#define USART_RDR_RDR ((uint32_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
7513
7514/******************* Bit definition for USART_TDR register ******************/
7515#define USART_TDR_TDR ((uint32_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
7516
7517/******************************************************************************/
7518/* */
7519/* Window WATCHDOG */
7520/* */
7521/******************************************************************************/
7522/******************* Bit definition for WWDG_CR register ********************/
7523#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
7524#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
7525#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
7526#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
7527#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
7528#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
7529#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
7530#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
7531
7532#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
7533
7534/******************* Bit definition for WWDG_CFR register *******************/
7535#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
7536#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
7537#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
7538#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
7539#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
7540#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
7541#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
7542#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
7543
7544#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
7545#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
7546#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
7547
7548#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
7549
7550/******************* Bit definition for WWDG_SR register ********************/
7551#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
7552
7553/******************************************************************************/
7554/* */
7555/* DBG */
7556/* */
7557/******************************************************************************/
7558/******************** Bit definition for DBGMCU_IDCODE register *************/
7559#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
7560#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
7561
7562/******************** Bit definition for DBGMCU_CR register *****************/
7563#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
7564#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
7565#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
7566#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
7567
7568#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
7569#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!<Bit 0 */
7570#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!<Bit 1 */
7571
7572/******************** Bit definition for DBGMCU_APB1_FZ register ************/
7573#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
7574#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
7575#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
7576#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
7577#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
7578#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
7579#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
7580#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
7581#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
7582#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
7583#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
7584#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
7585#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
7586#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
7587#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
7588#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
7589#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
7590
7591/******************** Bit definition for DBGMCU_APB2_FZ register ************/
7592#define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
7593#define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
7594#define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
7595#define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
7596#define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
7597
7598/******************************************************************************/
7599/* */
7600/* Ethernet MAC Registers bits definitions */
7601/* */
7602/******************************************************************************/
7603/* Bit definition for Ethernet MAC Control Register register */
7604#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
7605#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
7606#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
7607#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
7608#define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
7609#define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
7610#define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
7611#define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
7612#define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
7613#define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
7614#define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
7615#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
7616#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
7617#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
7618#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
7619#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
7620#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
7621#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
7622#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
7623#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
7624 a transmission attempt during retries after a collision: 0 =< r <2^k */
7625#define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
7626#define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
7627#define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
7628#define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
7629#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
7630#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
7631#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
7632
7633/* Bit definition for Ethernet MAC Frame Filter Register */
7634#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
7635#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
7636#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
7637#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
7638#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
7639#define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
7640#define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
7641#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
7642#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
7643#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
7644#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
7645#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
7646#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
7647#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
7648
7649/* Bit definition for Ethernet MAC Hash Table High Register */
7650#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
7651
7652/* Bit definition for Ethernet MAC Hash Table Low Register */
7653#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
7654
7655/* Bit definition for Ethernet MAC MII Address Register */
7656#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
7657#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
7658#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
7659#define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
7660#define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
7661#define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
7662#define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
7663#define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
7664#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
7665#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
7666
7667/* Bit definition for Ethernet MAC MII Data Register */
7668#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
7669
7670/* Bit definition for Ethernet MAC Flow Control Register */
7671#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
7672#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
7673#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
7674#define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
7675#define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
7676#define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
7677#define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
7678#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
7679#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
7680#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
7681#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
7682
7683/* Bit definition for Ethernet MAC VLAN Tag Register */
7684#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
7685#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
7686
7687/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
7688#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
7689/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
7690 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
7691/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
7692 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
7693 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
7694 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
7695 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
7696 RSVD - Filter1 Command - RSVD - Filter0 Command
7697 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
7698 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
7699 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
7700
7701/* Bit definition for Ethernet MAC PMT Control and Status Register */
7702#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
7703#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
7704#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
7705#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
7706#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
7707#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
7708#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
7709
7710/* Bit definition for Ethernet MAC Status Register */
7711#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
7712#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
7713#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
7714#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
7715#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
7716
7717/* Bit definition for Ethernet MAC Interrupt Mask Register */
7718#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
7719#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
7720
7721/* Bit definition for Ethernet MAC Address0 High Register */
7722#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
7723
7724/* Bit definition for Ethernet MAC Address0 Low Register */
7725#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
7726
7727/* Bit definition for Ethernet MAC Address1 High Register */
7728#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
7729#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
7730#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
7731#define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
7732#define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
7733#define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
7734#define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
7735#define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
7736#define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
7737#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
7738
7739/* Bit definition for Ethernet MAC Address1 Low Register */
7740#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
7741
7742/* Bit definition for Ethernet MAC Address2 High Register */
7743#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
7744#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
7745#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
7746#define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
7747#define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
7748#define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
7749#define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
7750#define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
7751#define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
7752#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
7753
7754/* Bit definition for Ethernet MAC Address2 Low Register */
7755#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
7756
7757/* Bit definition for Ethernet MAC Address3 High Register */
7758#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
7759#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
7760#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
7761#define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
7762#define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
7763#define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
7764#define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
7765#define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
7766#define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
7767#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
7768
7769/* Bit definition for Ethernet MAC Address3 Low Register */
7770#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
7771
7772/******************************************************************************/
7773/* Ethernet MMC Registers bits definition */
7774/******************************************************************************/
7775
7776/* Bit definition for Ethernet MMC Contol Register */
7777#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
7778#define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
7779#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
7780#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
7781#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
7782#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
7783
7784/* Bit definition for Ethernet MMC Receive Interrupt Register */
7785#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
7786#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
7787#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
7788
7789/* Bit definition for Ethernet MMC Transmit Interrupt Register */
7790#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
7791#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
7792#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
7793
7794/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
7795#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
7796#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
7797#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
7798
7799/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
7800#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
7801#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
7802#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
7803
7804/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
7805#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
7806
7807/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
7808#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
7809
7810/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
7811#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
7812
7813/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
7814#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
7815
7816/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
7817#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
7818
7819/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
7820#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
7821
7822/******************************************************************************/
7823/* Ethernet PTP Registers bits definition */
7824/******************************************************************************/
7825
7826/* Bit definition for Ethernet PTP Time Stamp Contol Register */
7827#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
7828#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
7829#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
7830#define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
7831#define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
7832#define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
7833#define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
7834#define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
7835#define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
7836
7837#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
7838#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
7839#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
7840#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
7841#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
7842#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
7843
7844/* Bit definition for Ethernet PTP Sub-Second Increment Register */
7845#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
7846
7847/* Bit definition for Ethernet PTP Time Stamp High Register */
7848#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
7849
7850/* Bit definition for Ethernet PTP Time Stamp Low Register */
7851#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
7852#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
7853
7854/* Bit definition for Ethernet PTP Time Stamp High Update Register */
7855#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
7856
7857/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
7858#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
7859#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
7860
7861/* Bit definition for Ethernet PTP Time Stamp Addend Register */
7862#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
7863
7864/* Bit definition for Ethernet PTP Target Time High Register */
7865#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
7866
7867/* Bit definition for Ethernet PTP Target Time Low Register */
7868#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
7869
7870/* Bit definition for Ethernet PTP Time Stamp Status Register */
7871#define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
7872#define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
7873
7874/******************************************************************************/
7875/* Ethernet DMA Registers bits definition */
7876/******************************************************************************/
7877
7878/* Bit definition for Ethernet DMA Bus Mode Register */
7879#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
7880#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
7881#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
7882#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
7883#define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
7884#define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
7885#define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
7886#define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
7887#define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
7888#define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
7889#define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
7890#define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
7891#define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
7892#define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
7893#define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
7894#define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
7895#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
7896#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
7897#define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
7898#define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
7899#define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
7900#define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
7901#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
7902#define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
7903#define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
7904#define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
7905#define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
7906#define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
7907#define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
7908#define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
7909#define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
7910#define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
7911#define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
7912#define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
7913#define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
7914#define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
7915#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
7916#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
7917#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
7918
7919/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
7920#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
7921
7922/* Bit definition for Ethernet DMA Receive Poll Demand Register */
7923#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
7924
7925/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
7926#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
7927
7928/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
7929#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
7930
7931/* Bit definition for Ethernet DMA Status Register */
7932#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
7933#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
7934#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
7935#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
7936/* combination with EBS[2:0] for GetFlagStatus function */
7937#define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
7938#define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
7939#define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
7940#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
7941#define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
7942#define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
7943#define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
7944#define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
7945#define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
7946#define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
7947#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
7948#define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
7949#define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
7950#define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
7951#define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
7952#define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
7953#define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
7954#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
7955#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
7956#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
7957#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
7958#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
7959#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
7960#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
7961#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
7962#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
7963#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
7964#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
7965#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
7966#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
7967#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
7968#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
7969
7970/* Bit definition for Ethernet DMA Operation Mode Register */
7971#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
7972#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
7973#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
7974#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
7975#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
7976#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
7977#define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
7978#define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
7979#define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
7980#define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
7981#define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
7982#define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
7983#define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
7984#define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
7985#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
7986#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
7987#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
7988#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
7989#define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
7990#define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
7991#define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
7992#define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
7993#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
7994#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
7995
7996/* Bit definition for Ethernet DMA Interrupt Enable Register */
7997#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
7998#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
7999#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
8000#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
8001#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
8002#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
8003#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
8004#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
8005#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
8006#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
8007#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
8008#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
8009#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
8010#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
8011#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
8012
8013/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
8014#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
8015#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
8016#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
8017#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
8018
8019/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
8020#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
8021
8022/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
8023#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
8024
8025/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
8026#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
8027
8028/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
8029#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
8030
8031/******************************************************************************/
8032/* */
8033/* USB_OTG */
8034/* */
8035/******************************************************************************/
8036/******************** Bit definition for USB_OTG_GOTGCTL register ********************/
8037#define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
8038#define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
8039#define USB_OTG_GOTGCTL_VBVALOEN ((uint32_t)0x00000004) /*!< VBUS valid override enable */
8040#define USB_OTG_GOTGCTL_VBVALOVAL ((uint32_t)0x00000008) /*!< VBUS valid override value */
8041#define USB_OTG_GOTGCTL_AVALOEN ((uint32_t)0x00000010) /*!< A-peripheral session valid override enable */
8042#define USB_OTG_GOTGCTL_AVALOVAL ((uint32_t)0x00000020) /*!< A-peripheral session valid override value */
8043#define USB_OTG_GOTGCTL_BVALOEN ((uint32_t)0x00000040) /*!< B-peripheral session valid override enable */
8044#define USB_OTG_GOTGCTL_BVALOVAL ((uint32_t)0x00000080) /*!< B-peripheral session valid override value */
8045#define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host set HNP enable */
8046#define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
8047#define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
8048#define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
8049#define USB_OTG_GOTGCTL_EHEN ((uint32_t)0x00001000) /*!< Embedded host enable */
8050#define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
8051#define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
8052#define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
8053#define USB_OTG_GOTGCTL_BSESVLD ((uint32_t)0x00080000) /*!< B-session valid */
8054#define USB_OTG_GOTGCTL_OTGVER ((uint32_t)0x00100000) /*!< OTG version */
8055
8056/******************** Bit definition for USB_OTG_HCFG register ********************/
8057#define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
8058#define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
8059#define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
8060#define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
8061
8062/******************** Bit definition for USB_OTG_DCFG register ********************/
8063#define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
8064#define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
8065#define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
8066#define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
8067
8068#define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
8069#define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
8070#define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
8071#define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
8072#define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
8073#define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
8074#define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
8075#define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
8076
8077#define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
8078#define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
8079#define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
8080
8081#define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
8082#define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
8083#define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
8084
8085/******************** Bit definition for USB_OTG_PCGCR register ********************/
8086#define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
8087#define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
8088#define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
8089
8090/******************** Bit definition for USB_OTG_GOTGINT register ********************/
8091#define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
8092#define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
8093#define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
8094#define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
8095#define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
8096#define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
8097#define USB_OTG_GOTGINT_IDCHNG ((uint32_t)0x00100000) /*!< Change in ID pin input value */
8098
8099/******************** Bit definition for USB_OTG_DCTL register ********************/
8100#define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
8101#define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
8102#define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
8103#define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
8104
8105#define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
8106#define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
8107#define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
8108#define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
8109#define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
8110#define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
8111#define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
8112#define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
8113#define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
8114
8115/******************** Bit definition for USB_OTG_HFIR register ********************/
8116#define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
8117
8118/******************** Bit definition for USB_OTG_HFNUM register ********************/
8119#define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
8120#define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
8121
8122/******************** Bit definition for USB_OTG_DSTS register ********************/
8123#define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
8124
8125#define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
8126#define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
8127#define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
8128#define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
8129#define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
8130
8131/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
8132#define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
8133#define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
8134#define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
8135#define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
8136#define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
8137#define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
8138#define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
8139#define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
8140#define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
8141
8142/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
8143#define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
8144#define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
8145#define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
8146#define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
8147#define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
8148#define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
8149#define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
8150#define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
8151#define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
8152#define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
8153#define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
8154#define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
8155#define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
8156#define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
8157#define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
8158#define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
8159#define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
8160#define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
8161#define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
8162#define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
8163#define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
8164#define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
8165#define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
8166#define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
8167#define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
8168
8169/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
8170#define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
8171#define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
8172#define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
8173#define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
8174#define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
8175#define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
8176#define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
8177#define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
8178#define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
8179#define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
8180#define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
8181#define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
8182#define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
8183
8184/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
8185#define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
8186#define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
8187#define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
8188#define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
8189#define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
8190#define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
8191#define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
8192#define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
8193
8194/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
8195#define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
8196#define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
8197#define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
8198#define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
8199#define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
8200#define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
8201#define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
8202#define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
8203#define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
8204#define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
8205
8206#define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
8207#define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
8208#define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
8209#define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
8210#define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
8211#define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
8212#define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
8213#define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
8214#define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
8215
8216/******************** Bit definition for USB_OTG_HAINT register ********************/
8217#define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
8218
8219/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
8220#define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
8221#define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
8222#define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
8223#define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
8224#define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
8225#define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
8226#define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
8227
8228/******************** Bit definition for USB_OTG_GINTSTS register ********************/
8229#define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
8230#define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
8231#define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
8232#define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
8233#define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
8234#define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
8235#define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
8236#define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
8237#define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
8238#define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
8239#define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
8240#define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
8241#define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
8242#define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
8243#define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
8244#define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
8245#define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
8246#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
8247#define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
8248#define USB_OTG_GINTSTS_RSTDET ((uint32_t)0x00800000) /*!< Reset detected interrupt */
8249#define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
8250#define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
8251#define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
8252#define USB_OTG_GINTSTS_LPMINT ((uint32_t)0x08000000) /*!< LPM interrupt */
8253#define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
8254#define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
8255#define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
8256#define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
8257
8258/******************** Bit definition for USB_OTG_GINTMSK register ********************/
8259#define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
8260#define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
8261#define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
8262#define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
8263#define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
8264#define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
8265#define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
8266#define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
8267#define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
8268#define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
8269#define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
8270#define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
8271#define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
8272#define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
8273#define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
8274#define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
8275#define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
8276#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
8277#define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
8278#define USB_OTG_GINTMSK_RSTDEM ((uint32_t)0x00800000) /*!< Reset detected interrupt mask */
8279#define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
8280#define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
8281#define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
8282#define USB_OTG_GINTMSK_LPMINTM ((uint32_t)0x08000000) /*!< LPM interrupt Mask */
8283#define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
8284#define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
8285#define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
8286#define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
8287
8288/******************** Bit definition for USB_OTG_DAINT register ********************/
8289#define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
8290#define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
8291
8292/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
8293#define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
8294
8295/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
8296#define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
8297#define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
8298#define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
8299#define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
8300
8301/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
8302#define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
8303#define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
8304
8305/******************** Bit definition for OTG register ********************/
8306
8307#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
8308#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
8309#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
8310#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
8311#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
8312#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
8313
8314#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
8315#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
8316#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
8317
8318#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
8319#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
8320#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
8321#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
8322#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
8323
8324#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
8325#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
8326#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
8327#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
8328#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
8329
8330#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
8331#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
8332#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
8333#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
8334#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
8335
8336/******************** Bit definition for OTG register ********************/
8337
8338#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
8339#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
8340#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
8341#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
8342#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
8343#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
8344
8345#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
8346#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
8347#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
8348
8349#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
8350#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
8351#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
8352#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
8353#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
8354
8355#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
8356#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
8357#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
8358#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
8359#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
8360
8361#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
8362#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
8363#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
8364#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
8365#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
8366
8367/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
8368#define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
8369
8370/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
8371#define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
8372
8373/******************** Bit definition for OTG register ********************/
8374#define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
8375#define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
8376#define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
8377#define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
8378
8379/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
8380#define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
8381
8382/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
8383#define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
8384
8385#define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
8386#define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
8387#define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
8388#define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
8389#define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
8390#define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
8391#define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
8392#define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
8393#define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
8394
8395#define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
8396#define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
8397#define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
8398#define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
8399#define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
8400#define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
8401#define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
8402#define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
8403
8404/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
8405#define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
8406#define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
8407
8408#define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
8409#define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
8410#define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
8411#define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
8412#define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
8413#define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
8414#define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
8415#define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
8416#define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
8417#define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
8418#define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
8419
8420#define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
8421#define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
8422#define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
8423#define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
8424#define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
8425#define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
8426#define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
8427#define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
8428#define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
8429#define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
8430#define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
8431
8432/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
8433#define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
8434
8435/******************** Bit definition for USB_OTG_DEACHINT register ********************/
8436#define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
8437#define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
8438
8439/******************** Bit definition for USB_OTG_GCCFG register ********************/
8440#define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
8441#define USB_OTG_GCCFG_VBDEN ((uint32_t)0x00200000) /*!< USB VBUS Detection Enable */
8442
8443/******************** Bit definition for USB_OTG_GPWRDN) register ********************/
8444#define USB_OTG_GPWRDN_ADPMEN ((uint32_t)0x00000001) /*!< ADP module enable */
8445#define USB_OTG_GPWRDN_ADPIF ((uint32_t)0x00800000) /*!< ADP Interrupt flag */
8446
8447/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
8448#define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
8449#define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
8450
8451/******************** Bit definition for USB_OTG_CID register ********************/
8452#define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
8453
8454/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
8455#define USB_OTG_GLPMCFG_LPMEN ((uint32_t)0x00000001) /*!< LPM support enable */
8456#define USB_OTG_GLPMCFG_LPMACK ((uint32_t)0x00000002) /*!< LPM Token acknowledge enable */
8457#define USB_OTG_GLPMCFG_BESL ((uint32_t)0x0000003C) /*!< BESL value received with last ACKed LPM Token */
8458#define USB_OTG_GLPMCFG_REMWAKE ((uint32_t)0x00000040) /*!< bRemoteWake value received with last ACKed LPM Token */
8459#define USB_OTG_GLPMCFG_L1SSEN ((uint32_t)0x00000080) /*!< L1 shallow sleep enable */
8460#define USB_OTG_GLPMCFG_BESLTHRS ((uint32_t)0x00000F00) /*!< BESL threshold */
8461#define USB_OTG_GLPMCFG_L1DSEN ((uint32_t)0x00001000) /*!< L1 deep sleep enable */
8462#define USB_OTG_GLPMCFG_LPMRSP ((uint32_t)0x00006000) /*!< LPM response */
8463#define USB_OTG_GLPMCFG_SLPSTS ((uint32_t)0x00008000) /*!< Port sleep status */
8464#define USB_OTG_GLPMCFG_L1RSMOK ((uint32_t)0x00010000) /*!< Sleep State Resume OK */
8465#define USB_OTG_GLPMCFG_LPMCHIDX ((uint32_t)0x001E0000) /*!< LPM Channel Index */
8466#define USB_OTG_GLPMCFG_LPMRCNT ((uint32_t)0x00E00000) /*!< LPM retry count */
8467#define USB_OTG_GLPMCFG_SNDLPM ((uint32_t)0x01000000) /*!< Send LPM transaction */
8468#define USB_OTG_GLPMCFG_LPMRCNTSTS ((uint32_t)0x0E000000) /*!< LPM retry count status */
8469#define USB_OTG_GLPMCFG_ENBESL ((uint32_t)0x10000000) /*!< Enable best effort service latency */
8470
8471/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
8472#define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
8473#define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
8474#define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
8475#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
8476#define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
8477#define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
8478#define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
8479#define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
8480#define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
8481
8482/******************** Bit definition for USB_OTG_HPRT register ********************/
8483#define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
8484#define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
8485#define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
8486#define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
8487#define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
8488#define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
8489#define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
8490#define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
8491#define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
8492
8493#define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
8494#define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
8495#define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
8496#define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
8497
8498#define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
8499#define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
8500#define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
8501#define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
8502#define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
8503
8504#define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
8505#define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
8506#define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
8507
8508/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
8509#define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
8510#define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
8511#define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
8512#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
8513#define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
8514#define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
8515#define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
8516#define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
8517#define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
8518#define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
8519#define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
8520
8521/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
8522#define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
8523#define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
8524
8525/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
8526#define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
8527#define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
8528#define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
8529#define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
8530
8531#define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
8532#define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
8533#define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
8534#define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
8535
8536#define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
8537#define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
8538#define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
8539#define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
8540#define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
8541#define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
8542#define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
8543#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
8544#define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
8545#define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
8546#define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
8547
8548/******************** Bit definition for USB_OTG_HCCHAR register ********************/
8549#define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
8550
8551#define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
8552#define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
8553#define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
8554#define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
8555#define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
8556#define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
8557#define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
8558
8559#define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
8560#define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
8561#define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
8562
8563#define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
8564#define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
8565#define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
8566
8567#define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
8568#define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
8569#define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
8570#define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
8571#define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
8572#define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
8573#define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
8574#define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
8575#define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
8576#define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
8577#define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
8578
8579/******************** Bit definition for USB_OTG_HCSPLT register ********************/
8580
8581#define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
8582#define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
8583#define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
8584#define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
8585#define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
8586#define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
8587#define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
8588#define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
8589
8590#define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
8591#define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
8592#define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
8593#define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
8594#define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
8595#define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
8596#define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
8597#define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
8598
8599#define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
8600#define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
8601#define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
8602#define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
8603#define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
8604
8605/******************** Bit definition for USB_OTG_HCINT register ********************/
8606#define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
8607#define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
8608#define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
8609#define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
8610#define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
8611#define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
8612#define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
8613#define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
8614#define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
8615#define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
8616#define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
8617
8618/******************** Bit definition for USB_OTG_DIEPINT register ********************/
8619#define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
8620#define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
8621#define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
8622#define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
8623#define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
8624#define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
8625#define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
8626#define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
8627#define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
8628#define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
8629#define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
8630
8631/******************** Bit definition for USB_OTG_HCINTMSK register ********************/
8632#define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
8633#define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
8634#define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
8635#define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
8636#define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
8637#define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
8638#define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
8639#define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
8640#define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
8641#define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
8642#define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
8643
8644/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
8645
8646#define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
8647#define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
8648#define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
8649/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
8650#define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
8651#define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
8652#define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
8653#define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
8654#define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
8655#define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
8656
8657/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
8658#define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
8659
8660/******************** Bit definition for USB_OTG_HCDMA register ********************/
8661#define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
8662
8663/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
8664#define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space available */
8665
8666/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
8667#define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
8668#define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
8669
8670/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
8671#define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
8672#define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
8673#define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
8674#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
8675#define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
8676#define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
8677#define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
8678#define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
8679#define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
8680#define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
8681#define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
8682#define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
8683#define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
8684#define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
8685
8686/******************** Bit definition for USB_OTG_DOEPINT register ********************/
8687#define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
8688#define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
8689#define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
8690#define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
8691#define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
8692#define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
8693
8694/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
8695#define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
8696#define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
8697
8698#define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
8699#define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
8700#define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
8701
8702/******************** Bit definition for PCGCCTL register ********************/
8703#define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
8704#define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
8705#define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
8706
8707/**
8708 * @}
8709 */
8710
8711/**
8712 * @}
8713 */
8714
8715/** @addtogroup Exported_macros
8716 * @{
8717 */
8718
8719/******************************* ADC Instances ********************************/
8720#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
8721 ((__INSTANCE__) == ADC2) || \
8722 ((__INSTANCE__) == ADC3))
8723
8724/******************************* CAN Instances ********************************/
8725#define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
8726 ((__INSTANCE__) == CAN2))
8727
8728/******************************* CRC Instances ********************************/
8729#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
8730
8731/******************************* DAC Instances ********************************/
8732#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
8733
8734/******************************* DCMI Instances *******************************/
8735#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
8736
8737/******************************* DMA2D Instances *******************************/
8738#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
8739
8740/******************************** DMA Instances *******************************/
8741#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
8742 ((__INSTANCE__) == DMA1_Stream1) || \
8743 ((__INSTANCE__) == DMA1_Stream2) || \
8744 ((__INSTANCE__) == DMA1_Stream3) || \
8745 ((__INSTANCE__) == DMA1_Stream4) || \
8746 ((__INSTANCE__) == DMA1_Stream5) || \
8747 ((__INSTANCE__) == DMA1_Stream6) || \
8748 ((__INSTANCE__) == DMA1_Stream7) || \
8749 ((__INSTANCE__) == DMA2_Stream0) || \
8750 ((__INSTANCE__) == DMA2_Stream1) || \
8751 ((__INSTANCE__) == DMA2_Stream2) || \
8752 ((__INSTANCE__) == DMA2_Stream3) || \
8753 ((__INSTANCE__) == DMA2_Stream4) || \
8754 ((__INSTANCE__) == DMA2_Stream5) || \
8755 ((__INSTANCE__) == DMA2_Stream6) || \
8756 ((__INSTANCE__) == DMA2_Stream7))
8757
8758/******************************* GPIO Instances *******************************/
8759#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
8760 ((__INSTANCE__) == GPIOB) || \
8761 ((__INSTANCE__) == GPIOC) || \
8762 ((__INSTANCE__) == GPIOD) || \
8763 ((__INSTANCE__) == GPIOE) || \
8764 ((__INSTANCE__) == GPIOF) || \
8765 ((__INSTANCE__) == GPIOG) || \
8766 ((__INSTANCE__) == GPIOH) || \
8767 ((__INSTANCE__) == GPIOI) || \
8768 ((__INSTANCE__) == GPIOJ) || \
8769 ((__INSTANCE__) == GPIOK))
8770
8771#define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
8772 ((__INSTANCE__) == GPIOB) || \
8773 ((__INSTANCE__) == GPIOC) || \
8774 ((__INSTANCE__) == GPIOD) || \
8775 ((__INSTANCE__) == GPIOE) || \
8776 ((__INSTANCE__) == GPIOF) || \
8777 ((__INSTANCE__) == GPIOG) || \
8778 ((__INSTANCE__) == GPIOH) || \
8779 ((__INSTANCE__) == GPIOI) || \
8780 ((__INSTANCE__) == GPIOJ) || \
8781 ((__INSTANCE__) == GPIOK))
8782
8783/****************************** CEC Instances *********************************/
8784#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
8785
8786/****************************** QSPI Instances *********************************/
8787#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
8788
8789
8790/******************************** I2C Instances *******************************/
8791#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
8792 ((__INSTANCE__) == I2C2) || \
8793 ((__INSTANCE__) == I2C3) || \
8794 ((__INSTANCE__) == I2C4))
8795
8796/******************************** I2S Instances *******************************/
8797#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
8798 ((__INSTANCE__) == SPI2) || \
8799 ((__INSTANCE__) == SPI3))
8800
8801/******************************* LPTIM Instances ********************************/
8802#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
8803
8804/******************************* RNG Instances ********************************/
8805#define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
8806
8807/****************************** RTC Instances *********************************/
8808#define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
8809
8810/******************************* SAI Instances ********************************/
8811#define IS_SAI_BLOCK_PERIPH(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
8812 ((__PERIPH__) == SAI1_Block_B) || \
8813 ((__PERIPH__) == SAI2_Block_A) || \
8814 ((__PERIPH__) == SAI2_Block_B))
8815
8816
8817/******************************** SDMMC Instances *******************************/
8818#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
8819
8820
8821/****************************** SPDIFRX Instances *********************************/
8822#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
8823
8824/******************************** SPI Instances *******************************/
8825#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
8826 ((__INSTANCE__) == SPI2) || \
8827 ((__INSTANCE__) == SPI3) || \
8828 ((__INSTANCE__) == SPI4) || \
8829 ((__INSTANCE__) == SPI5) || \
8830 ((__INSTANCE__) == SPI6))
8831
8832/****************** TIM Instances : All supported instances *******************/
8833#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
8834 ((__INSTANCE__) == TIM2) || \
8835 ((__INSTANCE__) == TIM3) || \
8836 ((__INSTANCE__) == TIM4) || \
8837 ((__INSTANCE__) == TIM5) || \
8838 ((__INSTANCE__) == TIM6) || \
8839 ((__INSTANCE__) == TIM7) || \
8840 ((__INSTANCE__) == TIM8) || \
8841 ((__INSTANCE__) == TIM9) || \
8842 ((__INSTANCE__) == TIM10) || \
8843 ((__INSTANCE__) == TIM11) || \
8844 ((__INSTANCE__) == TIM12) || \
8845 ((__INSTANCE__) == TIM13) || \
8846 ((__INSTANCE__) == TIM14))
8847
8848/************* TIM Instances : at least 1 capture/compare channel *************/
8849#define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
8850 ((__INSTANCE__) == TIM2) || \
8851 ((__INSTANCE__) == TIM3) || \
8852 ((__INSTANCE__) == TIM4) || \
8853 ((__INSTANCE__) == TIM5) || \
8854 ((__INSTANCE__) == TIM8) || \
8855 ((__INSTANCE__) == TIM9) || \
8856 ((__INSTANCE__) == TIM10) || \
8857 ((__INSTANCE__) == TIM11) || \
8858 ((__INSTANCE__) == TIM12) || \
8859 ((__INSTANCE__) == TIM13) || \
8860 ((__INSTANCE__) == TIM14))
8861
8862/************ TIM Instances : at least 2 capture/compare channels *************/
8863#define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
8864 ((__INSTANCE__) == TIM2) || \
8865 ((__INSTANCE__) == TIM3) || \
8866 ((__INSTANCE__) == TIM4) || \
8867 ((__INSTANCE__) == TIM5) || \
8868 ((__INSTANCE__) == TIM8) || \
8869 ((__INSTANCE__) == TIM9) || \
8870 ((__INSTANCE__) == TIM12))
8871
8872/************ TIM Instances : at least 3 capture/compare channels *************/
8873#define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
8874 ((__INSTANCE__) == TIM2) || \
8875 ((__INSTANCE__) == TIM3) || \
8876 ((__INSTANCE__) == TIM4) || \
8877 ((__INSTANCE__) == TIM5) || \
8878 ((__INSTANCE__) == TIM8))
8879
8880/************ TIM Instances : at least 4 capture/compare channels *************/
8881#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
8882 ((__INSTANCE__) == TIM2) || \
8883 ((__INSTANCE__) == TIM3) || \
8884 ((__INSTANCE__) == TIM4) || \
8885 ((__INSTANCE__) == TIM5) || \
8886 ((__INSTANCE__) == TIM8))
8887
8888/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
8889#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
8890 (((__INSTANCE__) == TIM1) || \
8891 ((__INSTANCE__) == TIM8))
8892
8893/****************** TIM Instances : supporting OCxREF clear *******************/
8894#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
8895 (((__INSTANCE__) == TIM1) || \
8896 ((__INSTANCE__) == TIM2) || \
8897 ((__INSTANCE__) == TIM3) || \
8898 ((__INSTANCE__) == TIM4) || \
8899 ((__INSTANCE__) == TIM8))
8900
8901/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
8902#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
8903 (((__INSTANCE__) == TIM1) || \
8904 ((__INSTANCE__) == TIM2) || \
8905 ((__INSTANCE__) == TIM3) || \
8906 ((__INSTANCE__) == TIM4) || \
8907 ((__INSTANCE__) == TIM5) || \
8908 ((__INSTANCE__) == TIM8))
8909
8910/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
8911#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
8912 (((__INSTANCE__) == TIM1) || \
8913 ((__INSTANCE__) == TIM2) || \
8914 ((__INSTANCE__) == TIM3) || \
8915 ((__INSTANCE__) == TIM4) || \
8916 ((__INSTANCE__) == TIM5) || \
8917 ((__INSTANCE__) == TIM8))
8918/****************** TIM Instances : at least 5 capture/compare channels *******/
8919#define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
8920 (((__INSTANCE__) == TIM1) || \
8921 ((__INSTANCE__) == TIM8) )
8922
8923/****************** TIM Instances : at least 6 capture/compare channels *******/
8924#define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
8925 (((__INSTANCE__) == TIM1) || \
8926 ((__INSTANCE__) == TIM8))
8927
8928
8929/******************** TIM Instances : Advanced-control timers *****************/
8930#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
8931 ((__INSTANCE__) == TIM8))
8932
8933/****************** TIM Instances : supporting 2 break inputs *****************/
8934#define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
8935 (((__INSTANCE__) == TIM1) || \
8936 ((__INSTANCE__) == TIM8))
8937
8938/******************* TIM Instances : Timer input XOR function *****************/
8939#define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
8940 ((__INSTANCE__) == TIM2) || \
8941 ((__INSTANCE__) == TIM3) || \
8942 ((__INSTANCE__) == TIM4) || \
8943 ((__INSTANCE__) == TIM5) || \
8944 ((__INSTANCE__) == TIM8))
8945
8946/****************** TIM Instances : DMA requests generation (UDE) *************/
8947#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
8948 ((__INSTANCE__) == TIM2) || \
8949 ((__INSTANCE__) == TIM3) || \
8950 ((__INSTANCE__) == TIM4) || \
8951 ((__INSTANCE__) == TIM5) || \
8952 ((__INSTANCE__) == TIM6) || \
8953 ((__INSTANCE__) == TIM7) || \
8954 ((__INSTANCE__) == TIM8))
8955
8956/************ TIM Instances : DMA requests generation (CCxDE) *****************/
8957#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
8958 ((__INSTANCE__) == TIM2) || \
8959 ((__INSTANCE__) == TIM3) || \
8960 ((__INSTANCE__) == TIM4) || \
8961 ((__INSTANCE__) == TIM5) || \
8962 ((__INSTANCE__) == TIM8))
8963
8964/************ TIM Instances : DMA requests generation (COMDE) *****************/
8965#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
8966 ((__INSTANCE__) == TIM2) || \
8967 ((__INSTANCE__) == TIM3) || \
8968 ((__INSTANCE__) == TIM4) || \
8969 ((__INSTANCE__) == TIM5) || \
8970 ((__INSTANCE__) == TIM8))
8971
8972/******************** TIM Instances : DMA burst feature ***********************/
8973#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
8974 ((__INSTANCE__) == TIM2) || \
8975 ((__INSTANCE__) == TIM3) || \
8976 ((__INSTANCE__) == TIM4) || \
8977 ((__INSTANCE__) == TIM5) || \
8978 ((__INSTANCE__) == TIM8))
8979
8980/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
8981#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
8982 ((__INSTANCE__) == TIM2) || \
8983 ((__INSTANCE__) == TIM3) || \
8984 ((__INSTANCE__) == TIM4) || \
8985 ((__INSTANCE__) == TIM5) || \
8986 ((__INSTANCE__) == TIM6) || \
8987 ((__INSTANCE__) == TIM7) || \
8988 ((__INSTANCE__) == TIM8) || \
8989 ((__INSTANCE__) == TIM13) || \
8990 ((__INSTANCE__) == TIM14))
8991
8992/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
8993#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
8994 ((__INSTANCE__) == TIM2) || \
8995 ((__INSTANCE__) == TIM3) || \
8996 ((__INSTANCE__) == TIM4) || \
8997 ((__INSTANCE__) == TIM5) || \
8998 ((__INSTANCE__) == TIM8) || \
8999 ((__INSTANCE__) == TIM9) || \
9000 ((__INSTANCE__) == TIM12))
9001
9002/********************** TIM Instances : 32 bit Counter ************************/
9003#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \
9004 ((__INSTANCE__) == TIM5))
9005
9006/***************** TIM Instances : external trigger input available ************/
9007#define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9008 ((__INSTANCE__) == TIM2) || \
9009 ((__INSTANCE__) == TIM3) || \
9010 ((__INSTANCE__) == TIM4) || \
9011 ((__INSTANCE__) == TIM5) || \
9012 ((__INSTANCE__) == TIM8))
9013
9014/****************** TIM Instances : remapping capability **********************/
9015#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
9016 ((__INSTANCE__) == TIM5) || \
9017 ((__INSTANCE__) == TIM11))
9018
9019/******************* TIM Instances : output(s) available **********************/
9020#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
9021 ((((__INSTANCE__) == TIM1) && \
9022 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9023 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9024 ((__CHANNEL__) == TIM_CHANNEL_3) || \
9025 ((__CHANNEL__) == TIM_CHANNEL_4))) \
9026 || \
9027 (((__INSTANCE__) == TIM2) && \
9028 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9029 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9030 ((__CHANNEL__) == TIM_CHANNEL_3) || \
9031 ((__CHANNEL__) == TIM_CHANNEL_4))) \
9032 || \
9033 (((__INSTANCE__) == TIM3) && \
9034 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9035 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9036 ((__CHANNEL__) == TIM_CHANNEL_3) || \
9037 ((__CHANNEL__) == TIM_CHANNEL_4))) \
9038 || \
9039 (((__INSTANCE__) == TIM4) && \
9040 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9041 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9042 ((__CHANNEL__) == TIM_CHANNEL_3) || \
9043 ((__CHANNEL__) == TIM_CHANNEL_4))) \
9044 || \
9045 (((__INSTANCE__) == TIM5) && \
9046 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9047 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9048 ((__CHANNEL__) == TIM_CHANNEL_3) || \
9049 ((__CHANNEL__) == TIM_CHANNEL_4))) \
9050 || \
9051 (((__INSTANCE__) == TIM8) && \
9052 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9053 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9054 ((__CHANNEL__) == TIM_CHANNEL_3) || \
9055 ((__CHANNEL__) == TIM_CHANNEL_4))) \
9056 || \
9057 (((__INSTANCE__) == TIM9) && \
9058 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9059 ((__CHANNEL__) == TIM_CHANNEL_2))) \
9060 || \
9061 (((__INSTANCE__) == TIM10) && \
9062 (((__CHANNEL__) == TIM_CHANNEL_1))) \
9063 || \
9064 (((__INSTANCE__) == TIM11) && \
9065 (((__CHANNEL__) == TIM_CHANNEL_1))) \
9066 || \
9067 (((__INSTANCE__) == TIM12) && \
9068 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9069 ((__CHANNEL__) == TIM_CHANNEL_2))) \
9070 || \
9071 (((__INSTANCE__) == TIM13) && \
9072 (((__CHANNEL__) == TIM_CHANNEL_1))) \
9073 || \
9074 (((__INSTANCE__) == TIM14) && \
9075 (((__CHANNEL__) == TIM_CHANNEL_1))))
9076
9077/************ TIM Instances : complementary output(s) available ***************/
9078#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
9079 ((((__INSTANCE__) == TIM1) && \
9080 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9081 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9082 ((__CHANNEL__) == TIM_CHANNEL_3))) \
9083 || \
9084 (((__INSTANCE__) == TIM8) && \
9085 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9086 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9087 ((__CHANNEL__) == TIM_CHANNEL_3))))
9088
9089/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
9090#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
9091 (((__INSTANCE__) == TIM1) || \
9092 ((__INSTANCE__) == TIM8) )
9093
9094/****************** TIM Instances : supporting synchronization ****************/
9095#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
9096 (((__INSTANCE__) == TIM1) || \
9097 ((__INSTANCE__) == TIM2) || \
9098 ((__INSTANCE__) == TIM3) || \
9099 ((__INSTANCE__) == TIM4) || \
9100 ((__INSTANCE__) == TIM5) || \
9101 ((__INSTANCE__) == TIM6) || \
9102 ((__INSTANCE__) == TIM7) || \
9103 ((__INSTANCE__) == TIM8))
9104
9105/******************** USART Instances : Synchronous mode **********************/
9106#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9107 ((__INSTANCE__) == USART2) || \
9108 ((__INSTANCE__) == USART3) || \
9109 ((__INSTANCE__) == USART6))
9110
9111/******************** UART Instances : Asynchronous mode **********************/
9112#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9113 ((__INSTANCE__) == USART2) || \
9114 ((__INSTANCE__) == USART3) || \
9115 ((__INSTANCE__) == UART4) || \
9116 ((__INSTANCE__) == UART5) || \
9117 ((__INSTANCE__) == USART6) || \
9118 ((__INSTANCE__) == UART7) || \
9119 ((__INSTANCE__) == UART8))
9120
9121/****************** UART Instances : Hardware Flow control ********************/
9122#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9123 ((__INSTANCE__) == USART2) || \
9124 ((__INSTANCE__) == USART3) || \
9125 ((__INSTANCE__) == UART4) || \
9126 ((__INSTANCE__) == UART5) || \
9127 ((__INSTANCE__) == USART6) || \
9128 ((__INSTANCE__) == UART7) || \
9129 ((__INSTANCE__) == UART8))
9130
9131/********************* UART Instances : Smart card mode ***********************/
9132#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9133 ((__INSTANCE__) == USART2) || \
9134 ((__INSTANCE__) == USART3) || \
9135 ((__INSTANCE__) == USART6))
9136
9137/*********************** UART Instances : IRDA mode ***************************/
9138#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9139 ((__INSTANCE__) == USART2) || \
9140 ((__INSTANCE__) == USART3) || \
9141 ((__INSTANCE__) == UART4) || \
9142 ((__INSTANCE__) == UART5) || \
9143 ((__INSTANCE__) == USART6) || \
9144 ((__INSTANCE__) == UART7) || \
9145 ((__INSTANCE__) == UART8))
9146
9147/****************************** IWDG Instances ********************************/
9148#define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
9149
9150/****************************** WWDG Instances ********************************/
9151#define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
9152
9153
9154/******************************************************************************/
9155/* For a painless codes migration between the STM32F7xx device product */
9156/* lines, the aliases defined below are put in place to overcome the */
9157/* differences in the interrupt handlers and IRQn definitions. */
9158/* No need to update developed interrupt code when moving across */
9159/* product lines within the same STM32F7 Family */
9160/******************************************************************************/
9161
9162/* Aliases for __IRQn */
9163#define HASH_RNG_IRQn RNG_IRQn
9164
9165/* Aliases for __IRQHandler */
9166#define HASH_RNG_IRQHandler RNG_IRQHandler
9167
9168/**
9169 * @}
9170 */
9171
9172/**
9173 * @}
9174 */
9175
9176/**
9177 * @}
9178 */
9179
9180#ifdef __cplusplus
9181}
9182#endif /* __cplusplus */
9183
9184#endif /* __STM32F745xx_H */
9185
9186
9187/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/