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192.168.1.100 / T103 / 1f884588077ad3476b9c91cbb0ee9ee0332bbb68 / . / src / bsp / lk / platform / stm32f7xx / CMSIS / stm32f746xx.h
blob: 0ca7de8f536554dc5d875a50723c5525cef85393 [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +0800[diff] [blame^]1/**
2 ******************************************************************************
3 * @file stm32f746xx.h
4 * @author MCD Application Team
5 * @version V1.0.1
6 * @date 25-June-2015
7 * @brief CMSIS STM32F746xx Device Peripheral Access Layer Header File.
8 *
9 * This file contains:
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheralÂ’s registers hardware
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44/** @addtogroup CMSIS_Device
45 * @{
46 */
47
48/** @addtogroup stm32f746xx
49 * @{
50 */
51
52#ifndef __STM32F746xx_H
53#define __STM32F746xx_H
54
55#ifdef __cplusplus
56extern "C" {
57#endif /* __cplusplus */
58
59/** @addtogroup Configuration_section_for_CMSIS
60 * @{
61 */
62
63/**
64 * @brief STM32F7xx Interrupt Number Definition, according to the selected device
65 * in @ref Library_configuration_section
66 */
67typedef enum IRQn {
68 /****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
69 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
70 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */
71 BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */
72 UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */
73 SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */
74 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */
75 PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */
76 SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */
77 /****** STM32 specific Interrupt Numbers **********************************************************************/
78 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
79 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
80 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
81 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
82 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
83 RCC_IRQn = 5, /*!< RCC global Interrupt */
84 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
85 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
86 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
87 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
88 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
89 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
90 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
91 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
92 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
93 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
94 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
95 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
96 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
97 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
98 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
99 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
100 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
101 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
102 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
103 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
104 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
105 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
106 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
107 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
108 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
109 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
110 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
111 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
112 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
113 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
114 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
115 USART1_IRQn = 37, /*!< USART1 global Interrupt */
116 USART2_IRQn = 38, /*!< USART2 global Interrupt */
117 USART3_IRQn = 39, /*!< USART3 global Interrupt */
118 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
119 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
120 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
121 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
122 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
123 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
124 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
125 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
126 FMC_IRQn = 48, /*!< FMC global Interrupt */
127 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
128 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
129 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
130 UART4_IRQn = 52, /*!< UART4 global Interrupt */
131 UART5_IRQn = 53, /*!< UART5 global Interrupt */
132 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
133 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
134 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
135 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
136 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
137 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
138 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
139 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
140 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
141 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
142 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
143 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
144 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
145 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
146 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
147 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
148 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
149 USART6_IRQn = 71, /*!< USART6 global interrupt */
150 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
151 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
152 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
153 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
154 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
155 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
156 DCMI_IRQn = 78, /*!< DCMI global interrupt */
157 RNG_IRQn = 80, /*!< RNG global interrupt */
158 FPU_IRQn = 81, /*!< FPU global interrupt */
159 UART7_IRQn = 82, /*!< UART7 global interrupt */
160 UART8_IRQn = 83, /*!< UART8 global interrupt */
161 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
162 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
163 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
164 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
165 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
166 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
167 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
168 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
169 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
170 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
171 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
172 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
173 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
174 SPDIF_RX_IRQn = 97 /*!< SPDIF-RX global Interrupt */
175} IRQn_Type;
176
177/**
178 * @}
179 */
180
181/**
182 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
183 */
184#define __CM7_REV 0x0000 /*!< Cortex-M7 revision r0p1 */
185#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
186#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
187#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
188#define __FPU_PRESENT 1 /*!< FPU present */
189#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
190#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
191#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
192
193
194#include "system_stm32f7xx.h"
195#include <stdint.h>
196
197/** @addtogroup Peripheral_registers_structures
198 * @{
199 */
200
201/**
202 * @brief Analog to Digital Converter
203 */
204
205typedef struct {
206 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
207 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
208 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
209 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
210 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
211 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
212 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
213 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
214 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
215 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
216 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
217 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
218 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
219 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
220 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
221 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
222 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
223 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
224 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
225 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
226} ADC_TypeDef;
227
228typedef struct {
229 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
230 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
231 __IO uint32_t CDR; /*!< ADC common regular data register for dual
232 AND triple modes, Address offset: ADC1 base address + 0x308 */
233} ADC_Common_TypeDef;
234
235
236/**
237 * @brief Controller Area Network TxMailBox
238 */
239
240typedef struct {
241 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
242 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
243 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
244 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
245} CAN_TxMailBox_TypeDef;
246
247/**
248 * @brief Controller Area Network FIFOMailBox
249 */
250
251typedef struct {
252 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
253 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
254 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
255 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
256} CAN_FIFOMailBox_TypeDef;
257
258/**
259 * @brief Controller Area Network FilterRegister
260 */
261
262typedef struct {
263 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
264 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
265} CAN_FilterRegister_TypeDef;
266
267/**
268 * @brief Controller Area Network
269 */
270
271typedef struct {
272 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
273 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
274 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
275 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
276 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
277 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
278 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
279 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
280 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
281 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
282 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
283 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
284 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
285 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
286 uint32_t RESERVED2; /*!< Reserved, 0x208 */
287 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
288 uint32_t RESERVED3; /*!< Reserved, 0x210 */
289 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
290 uint32_t RESERVED4; /*!< Reserved, 0x218 */
291 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
292 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
293 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
294} CAN_TypeDef;
295
296/**
297 * @brief HDMI-CEC
298 */
299
300typedef struct {
301 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
302 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
303 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
304 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
305 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
306 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
307} CEC_TypeDef;
308
309
310/**
311 * @brief CRC calculation unit
312 */
313
314typedef struct {
315 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
316 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
317 uint8_t RESERVED0; /*!< Reserved, 0x05 */
318 uint16_t RESERVED1; /*!< Reserved, 0x06 */
319 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
320 uint32_t RESERVED2; /*!< Reserved, 0x0C */
321 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
322 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
323} CRC_TypeDef;
324
325/**
326 * @brief Digital to Analog Converter
327 */
328
329typedef struct {
330 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
331 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
332 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
333 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
334 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
335 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
336 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
337 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
338 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
339 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
340 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
341 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
342 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
343 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
344} DAC_TypeDef;
345
346/**
347 * @brief Debug MCU
348 */
349
350typedef struct {
351 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
352 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
353 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
354 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
355} DBGMCU_TypeDef;
356
357/**
358 * @brief DCMI
359 */
360
361typedef struct {
362 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
363 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
364 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
365 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
366 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
367 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
368 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
369 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
370 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
371 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
372 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
373} DCMI_TypeDef;
374
375/**
376 * @brief DMA Controller
377 */
378
379typedef struct {
380 __IO uint32_t CR; /*!< DMA stream x configuration register */
381 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
382 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
383 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
384 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
385 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
386} DMA_Stream_TypeDef;
387
388typedef struct {
389 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
390 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
391 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
392 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
393} DMA_TypeDef;
394
395
396/**
397 * @brief DMA2D Controller
398 */
399
400typedef struct {
401 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
402 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
403 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
404 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
405 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
406 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
407 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
408 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
409 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
410 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
411 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
412 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
413 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
414 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
415 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
416 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
417 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
418 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
419 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
420 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
421 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
422 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
423 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
424} DMA2D_TypeDef;
425
426
427/**
428 * @brief Ethernet MAC
429 */
430
431typedef struct {
432 __IO uint32_t MACCR;
433 __IO uint32_t MACFFR;
434 __IO uint32_t MACHTHR;
435 __IO uint32_t MACHTLR;
436 __IO uint32_t MACMIIAR;
437 __IO uint32_t MACMIIDR;
438 __IO uint32_t MACFCR;
439 __IO uint32_t MACVLANTR; /* 8 */
440 uint32_t RESERVED0[2];
441 __IO uint32_t MACRWUFFR; /* 11 */
442 __IO uint32_t MACPMTCSR;
443 uint32_t RESERVED1[2];
444 __IO uint32_t MACSR; /* 15 */
445 __IO uint32_t MACIMR;
446 __IO uint32_t MACA0HR;
447 __IO uint32_t MACA0LR;
448 __IO uint32_t MACA1HR;
449 __IO uint32_t MACA1LR;
450 __IO uint32_t MACA2HR;
451 __IO uint32_t MACA2LR;
452 __IO uint32_t MACA3HR;
453 __IO uint32_t MACA3LR; /* 24 */
454 uint32_t RESERVED2[40];
455 __IO uint32_t MMCCR; /* 65 */
456 __IO uint32_t MMCRIR;
457 __IO uint32_t MMCTIR;
458 __IO uint32_t MMCRIMR;
459 __IO uint32_t MMCTIMR; /* 69 */
460 uint32_t RESERVED3[14];
461 __IO uint32_t MMCTGFSCCR; /* 84 */
462 __IO uint32_t MMCTGFMSCCR;
463 uint32_t RESERVED4[5];
464 __IO uint32_t MMCTGFCR;
465 uint32_t RESERVED5[10];
466 __IO uint32_t MMCRFCECR;
467 __IO uint32_t MMCRFAECR;
468 uint32_t RESERVED6[10];
469 __IO uint32_t MMCRGUFCR;
470 uint32_t RESERVED7[334];
471 __IO uint32_t PTPTSCR;
472 __IO uint32_t PTPSSIR;
473 __IO uint32_t PTPTSHR;
474 __IO uint32_t PTPTSLR;
475 __IO uint32_t PTPTSHUR;
476 __IO uint32_t PTPTSLUR;
477 __IO uint32_t PTPTSAR;
478 __IO uint32_t PTPTTHR;
479 __IO uint32_t PTPTTLR;
480 __IO uint32_t RESERVED8;
481 __IO uint32_t PTPTSSR;
482 uint32_t RESERVED9[565];
483 __IO uint32_t DMABMR;
484 __IO uint32_t DMATPDR;
485 __IO uint32_t DMARPDR;
486 __IO uint32_t DMARDLAR;
487 __IO uint32_t DMATDLAR;
488 __IO uint32_t DMASR;
489 __IO uint32_t DMAOMR;
490 __IO uint32_t DMAIER;
491 __IO uint32_t DMAMFBOCR;
492 __IO uint32_t DMARSWTR;
493 uint32_t RESERVED10[8];
494 __IO uint32_t DMACHTDR;
495 __IO uint32_t DMACHRDR;
496 __IO uint32_t DMACHTBAR;
497 __IO uint32_t DMACHRBAR;
498} ETH_TypeDef;
499
500/**
501 * @brief External Interrupt/Event Controller
502 */
503
504typedef struct {
505 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
506 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
507 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
508 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
509 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
510 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
511} EXTI_TypeDef;
512
513/**
514 * @brief FLASH Registers
515 */
516
517typedef struct {
518 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
519 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
520 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
521 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
522 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
523 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
524 __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */
525} FLASH_TypeDef;
526
527
528
529/**
530 * @brief Flexible Memory Controller
531 */
532
533typedef struct {
534 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
535} FMC_Bank1_TypeDef;
536
537/**
538 * @brief Flexible Memory Controller Bank1E
539 */
540
541typedef struct {
542 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
543} FMC_Bank1E_TypeDef;
544
545/**
546 * @brief Flexible Memory Controller Bank3
547 */
548
549typedef struct {
550 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
551 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
552 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
553 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
554 uint32_t RESERVED0; /*!< Reserved, 0x90 */
555 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
556} FMC_Bank3_TypeDef;
557
558/**
559 * @brief Flexible Memory Controller Bank5_6
560 */
561
562typedef struct {
563 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
564 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
565 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
566 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
567 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
568} FMC_Bank5_6_TypeDef;
569
570
571/**
572 * @brief General Purpose I/O
573 */
574
575typedef struct {
576 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
577 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
578 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
579 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
580 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
581 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
582 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
583 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
584 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
585} GPIO_TypeDef;
586
587/**
588 * @brief System configuration controller
589 */
590
591typedef struct {
592 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
593 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
594 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
595 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
596 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
597} SYSCFG_TypeDef;
598
599/**
600 * @brief Inter-integrated Circuit Interface
601 */
602
603typedef struct {
604 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
605 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
606 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
607 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
608 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
609 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
610 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
611 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
612 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
613 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
614 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
615} I2C_TypeDef;
616
617/**
618 * @brief Independent WATCHDOG
619 */
620
621typedef struct {
622 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
623 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
624 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
625 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
626 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
627} IWDG_TypeDef;
628
629
630/**
631 * @brief LCD-TFT Display Controller
632 */
633
634typedef struct {
635 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
636 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
637 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
638 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
639 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
640 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
641 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
642 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
643 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
644 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
645 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
646 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
647 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
648 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
649 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
650 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
651 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
652} LTDC_TypeDef;
653
654/**
655 * @brief LCD-TFT Display layer x Controller
656 */
657
658typedef struct {
659 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
660 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
661 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
662 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
663 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
664 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
665 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
666 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
667 uint32_t RESERVED0[2]; /*!< Reserved */
668 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
669 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
670 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
671 uint32_t RESERVED1[3]; /*!< Reserved */
672 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
673
674} LTDC_Layer_TypeDef;
675
676
677/**
678 * @brief Power Control
679 */
680
681typedef struct {
682 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
683 __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */
684 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
685 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */
686} PWR_TypeDef;
687
688
689/**
690 * @brief Reset and Clock Control
691 */
692
693typedef struct {
694 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
695 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
696 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
697 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
698 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
699 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
700 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
701 uint32_t RESERVED0; /*!< Reserved, 0x1C */
702 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
703 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
704 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
705 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
706 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
707 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
708 uint32_t RESERVED2; /*!< Reserved, 0x3C */
709 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
710 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
711 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
712 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
713 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
714 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
715 uint32_t RESERVED4; /*!< Reserved, 0x5C */
716 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
717 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
718 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
719 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
720 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
721 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
722 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
723 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
724 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
725 __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */
726 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */
727
728} RCC_TypeDef;
729
730/**
731 * @brief Real-Time Clock
732 */
733
734typedef struct {
735 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
736 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
737 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
738 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
739 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
740 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
741 uint32_t reserved; /*!< Reserved */
742 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
743 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
744 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
745 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
746 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
747 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
748 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
749 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
750 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
751 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
752 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
753 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
754 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
755 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
756 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
757 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
758 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
759 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
760 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
761 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
762 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
763 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
764 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
765 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
766 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
767 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
768 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
769 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
770 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
771 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
772 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
773 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
774 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
775 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
776 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
777 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
778 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
779 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
780 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
781 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
782 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
783 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
784 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
785 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
786 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
787} RTC_TypeDef;
788
789
790/**
791 * @brief Serial Audio Interface
792 */
793
794typedef struct {
795 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
796} SAI_TypeDef;
797
798typedef struct {
799 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
800 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
801 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
802 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
803 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
804 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
805 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
806 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
807} SAI_Block_TypeDef;
808
809/**
810 * @brief SPDIF-RX Interface
811 */
812
813typedef struct {
814 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
815 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
816 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
817 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
818 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
819 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
820 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
821} SPDIFRX_TypeDef;
822
823
824/**
825 * @brief SD host Interface
826 */
827
828typedef struct {
829 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
830 __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */
831 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
832 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
833 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
834 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
835 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
836 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
837 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
838 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
839 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
840 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
841 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
842 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
843 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
844 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
845 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
846 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
847 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
848 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
849} SDMMC_TypeDef;
850
851/**
852 * @brief Serial Peripheral Interface
853 */
854
855typedef struct {
856 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
857 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
858 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
859 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
860 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
861 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
862 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
863 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
864 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
865} SPI_TypeDef;
866
867/**
868 * @brief QUAD Serial Peripheral Interface
869 */
870
871typedef struct {
872 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
873 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
874 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
875 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
876 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
877 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
878 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
879 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
880 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
881 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
882 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
883 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
884 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
885} QUADSPI_TypeDef;
886
887/**
888 * @brief TIM
889 */
890
891typedef struct {
892 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
893 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
894 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
895 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
896 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
897 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
898 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
899 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
900 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
901 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
902 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
903 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
904 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
905 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
906 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
907 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
908 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
909 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
910 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
911 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
912 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
913 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
914 __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */
915 __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */
916
917} TIM_TypeDef;
918
919/**
920 * @brief LPTIMIMER
921 */
922typedef struct {
923 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
924 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
925 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
926 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
927 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
928 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
929 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
930 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
931 __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
932} LPTIM_TypeDef;
933
934
935/**
936 * @brief Universal Synchronous Asynchronous Receiver Transmitter
937 */
938
939typedef struct {
940 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
941 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
942 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
943 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
944 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
945 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
946 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
947 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
948 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
949 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
950 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
951} USART_TypeDef;
952
953
954/**
955 * @brief Window WATCHDOG
956 */
957
958typedef struct {
959 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
960 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
961 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
962} WWDG_TypeDef;
963
964/**
965 * @brief RNG
966 */
967
968typedef struct {
969 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
970 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
971 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
972} RNG_TypeDef;
973
974/**
975 * @}
976 */
977
978/**
979 * @brief USB_OTG_Core_Registers
980 */
981typedef struct {
982 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
983 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
984 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
985 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
986 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
987 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
988 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
989 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
990 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
991 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
992 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
993 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
994 uint32_t Reserved30[2]; /*!< Reserved 030h */
995 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
996 __IO uint32_t CID; /*!< User ID Register 03Ch */
997 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
998 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
999 uint32_t Reserved6; /*!< Reserved 050h */
1000 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
1001 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
1002 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
1003 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
1004 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
1005 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
1006 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
1007} USB_OTG_GlobalTypeDef;
1008
1009
1010/**
1011 * @brief USB_OTG_device_Registers
1012 */
1013typedef struct {
1014 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
1015 __IO uint32_t DCTL; /*!< dev Control Register 804h */
1016 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
1017 uint32_t Reserved0C; /*!< Reserved 80Ch */
1018 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
1019 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
1020 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
1021 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
1022 uint32_t Reserved20; /*!< Reserved 820h */
1023 uint32_t Reserved9; /*!< Reserved 824h */
1024 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
1025 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
1026 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
1027 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
1028 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
1029 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
1030 uint32_t Reserved40; /*!< dedicated EP mask 840h */
1031 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
1032 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
1033 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
1034} USB_OTG_DeviceTypeDef;
1035
1036
1037/**
1038 * @brief USB_OTG_IN_Endpoint-Specific_Register
1039 */
1040typedef struct {
1041 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
1042 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
1043 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
1044 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
1045 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
1046 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
1047 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
1048 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
1049} USB_OTG_INEndpointTypeDef;
1050
1051
1052/**
1053 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1054 */
1055typedef struct {
1056 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
1057 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
1058 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
1059 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
1060 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
1061 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
1062 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
1063} USB_OTG_OUTEndpointTypeDef;
1064
1065
1066/**
1067 * @brief USB_OTG_Host_Mode_Register_Structures
1068 */
1069typedef struct {
1070 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
1071 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
1072 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
1073 uint32_t Reserved40C; /*!< Reserved 40Ch */
1074 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
1075 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
1076 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
1077} USB_OTG_HostTypeDef;
1078
1079/**
1080 * @brief USB_OTG_Host_Channel_Specific_Registers
1081 */
1082typedef struct {
1083 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
1084 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
1085 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
1086 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
1087 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
1088 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
1089 uint32_t Reserved[2]; /*!< Reserved */
1090} USB_OTG_HostChannelTypeDef;
1091/**
1092 * @}
1093 */
1094
1095
1096/** @addtogroup Peripheral_memory_map
1097 * @{
1098 */
1099#define RAMITCM_BASE ((uint32_t)0x00000000) /*!< Base address of :16KB RAM reserved for CPU execution/instruction accessible over ITCM */
1100#define FLASHITCM_BASE ((uint32_t)0x00200000) /*!< Base address of :(up to 1 MB) embedded FLASH memory accessible over ITCM */
1101#define FLASHAXI_BASE ((uint32_t)0x08000000) /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */
1102#define RAMDTCM_BASE ((uint32_t)0x20000000) /*!< Base address of : 64KB system data RAM accessible over DTCM */
1103#define SRAM1_BASE ((uint32_t)0x20010000) /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */
1104#define SRAM2_BASE ((uint32_t)0x2004C000) /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
1105#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */
1106#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Base address of : Backup SRAM(4 KB) */
1107#define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */
1108#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< Base address of : FMC Control registers */
1109#define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< Base address of : QSPI Control registers */
1110#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
1111
1112/* Legacy define */
1113#define FLASH_BASE FLASHAXI_BASE
1114
1115/*!< Peripheral memory map */
1116#define APB1PERIPH_BASE PERIPH_BASE
1117#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
1118#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
1119#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
1120
1121/*!< APB1 peripherals */
1122#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
1123#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
1124#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
1125#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
1126#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
1127#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
1128#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
1129#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
1130#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
1131#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400)
1132#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
1133#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
1134#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
1135#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
1136#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
1137#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000)
1138#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
1139#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
1140#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
1141#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
1142#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
1143#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
1144#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
1145#define I2C4_BASE (APB1PERIPH_BASE + 0x6000)
1146#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
1147#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
1148#define CEC_BASE (APB1PERIPH_BASE + 0x6C00)
1149#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
1150#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
1151#define UART7_BASE (APB1PERIPH_BASE + 0x7800)
1152#define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
1153
1154/*!< APB2 peripherals */
1155#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
1156#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
1157#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
1158#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
1159#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
1160#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
1161#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
1162#define ADC_BASE (APB2PERIPH_BASE + 0x2300)
1163#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00)
1164#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
1165#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
1166#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
1167#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
1168#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
1169#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
1170#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
1171#define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
1172#define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
1173#define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
1174#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00)
1175#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
1176#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
1177#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
1178#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
1179#define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
1180#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
1181#define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
1182/*!< AHB1 peripherals */
1183#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
1184#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
1185#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
1186#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
1187#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
1188#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
1189#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
1190#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
1191#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
1192#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
1193#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
1194#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
1195#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
1196#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
1197#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
1198#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
1199#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
1200#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
1201#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
1202#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
1203#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
1204#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
1205#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
1206#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
1207#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
1208#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
1209#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
1210#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
1211#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
1212#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
1213#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
1214#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
1215#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
1216#define ETH_MAC_BASE (ETH_BASE)
1217#define ETH_MMC_BASE (ETH_BASE + 0x0100)
1218#define ETH_PTP_BASE (ETH_BASE + 0x0700)
1219#define ETH_DMA_BASE (ETH_BASE + 0x1000)
1220#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)
1221/*!< AHB2 peripherals */
1222#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
1223#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
1224/*!< FMC Bankx registers base address */
1225#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
1226#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
1227#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
1228#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
1229
1230/* Debug MCU registers base address */
1231#define DBGMCU_BASE ((uint32_t )0xE0042000)
1232
1233/*!< USB registers base address */
1234#define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
1235#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
1236
1237#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
1238#define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
1239#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
1240#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
1241#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
1242#define USB_OTG_HOST_BASE ((uint32_t )0x400)
1243#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
1244#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
1245#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
1246#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
1247#define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
1248#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
1249
1250/**
1251 * @}
1252 */
1253
1254/** @addtogroup Peripheral_declaration
1255 * @{
1256 */
1257#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1258#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1259#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1260#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1261#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1262#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1263#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1264#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1265#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1266#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1267#define RTC ((RTC_TypeDef *) RTC_BASE)
1268#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1269#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1270#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1271#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1272#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
1273#define USART2 ((USART_TypeDef *) USART2_BASE)
1274#define USART3 ((USART_TypeDef *) USART3_BASE)
1275#define UART4 ((USART_TypeDef *) UART4_BASE)
1276#define UART5 ((USART_TypeDef *) UART5_BASE)
1277#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1278#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1279#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1280#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
1281#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1282#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1283#define CEC ((CEC_TypeDef *) CEC_BASE)
1284#define PWR ((PWR_TypeDef *) PWR_BASE)
1285#define DAC ((DAC_TypeDef *) DAC_BASE)
1286#define UART7 ((USART_TypeDef *) UART7_BASE)
1287#define UART8 ((USART_TypeDef *) UART8_BASE)
1288#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1289#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1290#define USART1 ((USART_TypeDef *) USART1_BASE)
1291#define USART6 ((USART_TypeDef *) USART6_BASE)
1292#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1293#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1294#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1295#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1296#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1297#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1298#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1299#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1300#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1301#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1302#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1303#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1304#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1305#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1306#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1307#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1308#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1309#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1310#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1311#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1312#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
1313#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1314#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1315#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1316#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1317#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1318#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1319#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1320#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1321#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1322#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1323#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1324#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1325#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1326#define CRC ((CRC_TypeDef *) CRC_BASE)
1327#define RCC ((RCC_TypeDef *) RCC_BASE)
1328#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1329#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1330#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1331#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1332#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1333#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1334#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1335#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1336#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1337#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1338#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1339#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1340#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1341#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1342#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1343#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1344#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1345#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1346#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1347#define ETH ((ETH_TypeDef *) ETH_BASE)
1348#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1349#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1350#define RNG ((RNG_TypeDef *) RNG_BASE)
1351#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1352#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1353#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1354#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1355#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1356#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1357#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1358#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1359
1360/**
1361 * @}
1362 */
1363
1364/** @addtogroup Exported_constants
1365 * @{
1366 */
1367
1368/** @addtogroup Peripheral_Registers_Bits_Definition
1369* @{
1370*/
1371
1372/******************************************************************************/
1373/* Peripheral Registers_Bits_Definition */
1374/******************************************************************************/
1375
1376/******************************************************************************/
1377/* */
1378/* Analog to Digital Converter */
1379/* */
1380/******************************************************************************/
1381/******************** Bit definition for ADC_SR register ********************/
1382#define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
1383#define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
1384#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
1385#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
1386#define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
1387#define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
1388
1389/******************* Bit definition for ADC_CR1 register ********************/
1390#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1391#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1392#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1393#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1394#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1395#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1396#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
1397#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
1398#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
1399#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
1400#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
1401#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
1402#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
1403#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
1404#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1405#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
1406#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
1407#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
1408#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
1409#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
1410#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
1411#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1412#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1413#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
1414
1415/******************* Bit definition for ADC_CR2 register ********************/
1416#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
1417#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
1418#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
1419#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
1420#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
1421#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
1422#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1423#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
1424#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
1425#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
1426#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
1427#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1428#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1429#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1430#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
1431#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1432#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1433#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1434#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
1435#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
1436#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1437#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
1438#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
1439#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
1440
1441/****************** Bit definition for ADC_SMPR1 register *******************/
1442#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1443#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1444#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1445#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1446#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1447#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
1448#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
1449#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
1450#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1451#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
1452#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
1453#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
1454#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1455#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
1456#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
1457#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
1458#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1459#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
1460#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
1461#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
1462#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1463#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1464#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1465#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1466#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1467#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
1468#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
1469#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
1470#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1471#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
1472#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
1473#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
1474#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1475#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1476#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1477#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
1478
1479/****************** Bit definition for ADC_SMPR2 register *******************/
1480#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1481#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1482#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1483#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1484#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1485#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
1486#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
1487#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
1488#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1489#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
1490#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
1491#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
1492#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1493#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
1494#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
1495#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
1496#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1497#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
1498#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
1499#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
1500#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1501#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1502#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1503#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1504#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1505#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
1506#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
1507#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
1508#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1509#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
1510#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
1511#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
1512#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1513#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1514#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1515#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
1516#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1517#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
1518#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
1519#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
1520
1521/****************** Bit definition for ADC_JOFR1 register *******************/
1522#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
1523
1524/****************** Bit definition for ADC_JOFR2 register *******************/
1525#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
1526
1527/****************** Bit definition for ADC_JOFR3 register *******************/
1528#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
1529
1530/****************** Bit definition for ADC_JOFR4 register *******************/
1531#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
1532
1533/******************* Bit definition for ADC_HTR register ********************/
1534#define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
1535
1536/******************* Bit definition for ADC_LTR register ********************/
1537#define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
1538
1539/******************* Bit definition for ADC_SQR1 register *******************/
1540#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1541#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1542#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1543#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1544#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1545#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1546#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1547#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1548#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1549#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1550#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1551#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1552#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1553#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1554#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1555#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1556#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1557#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1558#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1559#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1560#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1561#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1562#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1563#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1564#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
1565#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1566#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1567#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1568#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
1569
1570/******************* Bit definition for ADC_SQR2 register *******************/
1571#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1572#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1573#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1574#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1575#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1576#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1577#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1578#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1579#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1580#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1581#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1582#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1583#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1584#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1585#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1586#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1587#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1588#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1589#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1590#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1591#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1592#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1593#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1594#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1595#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1596#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1597#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1598#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1599#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
1600#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
1601#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1602#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
1603#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
1604#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
1605#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
1606#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
1607
1608/******************* Bit definition for ADC_SQR3 register *******************/
1609#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1610#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1611#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1612#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1613#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1614#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1615#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1616#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1617#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1618#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1619#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1620#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1621#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1622#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1623#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1624#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1625#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1626#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1627#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1628#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1629#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1630#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1631#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1632#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1633#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1634#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1635#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1636#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1637#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
1638#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
1639#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1640#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
1641#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
1642#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
1643#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
1644#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
1645
1646/******************* Bit definition for ADC_JSQR register *******************/
1647#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1648#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1649#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1650#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1651#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1652#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1653#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1654#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
1655#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
1656#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
1657#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
1658#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
1659#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1660#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
1661#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
1662#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
1663#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
1664#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
1665#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1666#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
1667#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
1668#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
1669#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
1670#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
1671#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
1672#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1673#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1674
1675/******************* Bit definition for ADC_JDR1 register *******************/
1676#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
1677
1678/******************* Bit definition for ADC_JDR2 register *******************/
1679#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
1680
1681/******************* Bit definition for ADC_JDR3 register *******************/
1682#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
1683
1684/******************* Bit definition for ADC_JDR4 register *******************/
1685#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
1686
1687/******************** Bit definition for ADC_DR register ********************/
1688#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
1689#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
1690
1691/******************* Bit definition for ADC_CSR register ********************/
1692#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
1693#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
1694#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
1695#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
1696#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
1697#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
1698#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
1699#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
1700#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
1701#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
1702#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
1703#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
1704#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
1705#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
1706#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
1707#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
1708#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
1709#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
1710
1711/******************* Bit definition for ADC_CCR register ********************/
1712#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1713#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
1714#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
1715#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
1716#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
1717#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
1718#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1719#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
1720#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
1721#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
1722#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
1723#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
1724#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1725#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
1726#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
1727#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
1728#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
1729#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
1730#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
1731#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
1732
1733/******************* Bit definition for ADC_CDR register ********************/
1734#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
1735#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
1736
1737/******************************************************************************/
1738/* */
1739/* Controller Area Network */
1740/* */
1741/******************************************************************************/
1742/*!<CAN control and status registers */
1743/******************* Bit definition for CAN_MCR register ********************/
1744#define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
1745#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
1746#define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
1747#define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
1748#define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
1749#define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
1750#define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
1751#define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
1752#define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
1753
1754/******************* Bit definition for CAN_MSR register ********************/
1755#define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
1756#define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
1757#define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
1758#define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
1759#define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
1760#define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
1761#define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
1762#define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
1763#define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
1764
1765/******************* Bit definition for CAN_TSR register ********************/
1766#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
1767#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
1768#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
1769#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
1770#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
1771#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
1772#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
1773#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
1774#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
1775#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
1776#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
1777#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
1778#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
1779#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
1780#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
1781#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
1782
1783#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
1784#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
1785#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
1786#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
1787
1788#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
1789#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
1790#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
1791#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
1792
1793/******************* Bit definition for CAN_RF0R register *******************/
1794#define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
1795#define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
1796#define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
1797#define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
1798
1799/******************* Bit definition for CAN_RF1R register *******************/
1800#define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
1801#define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
1802#define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
1803#define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
1804
1805/******************** Bit definition for CAN_IER register *******************/
1806#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
1807#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
1808#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
1809#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
1810#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
1811#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
1812#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
1813#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
1814#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
1815#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
1816#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
1817#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
1818#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
1819#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
1820
1821/******************** Bit definition for CAN_ESR register *******************/
1822#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
1823#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
1824#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
1825
1826#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
1827#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
1828#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
1829#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
1830
1831#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
1832#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
1833
1834/******************* Bit definition for CAN_BTR register ********************/
1835#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
1836#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
1837#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
1838#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
1839#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
1840#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
1841#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
1842#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
1843#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
1844#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
1845#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
1846#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
1847#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
1848#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
1849#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
1850
1851/*!<Mailbox registers */
1852/****************** Bit definition for CAN_TI0R register ********************/
1853#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1854#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1855#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1856#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1857#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1858
1859/****************** Bit definition for CAN_TDT0R register *******************/
1860#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1861#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1862#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1863
1864/****************** Bit definition for CAN_TDL0R register *******************/
1865#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1866#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1867#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1868#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1869
1870/****************** Bit definition for CAN_TDH0R register *******************/
1871#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1872#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1873#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1874#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1875
1876/******************* Bit definition for CAN_TI1R register *******************/
1877#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1878#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1879#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1880#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1881#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1882
1883/******************* Bit definition for CAN_TDT1R register ******************/
1884#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1885#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1886#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1887
1888/******************* Bit definition for CAN_TDL1R register ******************/
1889#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1890#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1891#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1892#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1893
1894/******************* Bit definition for CAN_TDH1R register ******************/
1895#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1896#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1897#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1898#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1899
1900/******************* Bit definition for CAN_TI2R register *******************/
1901#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
1902#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1903#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1904#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
1905#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1906
1907/******************* Bit definition for CAN_TDT2R register ******************/
1908#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1909#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
1910#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1911
1912/******************* Bit definition for CAN_TDL2R register ******************/
1913#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1914#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1915#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1916#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1917
1918/******************* Bit definition for CAN_TDH2R register ******************/
1919#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1920#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1921#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1922#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1923
1924/******************* Bit definition for CAN_RI0R register *******************/
1925#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1926#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1927#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
1928#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1929
1930/******************* Bit definition for CAN_RDT0R register ******************/
1931#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1932#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
1933#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1934
1935/******************* Bit definition for CAN_RDL0R register ******************/
1936#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1937#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1938#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1939#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1940
1941/******************* Bit definition for CAN_RDH0R register ******************/
1942#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1943#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1944#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1945#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1946
1947/******************* Bit definition for CAN_RI1R register *******************/
1948#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
1949#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
1950#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
1951#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
1952
1953/******************* Bit definition for CAN_RDT1R register ******************/
1954#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
1955#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
1956#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
1957
1958/******************* Bit definition for CAN_RDL1R register ******************/
1959#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
1960#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
1961#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
1962#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
1963
1964/******************* Bit definition for CAN_RDH1R register ******************/
1965#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
1966#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
1967#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
1968#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
1969
1970/*!<CAN filter registers */
1971/******************* Bit definition for CAN_FMR register ********************/
1972#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
1973#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
1974
1975/******************* Bit definition for CAN_FM1R register *******************/
1976#define CAN_FM1R_FBM ((uint32_t)0x3FFF) /*!<Filter Mode */
1977#define CAN_FM1R_FBM0 ((uint32_t)0x0001) /*!<Filter Init Mode bit 0 */
1978#define CAN_FM1R_FBM1 ((uint32_t)0x0002) /*!<Filter Init Mode bit 1 */
1979#define CAN_FM1R_FBM2 ((uint32_t)0x0004) /*!<Filter Init Mode bit 2 */
1980#define CAN_FM1R_FBM3 ((uint32_t)0x0008) /*!<Filter Init Mode bit 3 */
1981#define CAN_FM1R_FBM4 ((uint32_t)0x0010) /*!<Filter Init Mode bit 4 */
1982#define CAN_FM1R_FBM5 ((uint32_t)0x0020) /*!<Filter Init Mode bit 5 */
1983#define CAN_FM1R_FBM6 ((uint32_t)0x0040) /*!<Filter Init Mode bit 6 */
1984#define CAN_FM1R_FBM7 ((uint32_t)0x0080) /*!<Filter Init Mode bit 7 */
1985#define CAN_FM1R_FBM8 ((uint32_t)0x0100) /*!<Filter Init Mode bit 8 */
1986#define CAN_FM1R_FBM9 ((uint32_t)0x0200) /*!<Filter Init Mode bit 9 */
1987#define CAN_FM1R_FBM10 ((uint32_t)0x0400) /*!<Filter Init Mode bit 10 */
1988#define CAN_FM1R_FBM11 ((uint32_t)0x0800) /*!<Filter Init Mode bit 11 */
1989#define CAN_FM1R_FBM12 ((uint32_t)0x1000) /*!<Filter Init Mode bit 12 */
1990#define CAN_FM1R_FBM13 ((uint32_t)0x2000) /*!<Filter Init Mode bit 13 */
1991
1992/******************* Bit definition for CAN_FS1R register *******************/
1993#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
1994#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
1995#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
1996#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
1997#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
1998#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
1999#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
2000#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
2001#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
2002#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
2003#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
2004#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
2005#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
2006#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
2007#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
2008
2009/****************** Bit definition for CAN_FFA1R register *******************/
2010#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
2011#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
2012#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
2013#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
2014#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
2015#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
2016#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
2017#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
2018#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
2019#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
2020#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
2021#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
2022#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
2023#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
2024#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
2025
2026/******************* Bit definition for CAN_FA1R register *******************/
2027#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
2028#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
2029#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
2030#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
2031#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
2032#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
2033#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
2034#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
2035#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
2036#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
2037#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
2038#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
2039#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
2040#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
2041#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
2042
2043/******************* Bit definition for CAN_F0R1 register *******************/
2044#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2045#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2046#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2047#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2048#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2049#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2050#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2051#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2052#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2053#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2054#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2055#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2056#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2057#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2058#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2059#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2060#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2061#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2062#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2063#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2064#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2065#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2066#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2067#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2068#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2069#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2070#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2071#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2072#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2073#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2074#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2075#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2076
2077/******************* Bit definition for CAN_F1R1 register *******************/
2078#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2079#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2080#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2081#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2082#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2083#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2084#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2085#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2086#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2087#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2088#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2089#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2090#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2091#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2092#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2093#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2094#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2095#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2096#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2097#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2098#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2099#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2100#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2101#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2102#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2103#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2104#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2105#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2106#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2107#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2108#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2109#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2110
2111/******************* Bit definition for CAN_F2R1 register *******************/
2112#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2113#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2114#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2115#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2116#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2117#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2118#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2119#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2120#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2121#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2122#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2123#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2124#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2125#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2126#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2127#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2128#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2129#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2130#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2131#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2132#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2133#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2134#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2135#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2136#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2137#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2138#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2139#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2140#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2141#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2142#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2143#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2144
2145/******************* Bit definition for CAN_F3R1 register *******************/
2146#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2147#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2148#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2149#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2150#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2151#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2152#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2153#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2154#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2155#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2156#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2157#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2158#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2159#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2160#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2161#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2162#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2163#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2164#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2165#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2166#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2167#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2168#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2169#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2170#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2171#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2172#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2173#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2174#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2175#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2176#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2177#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2178
2179/******************* Bit definition for CAN_F4R1 register *******************/
2180#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2181#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2182#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2183#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2184#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2185#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2186#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2187#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2188#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2189#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2190#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2191#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2192#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2193#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2194#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2195#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2196#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2197#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2198#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2199#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2200#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2201#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2202#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2203#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2204#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2205#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2206#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2207#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2208#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2209#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2210#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2211#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2212
2213/******************* Bit definition for CAN_F5R1 register *******************/
2214#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2215#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2216#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2217#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2218#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2219#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2220#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2221#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2222#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2223#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2224#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2225#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2226#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2227#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2228#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2229#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2230#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2231#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2232#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2233#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2234#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2235#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2236#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2237#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2238#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2239#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2240#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2241#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2242#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2243#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2244#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2245#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2246
2247/******************* Bit definition for CAN_F6R1 register *******************/
2248#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2249#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2250#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2251#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2252#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2253#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2254#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2255#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2256#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2257#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2258#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2259#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2260#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2261#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2262#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2263#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2264#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2265#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2266#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2267#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2268#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2269#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2270#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2271#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2272#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2273#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2274#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2275#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2276#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2277#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2278#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2279#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2280
2281/******************* Bit definition for CAN_F7R1 register *******************/
2282#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2283#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2284#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2285#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2286#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2287#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2288#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2289#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2290#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2291#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2292#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2293#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2294#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2295#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2296#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2297#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2298#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2299#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2300#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2301#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2302#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2303#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2304#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2305#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2306#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2307#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2308#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2309#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2310#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2311#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2312#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2313#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2314
2315/******************* Bit definition for CAN_F8R1 register *******************/
2316#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2317#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2318#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2319#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2320#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2321#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2322#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2323#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2324#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2325#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2326#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2327#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2328#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2329#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2330#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2331#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2332#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2333#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2334#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2335#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2336#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2337#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2338#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2339#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2340#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2341#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2342#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2343#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2344#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2345#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2346#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2347#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2348
2349/******************* Bit definition for CAN_F9R1 register *******************/
2350#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2351#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2352#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2353#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2354#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2355#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2356#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2357#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2358#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2359#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2360#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2361#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2362#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2363#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2364#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2365#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2366#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2367#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2368#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2369#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2370#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2371#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2372#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2373#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2374#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2375#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2376#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2377#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2378#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2379#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2380#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2381#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2382
2383/******************* Bit definition for CAN_F10R1 register ******************/
2384#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2385#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2386#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2387#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2388#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2389#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2390#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2391#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2392#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2393#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2394#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2395#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2396#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2397#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2398#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2399#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2400#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2401#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2402#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2403#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2404#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2405#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2406#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2407#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2408#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2409#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2410#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2411#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2412#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2413#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2414#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2415#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2416
2417/******************* Bit definition for CAN_F11R1 register ******************/
2418#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2419#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2420#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2421#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2422#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2423#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2424#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2425#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2426#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2427#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2428#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2429#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2430#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2431#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2432#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2433#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2434#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2435#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2436#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2437#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2438#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2439#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2440#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2441#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2442#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2443#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2444#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2445#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2446#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2447#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2448#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2449#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2450
2451/******************* Bit definition for CAN_F12R1 register ******************/
2452#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2453#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2454#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2455#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2456#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2457#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2458#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2459#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2460#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2461#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2462#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2463#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2464#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2465#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2466#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2467#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2468#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2469#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2470#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2471#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2472#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2473#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2474#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2475#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2476#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2477#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2478#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2479#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2480#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2481#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2482#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2483#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2484
2485/******************* Bit definition for CAN_F13R1 register ******************/
2486#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2487#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2488#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2489#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2490#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2491#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2492#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2493#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2494#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2495#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2496#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2497#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2498#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2499#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2500#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2501#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2502#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2503#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2504#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2505#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2506#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2507#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2508#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2509#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2510#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2511#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2512#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2513#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2514#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2515#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2516#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2517#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2518
2519/******************* Bit definition for CAN_F0R2 register *******************/
2520#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2521#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2522#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2523#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2524#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2525#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2526#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2527#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2528#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2529#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2530#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2531#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2532#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2533#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2534#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2535#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2536#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2537#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2538#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2539#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2540#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2541#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2542#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2543#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2544#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2545#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2546#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2547#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2548#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2549#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2550#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2551#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2552
2553/******************* Bit definition for CAN_F1R2 register *******************/
2554#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2555#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2556#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2557#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2558#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2559#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2560#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2561#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2562#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2563#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2564#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2565#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2566#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2567#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2568#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2569#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2570#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2571#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2572#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2573#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2574#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2575#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2576#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2577#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2578#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2579#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2580#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2581#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2582#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2583#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2584#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2585#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2586
2587/******************* Bit definition for CAN_F2R2 register *******************/
2588#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2589#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2590#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2591#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2592#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2593#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2594#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2595#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2596#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2597#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2598#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2599#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2600#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2601#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2602#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2603#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2604#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2605#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2606#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2607#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2608#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2609#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2610#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2611#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2612#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2613#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2614#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2615#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2616#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2617#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2618#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2619#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2620
2621/******************* Bit definition for CAN_F3R2 register *******************/
2622#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2623#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2624#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2625#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2626#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2627#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2628#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2629#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2630#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2631#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2632#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2633#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2634#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2635#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2636#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2637#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2638#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2639#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2640#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2641#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2642#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2643#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2644#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2645#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2646#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2647#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2648#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2649#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2650#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2651#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2652#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2653#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2654
2655/******************* Bit definition for CAN_F4R2 register *******************/
2656#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2657#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2658#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2659#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2660#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2661#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2662#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2663#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2664#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2665#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2666#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2667#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2668#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2669#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2670#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2671#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2672#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2673#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2674#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2675#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2676#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2677#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2678#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2679#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2680#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2681#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2682#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2683#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2684#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2685#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2686#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2687#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2688
2689/******************* Bit definition for CAN_F5R2 register *******************/
2690#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2691#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2692#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2693#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2694#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2695#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2696#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2697#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2698#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2699#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2700#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2701#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2702#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2703#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2704#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2705#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2706#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2707#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2708#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2709#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2710#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2711#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2712#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2713#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2714#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2715#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2716#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2717#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2718#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2719#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2720#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2721#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2722
2723/******************* Bit definition for CAN_F6R2 register *******************/
2724#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2725#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2726#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2727#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2728#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2729#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2730#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2731#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2732#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2733#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2734#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2735#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2736#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2737#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2738#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2739#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2740#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2741#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2742#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2743#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2744#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2745#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2746#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2747#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2748#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2749#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2750#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2751#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2752#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2753#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2754#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2755#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2756
2757/******************* Bit definition for CAN_F7R2 register *******************/
2758#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2759#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2760#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2761#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2762#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2763#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2764#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2765#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2766#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2767#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2768#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2769#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2770#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2771#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2772#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2773#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2774#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2775#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2776#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2777#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2778#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2779#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2780#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2781#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2782#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2783#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2784#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2785#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2786#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2787#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2788#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2789#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2790
2791/******************* Bit definition for CAN_F8R2 register *******************/
2792#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2793#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2794#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2795#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2796#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2797#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2798#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2799#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2800#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2801#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2802#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2803#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2804#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2805#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2806#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2807#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2808#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2809#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2810#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2811#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2812#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2813#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2814#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2815#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2816#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2817#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2818#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2819#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2820#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2821#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2822#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2823#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2824
2825/******************* Bit definition for CAN_F9R2 register *******************/
2826#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2827#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2828#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2829#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2830#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2831#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2832#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2833#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2834#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2835#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2836#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2837#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2838#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2839#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2840#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2841#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2842#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2843#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2844#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2845#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2846#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2847#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2848#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2849#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2850#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2851#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2852#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2853#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2854#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2855#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2856#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2857#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2858
2859/******************* Bit definition for CAN_F10R2 register ******************/
2860#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2861#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2862#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2863#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2864#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2865#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2866#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2867#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2868#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2869#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2870#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2871#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2872#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2873#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2874#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2875#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2876#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2877#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2878#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2879#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2880#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2881#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2882#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2883#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2884#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2885#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2886#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2887#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2888#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2889#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2890#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2891#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2892
2893/******************* Bit definition for CAN_F11R2 register ******************/
2894#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2895#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2896#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2897#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2898#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2899#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2900#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2901#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2902#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2903#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2904#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2905#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2906#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2907#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2908#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2909#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2910#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2911#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2912#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2913#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2914#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2915#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2916#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2917#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2918#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2919#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2920#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2921#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2922#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2923#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2924#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2925#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2926
2927/******************* Bit definition for CAN_F12R2 register ******************/
2928#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2929#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2930#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2931#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2932#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2933#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2934#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2935#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2936#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2937#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2938#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2939#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2940#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2941#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2942#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2943#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2944#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2945#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2946#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2947#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2948#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2949#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2950#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2951#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2952#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2953#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2954#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2955#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2956#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2957#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2958#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2959#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2960
2961/******************* Bit definition for CAN_F13R2 register ******************/
2962#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2963#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2964#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2965#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2966#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2967#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2968#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2969#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2970#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2971#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2972#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2973#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2974#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2975#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2976#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2977#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2978#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2979#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2980#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2981#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2982#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2983#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2984#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2985#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2986#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2987#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2988#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2989#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2990#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2991#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2992#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2993#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2994
2995/******************************************************************************/
2996/* */
2997/* HDMI-CEC (CEC) */
2998/* */
2999/******************************************************************************/
3000
3001/******************* Bit definition for CEC_CR register *********************/
3002#define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
3003#define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
3004#define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
3005
3006/******************* Bit definition for CEC_CFGR register *******************/
3007#define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
3008#define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
3009#define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
3010#define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
3011#define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Period Error generation */
3012#define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast no Error generation */
3013#define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
3014#define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
3015#define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
3016
3017/******************* Bit definition for CEC_TXDR register *******************/
3018#define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
3019
3020/******************* Bit definition for CEC_RXDR register *******************/
3021#define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
3022
3023/******************* Bit definition for CEC_ISR register ********************/
3024#define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
3025#define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
3026#define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
3027#define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
3028#define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
3029#define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
3030#define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
3031#define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
3032#define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
3033#define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
3034#define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
3035#define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
3036#define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
3037
3038/******************* Bit definition for CEC_IER register ********************/
3039#define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
3040#define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
3041#define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
3042#define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
3043#define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/
3044#define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
3045#define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
3046#define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
3047#define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
3048#define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
3049#define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
3050#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
3051#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
3052
3053/******************************************************************************/
3054/* */
3055/* CRC calculation unit */
3056/* */
3057/******************************************************************************/
3058/******************* Bit definition for CRC_DR register *********************/
3059#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
3060
3061/******************* Bit definition for CRC_IDR register ********************/
3062#define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */
3063
3064/******************** Bit definition for CRC_CR register ********************/
3065#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
3066#define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
3067#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
3068#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
3069#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
3070#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
3071#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
3072#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
3073
3074/******************* Bit definition for CRC_INIT register *******************/
3075#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
3076
3077/******************* Bit definition for CRC_POL register ********************/
3078#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
3079
3080/******************************************************************************/
3081/* */
3082/* Digital to Analog Converter */
3083/* */
3084/******************************************************************************/
3085/******************** Bit definition for DAC_CR register ********************/
3086#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
3087#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
3088#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
3089
3090#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
3091#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
3092#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
3093#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
3094
3095#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
3096#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
3097#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
3098
3099#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
3100#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3101#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3102#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3103#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3104
3105#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
3106#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
3107#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
3108#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
3109
3110#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
3111#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
3112#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
3113#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
3114
3115#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
3116#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
3117#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
3118
3119#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
3120#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3121#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3122#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3123#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3124
3125#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
3126
3127/***************** Bit definition for DAC_SWTRIGR register ******************/
3128#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
3129#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
3130
3131/***************** Bit definition for DAC_DHR12R1 register ******************/
3132#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
3133
3134/***************** Bit definition for DAC_DHR12L1 register ******************/
3135#define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
3136
3137/****************** Bit definition for DAC_DHR8R1 register ******************/
3138#define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
3139
3140/***************** Bit definition for DAC_DHR12R2 register ******************/
3141#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
3142
3143/***************** Bit definition for DAC_DHR12L2 register ******************/
3144#define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
3145
3146/****************** Bit definition for DAC_DHR8R2 register ******************/
3147#define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
3148
3149/***************** Bit definition for DAC_DHR12RD register ******************/
3150#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
3151#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
3152
3153/***************** Bit definition for DAC_DHR12LD register ******************/
3154#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
3155#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
3156
3157/****************** Bit definition for DAC_DHR8RD register ******************/
3158#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
3159#define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
3160
3161/******************* Bit definition for DAC_DOR1 register *******************/
3162#define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
3163
3164/******************* Bit definition for DAC_DOR2 register *******************/
3165#define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
3166
3167/******************** Bit definition for DAC_SR register ********************/
3168#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
3169#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
3170
3171/******************************************************************************/
3172/* */
3173/* Debug MCU */
3174/* */
3175/******************************************************************************/
3176
3177/******************************************************************************/
3178/* */
3179/* DCMI */
3180/* */
3181/******************************************************************************/
3182/******************** Bits definition for DCMI_CR register ******************/
3183#define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
3184#define DCMI_CR_CM ((uint32_t)0x00000002)
3185#define DCMI_CR_CROP ((uint32_t)0x00000004)
3186#define DCMI_CR_JPEG ((uint32_t)0x00000008)
3187#define DCMI_CR_ESS ((uint32_t)0x00000010)
3188#define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
3189#define DCMI_CR_HSPOL ((uint32_t)0x00000040)
3190#define DCMI_CR_VSPOL ((uint32_t)0x00000080)
3191#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
3192#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
3193#define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
3194#define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
3195#define DCMI_CR_CRE ((uint32_t)0x00001000)
3196#define DCMI_CR_ENABLE ((uint32_t)0x00004000)
3197#define DCMI_CR_BSM ((uint32_t)0x00030000)
3198#define DCMI_CR_BSM_0 ((uint32_t)0x00010000)
3199#define DCMI_CR_BSM_1 ((uint32_t)0x00020000)
3200#define DCMI_CR_OEBS ((uint32_t)0x00040000)
3201#define DCMI_CR_LSM ((uint32_t)0x00080000)
3202#define DCMI_CR_OELS ((uint32_t)0x00100000)
3203
3204/******************** Bits definition for DCMI_SR register ******************/
3205#define DCMI_SR_HSYNC ((uint32_t)0x00000001)
3206#define DCMI_SR_VSYNC ((uint32_t)0x00000002)
3207#define DCMI_SR_FNE ((uint32_t)0x00000004)
3208
3209/******************** Bits definition for DCMI_RISR register ****************/
3210#define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
3211#define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
3212#define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
3213#define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
3214#define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
3215
3216/******************** Bits definition for DCMI_IER register *****************/
3217#define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
3218#define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
3219#define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
3220#define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
3221#define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
3222
3223/******************** Bits definition for DCMI_MISR register ****************/
3224#define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
3225#define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
3226#define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
3227#define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
3228#define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
3229
3230/******************** Bits definition for DCMI_ICR register *****************/
3231#define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
3232#define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
3233#define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
3234#define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
3235#define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
3236
3237/******************************************************************************/
3238/* */
3239/* DMA Controller */
3240/* */
3241/******************************************************************************/
3242/******************** Bits definition for DMA_SxCR register *****************/
3243#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
3244#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
3245#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
3246#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
3247#define DMA_SxCR_MBURST ((uint32_t)0x01800000)
3248#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
3249#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
3250#define DMA_SxCR_PBURST ((uint32_t)0x00600000)
3251#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
3252#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
3253#define DMA_SxCR_ACK ((uint32_t)0x00100000)
3254#define DMA_SxCR_CT ((uint32_t)0x00080000)
3255#define DMA_SxCR_DBM ((uint32_t)0x00040000)
3256#define DMA_SxCR_PL ((uint32_t)0x00030000)
3257#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
3258#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
3259#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
3260#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
3261#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
3262#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
3263#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
3264#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
3265#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
3266#define DMA_SxCR_MINC ((uint32_t)0x00000400)
3267#define DMA_SxCR_PINC ((uint32_t)0x00000200)
3268#define DMA_SxCR_CIRC ((uint32_t)0x00000100)
3269#define DMA_SxCR_DIR ((uint32_t)0x000000C0)
3270#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
3271#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
3272#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
3273#define DMA_SxCR_TCIE ((uint32_t)0x00000010)
3274#define DMA_SxCR_HTIE ((uint32_t)0x00000008)
3275#define DMA_SxCR_TEIE ((uint32_t)0x00000004)
3276#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
3277#define DMA_SxCR_EN ((uint32_t)0x00000001)
3278
3279/******************** Bits definition for DMA_SxCNDTR register **************/
3280#define DMA_SxNDT ((uint32_t)0x0000FFFF)
3281#define DMA_SxNDT_0 ((uint32_t)0x00000001)
3282#define DMA_SxNDT_1 ((uint32_t)0x00000002)
3283#define DMA_SxNDT_2 ((uint32_t)0x00000004)
3284#define DMA_SxNDT_3 ((uint32_t)0x00000008)
3285#define DMA_SxNDT_4 ((uint32_t)0x00000010)
3286#define DMA_SxNDT_5 ((uint32_t)0x00000020)
3287#define DMA_SxNDT_6 ((uint32_t)0x00000040)
3288#define DMA_SxNDT_7 ((uint32_t)0x00000080)
3289#define DMA_SxNDT_8 ((uint32_t)0x00000100)
3290#define DMA_SxNDT_9 ((uint32_t)0x00000200)
3291#define DMA_SxNDT_10 ((uint32_t)0x00000400)
3292#define DMA_SxNDT_11 ((uint32_t)0x00000800)
3293#define DMA_SxNDT_12 ((uint32_t)0x00001000)
3294#define DMA_SxNDT_13 ((uint32_t)0x00002000)
3295#define DMA_SxNDT_14 ((uint32_t)0x00004000)
3296#define DMA_SxNDT_15 ((uint32_t)0x00008000)
3297
3298/******************** Bits definition for DMA_SxFCR register ****************/
3299#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
3300#define DMA_SxFCR_FS ((uint32_t)0x00000038)
3301#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
3302#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
3303#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
3304#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
3305#define DMA_SxFCR_FTH ((uint32_t)0x00000003)
3306#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
3307#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
3308
3309/******************** Bits definition for DMA_LISR register *****************/
3310#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
3311#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
3312#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
3313#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
3314#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
3315#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
3316#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
3317#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
3318#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
3319#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
3320#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
3321#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
3322#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
3323#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
3324#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
3325#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
3326#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
3327#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
3328#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
3329#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
3330
3331/******************** Bits definition for DMA_HISR register *****************/
3332#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
3333#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
3334#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
3335#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
3336#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
3337#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
3338#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
3339#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
3340#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
3341#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
3342#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
3343#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
3344#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
3345#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
3346#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
3347#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
3348#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
3349#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
3350#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
3351#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
3352
3353/******************** Bits definition for DMA_LIFCR register ****************/
3354#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
3355#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
3356#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
3357#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
3358#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
3359#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
3360#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
3361#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
3362#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
3363#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
3364#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
3365#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
3366#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
3367#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
3368#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
3369#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
3370#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
3371#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
3372#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
3373#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
3374
3375/******************** Bits definition for DMA_HIFCR register ****************/
3376#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
3377#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
3378#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
3379#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
3380#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
3381#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
3382#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
3383#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
3384#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
3385#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
3386#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
3387#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
3388#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
3389#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
3390#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
3391#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
3392#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
3393#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
3394#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
3395#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
3396
3397/******************************************************************************/
3398/* */
3399/* AHB Master DMA2D Controller (DMA2D) */
3400/* */
3401/******************************************************************************/
3402
3403/******************** Bit definition for DMA2D_CR register ******************/
3404
3405#define DMA2D_CR_START ((uint32_t)0x00000001) /*!< Start transfer */
3406#define DMA2D_CR_SUSP ((uint32_t)0x00000002) /*!< Suspend transfer */
3407#define DMA2D_CR_ABORT ((uint32_t)0x00000004) /*!< Abort transfer */
3408#define DMA2D_CR_TEIE ((uint32_t)0x00000100) /*!< Transfer Error Interrupt Enable */
3409#define DMA2D_CR_TCIE ((uint32_t)0x00000200) /*!< Transfer Complete Interrupt Enable */
3410#define DMA2D_CR_TWIE ((uint32_t)0x00000400) /*!< Transfer Watermark Interrupt Enable */
3411#define DMA2D_CR_CAEIE ((uint32_t)0x00000800) /*!< CLUT Access Error Interrupt Enable */
3412#define DMA2D_CR_CTCIE ((uint32_t)0x00001000) /*!< CLUT Transfer Complete Interrupt Enable */
3413#define DMA2D_CR_CEIE ((uint32_t)0x00002000) /*!< Configuration Error Interrupt Enable */
3414#define DMA2D_CR_MODE ((uint32_t)0x00030000) /*!< DMA2D Mode */
3415
3416/******************** Bit definition for DMA2D_ISR register *****************/
3417
3418#define DMA2D_ISR_TEIF ((uint32_t)0x00000001) /*!< Transfer Error Interrupt Flag */
3419#define DMA2D_ISR_TCIF ((uint32_t)0x00000002) /*!< Transfer Complete Interrupt Flag */
3420#define DMA2D_ISR_TWIF ((uint32_t)0x00000004) /*!< Transfer Watermark Interrupt Flag */
3421#define DMA2D_ISR_CAEIF ((uint32_t)0x00000008) /*!< CLUT Access Error Interrupt Flag */
3422#define DMA2D_ISR_CTCIF ((uint32_t)0x00000010) /*!< CLUT Transfer Complete Interrupt Flag */
3423#define DMA2D_ISR_CEIF ((uint32_t)0x00000020) /*!< Configuration Error Interrupt Flag */
3424
3425/******************** Bit definition for DMA2D_IFSR register ****************/
3426
3427#define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001) /*!< Clears Transfer Error Interrupt Flag */
3428#define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002) /*!< Clears Transfer Complete Interrupt Flag */
3429#define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004) /*!< Clears Transfer Watermark Interrupt Flag */
3430#define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008) /*!< Clears CLUT Access Error Interrupt Flag */
3431#define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010) /*!< Clears CLUT Transfer Complete Interrupt Flag */
3432#define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020) /*!< Clears Configuration Error Interrupt Flag */
3433
3434/******************** Bit definition for DMA2D_FGMAR register ***************/
3435
3436#define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
3437
3438/******************** Bit definition for DMA2D_FGOR register ****************/
3439
3440#define DMA2D_FGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
3441
3442/******************** Bit definition for DMA2D_BGMAR register ***************/
3443
3444#define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
3445
3446/******************** Bit definition for DMA2D_BGOR register ****************/
3447
3448#define DMA2D_BGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
3449
3450/******************** Bit definition for DMA2D_FGPFCCR register *************/
3451
3452#define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
3453#define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
3454#define DMA2D_FGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
3455#define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
3456#define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha mode */
3457#define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
3458
3459/******************** Bit definition for DMA2D_FGCOLR register **************/
3460
3461#define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
3462#define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
3463#define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
3464
3465/******************** Bit definition for DMA2D_BGPFCCR register *************/
3466
3467#define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
3468#define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
3469#define DMA2D_BGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
3470#define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
3471#define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha Mode */
3472#define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
3473
3474/******************** Bit definition for DMA2D_BGCOLR register **************/
3475
3476#define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
3477#define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
3478#define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
3479
3480/******************** Bit definition for DMA2D_FGCMAR register **************/
3481
3482#define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
3483
3484/******************** Bit definition for DMA2D_BGCMAR register **************/
3485
3486#define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
3487
3488/******************** Bit definition for DMA2D_OPFCCR register **************/
3489
3490#define DMA2D_OPFCCR_CM ((uint32_t)0x00000007) /*!< Color mode */
3491
3492/******************** Bit definition for DMA2D_OCOLR register ***************/
3493
3494/*!<Mode_ARGB8888/RGB888 */
3495
3496#define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) /*!< BLUE Value */
3497#define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) /*!< GREEN Value */
3498#define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) /*!< Red Value */
3499#define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /*!< Alpha Channel Value */
3500
3501/*!<Mode_RGB565 */
3502#define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) /*!< BLUE Value */
3503#define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) /*!< GREEN Value */
3504#define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) /*!< Red Value */
3505
3506/*!<Mode_ARGB1555 */
3507#define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) /*!< BLUE Value */
3508#define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) /*!< GREEN Value */
3509#define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) /*!< Red Value */
3510#define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) /*!< Alpha Channel Value */
3511
3512/*!<Mode_ARGB4444 */
3513#define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) /*!< BLUE Value */
3514#define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) /*!< GREEN Value */
3515#define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) /*!< Red Value */
3516#define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) /*!< Alpha Channel Value */
3517
3518/******************** Bit definition for DMA2D_OMAR register ****************/
3519
3520#define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
3521
3522/******************** Bit definition for DMA2D_OOR register *****************/
3523
3524#define DMA2D_OOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
3525
3526/******************** Bit definition for DMA2D_NLR register *****************/
3527
3528#define DMA2D_NLR_NL ((uint32_t)0x0000FFFF) /*!< Number of Lines */
3529#define DMA2D_NLR_PL ((uint32_t)0x3FFF0000) /*!< Pixel per Lines */
3530
3531/******************** Bit definition for DMA2D_LWR register *****************/
3532
3533#define DMA2D_LWR_LW ((uint32_t)0x0000FFFF) /*!< Line Watermark */
3534
3535/******************** Bit definition for DMA2D_AMTCR register ***************/
3536
3537#define DMA2D_AMTCR_EN ((uint32_t)0x00000001) /*!< Enable */
3538#define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) /*!< Dead Time */
3539
3540
3541
3542/******************** Bit definition for DMA2D_FGCLUT register **************/
3543
3544/******************** Bit definition for DMA2D_BGCLUT register **************/
3545
3546
3547/******************************************************************************/
3548/* */
3549/* External Interrupt/Event Controller */
3550/* */
3551/******************************************************************************/
3552/******************* Bit definition for EXTI_IMR register *******************/
3553#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
3554#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
3555#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
3556#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
3557#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
3558#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
3559#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
3560#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
3561#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
3562#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
3563#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
3564#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
3565#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
3566#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
3567#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
3568#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
3569#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
3570#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
3571#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
3572#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
3573#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
3574#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
3575#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
3576#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
3577
3578/******************* Bit definition for EXTI_EMR register *******************/
3579#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
3580#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
3581#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
3582#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
3583#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
3584#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
3585#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
3586#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
3587#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
3588#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
3589#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
3590#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
3591#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
3592#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
3593#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
3594#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
3595#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
3596#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
3597#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
3598#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
3599#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
3600#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
3601#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
3602#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
3603
3604/****************** Bit definition for EXTI_RTSR register *******************/
3605#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
3606#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
3607#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
3608#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
3609#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
3610#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
3611#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
3612#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
3613#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
3614#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
3615#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
3616#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
3617#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
3618#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
3619#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
3620#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
3621#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
3622#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
3623#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
3624#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
3625#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
3626#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
3627#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
3628#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
3629
3630/****************** Bit definition for EXTI_FTSR register *******************/
3631#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
3632#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
3633#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
3634#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
3635#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
3636#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
3637#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
3638#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
3639#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
3640#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
3641#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
3642#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
3643#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
3644#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
3645#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
3646#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
3647#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
3648#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
3649#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
3650#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
3651#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
3652#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
3653#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
3654#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
3655
3656/****************** Bit definition for EXTI_SWIER register ******************/
3657#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
3658#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
3659#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
3660#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
3661#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
3662#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
3663#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
3664#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
3665#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
3666#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
3667#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
3668#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
3669#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
3670#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
3671#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
3672#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
3673#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
3674#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
3675#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
3676#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
3677#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
3678#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
3679#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
3680#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
3681
3682/******************* Bit definition for EXTI_PR register ********************/
3683#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
3684#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
3685#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
3686#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
3687#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
3688#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
3689#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
3690#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
3691#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
3692#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
3693#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
3694#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
3695#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
3696#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
3697#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
3698#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
3699#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
3700#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
3701#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
3702#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
3703#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
3704#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
3705#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
3706#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
3707
3708/******************************************************************************/
3709/* */
3710/* FLASH */
3711/* */
3712/******************************************************************************/
3713/******************* Bits definition for FLASH_ACR register *****************/
3714#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
3715#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
3716#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
3717#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
3718#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
3719#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
3720#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
3721#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
3722#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
3723#define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)
3724#define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)
3725#define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)
3726#define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)
3727#define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)
3728#define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)
3729#define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)
3730#define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)
3731#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
3732#define FLASH_ACR_ARTEN ((uint32_t)0x00000200)
3733#define FLASH_ACR_ARTRST ((uint32_t)0x00000800)
3734
3735/******************* Bits definition for FLASH_SR register ******************/
3736#define FLASH_SR_EOP ((uint32_t)0x00000001)
3737#define FLASH_SR_OPERR ((uint32_t)0x00000002)
3738#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
3739#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
3740#define FLASH_SR_PGPERR ((uint32_t)0x00000040)
3741#define FLASH_SR_ERSERR ((uint32_t)0x00000080)
3742#define FLASH_SR_BSY ((uint32_t)0x00010000)
3743
3744/******************* Bits definition for FLASH_CR register ******************/
3745#define FLASH_CR_PG ((uint32_t)0x00000001)
3746#define FLASH_CR_SER ((uint32_t)0x00000002)
3747#define FLASH_CR_MER ((uint32_t)0x00000004)
3748#define FLASH_CR_SNB ((uint32_t)0x00000078)
3749#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
3750#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
3751#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
3752#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
3753#define FLASH_CR_PSIZE ((uint32_t)0x00000300)
3754#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
3755#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
3756#define FLASH_CR_STRT ((uint32_t)0x00010000)
3757#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
3758#define FLASH_CR_ERRIE ((uint32_t)0x02000000)
3759#define FLASH_CR_LOCK ((uint32_t)0x80000000)
3760
3761/******************* Bits definition for FLASH_OPTCR register ***************/
3762#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
3763#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
3764#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
3765#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
3766#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
3767#define FLASH_OPTCR_WWDG_SW ((uint32_t)0x00000010)
3768#define FLASH_OPTCR_IWDG_SW ((uint32_t)0x00000020)
3769#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
3770#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
3771#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
3772#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
3773#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
3774#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
3775#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
3776#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
3777#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
3778#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
3779#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
3780#define FLASH_OPTCR_nWRP ((uint32_t)0x00FF0000)
3781#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
3782#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
3783#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
3784#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
3785#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
3786#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
3787#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
3788#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
3789#define FLASH_OPTCR_IWDG_STDBY ((uint32_t)0x40000000)
3790#define FLASH_OPTCR_IWDG_STOP ((uint32_t)0x80000000)
3791
3792/******************* Bits definition for FLASH_OPTCR1 register ***************/
3793#define FLASH_OPTCR1_BOOT_ADD0 ((uint32_t)0x0000FFFF)
3794#define FLASH_OPTCR1_BOOT_ADD1 ((uint32_t)0xFFFF0000)
3795
3796
3797
3798/******************************************************************************/
3799/* */
3800/* Flexible Memory Controller */
3801/* */
3802/******************************************************************************/
3803/****************** Bit definition for FMC_BCR1 register *******************/
3804#define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3805#define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3806
3807#define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3808#define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3809#define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3810
3811#define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3812#define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3813#define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3814
3815#define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3816#define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3817#define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3818#define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3819#define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3820#define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3821#define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3822#define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3823#define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3824#define FMC_BCR1_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
3825#define FMC_BCR1_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3826#define FMC_BCR1_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3827#define FMC_BCR1_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3828#define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3829#define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */
3830#define FMC_BCR1_WFDIS ((uint32_t)0x00200000) /*!<Write FIFO Disable */
3831
3832/****************** Bit definition for FMC_BCR2 register *******************/
3833#define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3834#define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3835
3836#define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3837#define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3838#define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3839
3840#define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3841#define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3842#define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3843
3844#define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3845#define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3846#define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3847#define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3848#define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3849#define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3850#define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3851#define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3852#define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3853#define FMC_BCR2_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
3854#define FMC_BCR2_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3855#define FMC_BCR2_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3856#define FMC_BCR2_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3857#define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3858
3859/****************** Bit definition for FMC_BCR3 register *******************/
3860#define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3861#define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3862
3863#define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3864#define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3865#define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3866
3867#define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3868#define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3869#define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3870
3871#define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3872#define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3873#define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3874#define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3875#define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3876#define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3877#define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3878#define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3879#define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3880#define FMC_BCR3_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
3881#define FMC_BCR3_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3882#define FMC_BCR3_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3883#define FMC_BCR3_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3884#define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3885
3886/****************** Bit definition for FMC_BCR4 register *******************/
3887#define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
3888#define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
3889
3890#define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
3891#define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
3892#define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
3893
3894#define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
3895#define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3896#define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3897
3898#define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
3899#define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
3900#define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
3901#define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
3902#define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
3903#define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
3904#define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
3905#define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
3906#define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
3907#define FMC_BCR4_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
3908#define FMC_BCR4_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3909#define FMC_BCR4_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3910#define FMC_BCR4_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3911#define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
3912
3913/****************** Bit definition for FMC_BTR1 register ******************/
3914#define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3915#define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3916#define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3917#define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3918#define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3919
3920#define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3921#define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3922#define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3923#define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3924#define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3925
3926#define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3927#define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3928#define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3929#define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3930#define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3931#define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3932#define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3933#define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3934#define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3935
3936#define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3937#define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3938#define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3939#define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3940#define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3941
3942#define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3943#define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3944#define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3945#define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3946#define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3947
3948#define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3949#define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3950#define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3951#define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3952#define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3953
3954#define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
3955#define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3956#define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3957
3958/****************** Bit definition for FMC_BTR2 register *******************/
3959#define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
3960#define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3961#define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3962#define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3963#define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3964
3965#define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
3966#define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
3967#define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
3968#define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
3969#define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
3970
3971#define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
3972#define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3973#define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3974#define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3975#define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3976#define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3977#define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
3978#define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
3979#define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
3980
3981#define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
3982#define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
3983#define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
3984#define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
3985#define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
3986
3987#define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
3988#define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
3989#define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
3990#define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
3991#define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
3992
3993#define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
3994#define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3995#define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3996#define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3997#define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3998
3999#define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4000#define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4001#define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4002
4003/******************* Bit definition for FMC_BTR3 register *******************/
4004#define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4005#define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4006#define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4007#define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4008#define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4009
4010#define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4011#define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4012#define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4013#define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4014#define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4015
4016#define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4017#define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4018#define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4019#define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4020#define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4021#define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4022#define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4023#define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4024#define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4025
4026#define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4027#define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4028#define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4029#define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4030#define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4031
4032#define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4033#define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4034#define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4035#define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4036#define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4037
4038#define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4039#define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4040#define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4041#define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4042#define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4043
4044#define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4045#define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4046#define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4047
4048/****************** Bit definition for FMC_BTR4 register *******************/
4049#define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4050#define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4051#define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4052#define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4053#define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4054
4055#define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4056#define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4057#define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4058#define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4059#define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4060
4061#define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4062#define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4063#define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4064#define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4065#define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4066#define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4067#define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4068#define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4069#define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4070
4071#define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4072#define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4073#define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4074#define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4075#define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4076
4077#define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
4078#define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4079#define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4080#define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4081#define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
4082
4083#define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
4084#define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4085#define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4086#define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4087#define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4088
4089#define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4090#define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4091#define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4092
4093/****************** Bit definition for FMC_BWTR1 register ******************/
4094#define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4095#define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4096#define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4097#define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4098#define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4099
4100#define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4101#define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4102#define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4103#define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4104#define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4105
4106#define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4107#define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4108#define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4109#define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4110#define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4111#define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4112#define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4113#define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4114#define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4115
4116#define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4117#define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4118#define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4119#define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4120#define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4121
4122#define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4123#define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4124#define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4125
4126/****************** Bit definition for FMC_BWTR2 register ******************/
4127#define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4128#define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4129#define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4130#define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4131#define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4132
4133#define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4134#define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4135#define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4136#define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4137#define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4138
4139#define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4140#define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4141#define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4142#define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4143#define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4144#define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4145#define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4146#define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4147#define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4148
4149#define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4150#define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4151#define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4152#define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4153#define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4154
4155#define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4156#define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4157#define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4158
4159/****************** Bit definition for FMC_BWTR3 register ******************/
4160#define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4161#define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4162#define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4163#define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4164#define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4165
4166#define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4167#define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4168#define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4169#define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4170#define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4171
4172#define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4173#define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4174#define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4175#define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4176#define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4177#define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4178#define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4179#define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4180#define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4181
4182#define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4183#define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4184#define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4185#define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4186#define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4187
4188#define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4189#define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4190#define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4191
4192/****************** Bit definition for FMC_BWTR4 register ******************/
4193#define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
4194#define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4195#define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4196#define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4197#define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4198
4199#define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
4200#define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4201#define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4202#define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4203#define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4204
4205#define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
4206#define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4207#define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4208#define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4209#define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4210#define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4211#define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4212#define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4213#define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4214
4215#define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
4216#define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4217#define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4218#define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4219#define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4220
4221#define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
4222#define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
4223#define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
4224
4225/****************** Bit definition for FMC_PCR register *******************/
4226#define FMC_PCR_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
4227#define FMC_PCR_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
4228#define FMC_PCR_PTYP ((uint32_t)0x00000008) /*!<Memory type */
4229
4230#define FMC_PCR_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
4231#define FMC_PCR_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4232#define FMC_PCR_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4233
4234#define FMC_PCR_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
4235
4236#define FMC_PCR_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
4237#define FMC_PCR_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
4238#define FMC_PCR_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
4239#define FMC_PCR_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
4240#define FMC_PCR_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
4241
4242#define FMC_PCR_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
4243#define FMC_PCR_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
4244#define FMC_PCR_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
4245#define FMC_PCR_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
4246#define FMC_PCR_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
4247
4248#define FMC_PCR_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
4249#define FMC_PCR_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
4250#define FMC_PCR_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
4251#define FMC_PCR_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
4252
4253/******************* Bit definition for FMC_SR register *******************/
4254#define FMC_SR_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
4255#define FMC_SR_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
4256#define FMC_SR_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
4257#define FMC_SR_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
4258#define FMC_SR_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
4259#define FMC_SR_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
4260#define FMC_SR_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
4261
4262/****************** Bit definition for FMC_PMEM register ******************/
4263#define FMC_PMEM_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
4264#define FMC_PMEM_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4265#define FMC_PMEM_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4266#define FMC_PMEM_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4267#define FMC_PMEM_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4268#define FMC_PMEM_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4269#define FMC_PMEM_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4270#define FMC_PMEM_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4271#define FMC_PMEM_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4272
4273#define FMC_PMEM_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
4274#define FMC_PMEM_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4275#define FMC_PMEM_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4276#define FMC_PMEM_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4277#define FMC_PMEM_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4278#define FMC_PMEM_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4279#define FMC_PMEM_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4280#define FMC_PMEM_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4281#define FMC_PMEM_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4282
4283#define FMC_PMEM_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
4284#define FMC_PMEM_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4285#define FMC_PMEM_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4286#define FMC_PMEM_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4287#define FMC_PMEM_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4288#define FMC_PMEM_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4289#define FMC_PMEM_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4290#define FMC_PMEM_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4291#define FMC_PMEM_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4292
4293#define FMC_PMEM_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
4294#define FMC_PMEM_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4295#define FMC_PMEM_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4296#define FMC_PMEM_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4297#define FMC_PMEM_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4298#define FMC_PMEM_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4299#define FMC_PMEM_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4300#define FMC_PMEM_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4301#define FMC_PMEM_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4302
4303/****************** Bit definition for FMC_PATT register ******************/
4304#define FMC_PATT_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
4305#define FMC_PATT_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4306#define FMC_PATT_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4307#define FMC_PATT_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4308#define FMC_PATT_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4309#define FMC_PATT_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
4310#define FMC_PATT_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
4311#define FMC_PATT_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
4312#define FMC_PATT_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
4313
4314#define FMC_PATT_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
4315#define FMC_PATT_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4316#define FMC_PATT_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4317#define FMC_PATT_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4318#define FMC_PATT_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4319#define FMC_PATT_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
4320#define FMC_PATT_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
4321#define FMC_PATT_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
4322#define FMC_PATT_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
4323
4324#define FMC_PATT_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
4325#define FMC_PATT_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4326#define FMC_PATT_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4327#define FMC_PATT_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4328#define FMC_PATT_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
4329#define FMC_PATT_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
4330#define FMC_PATT_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
4331#define FMC_PATT_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
4332#define FMC_PATT_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
4333
4334#define FMC_PATT_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
4335#define FMC_PATT_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4336#define FMC_PATT_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4337#define FMC_PATT_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4338#define FMC_PATT_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
4339#define FMC_PATT_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
4340#define FMC_PATT_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
4341#define FMC_PATT_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
4342#define FMC_PATT_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
4343
4344/****************** Bit definition for FMC_ECCR register ******************/
4345#define FMC_ECCR_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
4346
4347/****************** Bit definition for FMC_SDCR1 register ******************/
4348#define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
4349#define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4350#define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4351
4352#define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
4353#define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4354#define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4355
4356#define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
4357#define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4358#define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4359
4360#define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
4361
4362#define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
4363#define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
4364#define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
4365
4366#define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */
4367
4368#define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */
4369#define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
4370#define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
4371
4372#define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */
4373
4374#define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */
4375#define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
4376#define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
4377
4378/****************** Bit definition for FMC_SDCR2 register ******************/
4379#define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
4380#define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4381#define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4382
4383#define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
4384#define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
4385#define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
4386
4387#define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
4388#define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4389#define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4390
4391#define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
4392
4393#define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
4394#define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
4395#define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
4396
4397#define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */
4398
4399#define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */
4400#define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
4401#define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
4402
4403#define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */
4404
4405#define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */
4406#define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
4407#define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
4408
4409/****************** Bit definition for FMC_SDTR1 register ******************/
4410#define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
4411#define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4412#define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4413#define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4414#define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4415
4416#define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
4417#define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4418#define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4419#define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4420#define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4421
4422#define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
4423#define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4424#define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4425#define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4426#define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4427
4428#define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
4429#define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4430#define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4431#define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
4432
4433#define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
4434#define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4435#define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4436#define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4437
4438#define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
4439#define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4440#define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4441#define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4442
4443#define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
4444#define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4445#define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4446#define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4447
4448/****************** Bit definition for FMC_SDTR2 register ******************/
4449#define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
4450#define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4451#define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4452#define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
4453#define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
4454
4455#define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
4456#define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
4457#define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
4458#define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
4459#define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
4460
4461#define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
4462#define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
4463#define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
4464#define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
4465#define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
4466
4467#define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
4468#define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
4469#define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
4470#define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
4471
4472#define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
4473#define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
4474#define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
4475#define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
4476
4477#define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
4478#define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
4479#define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
4480#define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
4481
4482#define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
4483#define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
4484#define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
4485#define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
4486
4487/****************** Bit definition for FMC_SDCMR register ******************/
4488#define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
4489#define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
4490#define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
4491#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */
4492
4493#define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
4494
4495#define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */
4496
4497#define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */
4498#define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
4499#define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
4500#define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
4501#define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */
4502
4503#define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */
4504
4505/****************** Bit definition for FMC_SDRTR register ******************/
4506#define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */
4507
4508#define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */
4509
4510#define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */
4511
4512/****************** Bit definition for FMC_SDSR register ******************/
4513#define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */
4514
4515#define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */
4516#define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */
4517#define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */
4518
4519#define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */
4520#define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */
4521#define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */
4522
4523#define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */
4524
4525/******************************************************************************/
4526/* */
4527/* General Purpose I/O */
4528/* */
4529/******************************************************************************/
4530/****************** Bits definition for GPIO_MODER register *****************/
4531#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
4532#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
4533#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
4534
4535#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
4536#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
4537#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
4538
4539#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
4540#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
4541#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
4542
4543#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
4544#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
4545#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
4546
4547#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
4548#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
4549#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
4550
4551#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
4552#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
4553#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
4554
4555#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
4556#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
4557#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
4558
4559#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
4560#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
4561#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
4562
4563#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
4564#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
4565#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
4566
4567#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
4568#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
4569#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
4570
4571#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
4572#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
4573#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
4574
4575#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
4576#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
4577#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
4578
4579#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
4580#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
4581#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
4582
4583#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
4584#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
4585#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
4586
4587#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
4588#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
4589#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
4590
4591#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
4592#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
4593#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
4594
4595/****************** Bits definition for GPIO_OTYPER register ****************/
4596#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
4597#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
4598#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
4599#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
4600#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
4601#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
4602#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
4603#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
4604#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
4605#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
4606#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
4607#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
4608#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
4609#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
4610#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
4611#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
4612
4613/****************** Bits definition for GPIO_OSPEEDR register ***************/
4614#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
4615#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
4616#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
4617
4618#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
4619#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
4620#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
4621
4622#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
4623#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
4624#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
4625
4626#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
4627#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
4628#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
4629
4630#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
4631#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
4632#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
4633
4634#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
4635#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
4636#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
4637
4638#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
4639#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
4640#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
4641
4642#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
4643#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
4644#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
4645
4646#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
4647#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
4648#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
4649
4650#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
4651#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
4652#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
4653
4654#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
4655#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
4656#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
4657
4658#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
4659#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
4660#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
4661
4662#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
4663#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
4664#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
4665
4666#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
4667#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
4668#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
4669
4670#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
4671#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
4672#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
4673
4674#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
4675#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
4676#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
4677
4678/****************** Bits definition for GPIO_PUPDR register *****************/
4679#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
4680#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
4681#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
4682
4683#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
4684#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
4685#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
4686
4687#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
4688#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
4689#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
4690
4691#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
4692#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
4693#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
4694
4695#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
4696#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
4697#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
4698
4699#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
4700#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
4701#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
4702
4703#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
4704#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
4705#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
4706
4707#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
4708#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
4709#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
4710
4711#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
4712#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
4713#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
4714
4715#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
4716#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
4717#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
4718
4719#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
4720#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
4721#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
4722
4723#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
4724#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
4725#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
4726
4727#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
4728#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
4729#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
4730
4731#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
4732#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
4733#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
4734
4735#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
4736#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
4737#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
4738
4739#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
4740#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
4741#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
4742
4743/****************** Bits definition for GPIO_IDR register *******************/
4744#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
4745#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
4746#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
4747#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
4748#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
4749#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
4750#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
4751#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
4752#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
4753#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
4754#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
4755#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
4756#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
4757#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
4758#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
4759#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
4760
4761/****************** Bits definition for GPIO_ODR register *******************/
4762#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
4763#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
4764#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
4765#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
4766#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
4767#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
4768#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
4769#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
4770#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
4771#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
4772#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
4773#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
4774#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
4775#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
4776#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
4777#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
4778
4779/****************** Bits definition for GPIO_BSRR register ******************/
4780#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
4781#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
4782#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
4783#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
4784#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
4785#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
4786#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
4787#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
4788#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
4789#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
4790#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
4791#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
4792#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
4793#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
4794#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
4795#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
4796#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
4797#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
4798#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
4799#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
4800#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
4801#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
4802#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
4803#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
4804#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
4805#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
4806#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
4807#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
4808#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
4809#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
4810#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
4811#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
4812
4813/****************** Bit definition for GPIO_LCKR register *********************/
4814#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
4815#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
4816#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
4817#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
4818#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
4819#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
4820#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
4821#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
4822#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
4823#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
4824#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
4825#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
4826#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
4827#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
4828#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
4829#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
4830#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
4831
4832/******************************************************************************/
4833/* */
4834/* Inter-integrated Circuit Interface (I2C) */
4835/* */
4836/******************************************************************************/
4837/******************* Bit definition for I2C_CR1 register *******************/
4838#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
4839#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
4840#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
4841#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
4842#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
4843#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
4844#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
4845#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
4846#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
4847#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
4848#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
4849#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
4850#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
4851#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
4852#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
4853#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
4854#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
4855#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
4856#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
4857#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
4858#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
4859
4860/****************** Bit definition for I2C_CR2 register ********************/
4861#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
4862#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
4863#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
4864#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
4865#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
4866#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
4867#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
4868#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
4869#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
4870#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
4871#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
4872
4873/******************* Bit definition for I2C_OAR1 register ******************/
4874#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
4875#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
4876#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
4877
4878/******************* Bit definition for I2C_OAR2 register ******************/
4879#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
4880#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
4881#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
4882#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
4883#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
4884#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
4885#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
4886#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
4887#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
4888#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
4889#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
4890
4891/******************* Bit definition for I2C_TIMINGR register *******************/
4892#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
4893#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
4894#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
4895#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
4896#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
4897
4898/******************* Bit definition for I2C_TIMEOUTR register *******************/
4899#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
4900#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
4901#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
4902#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B */
4903#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
4904
4905/****************** Bit definition for I2C_ISR register *********************/
4906#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
4907#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
4908#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
4909#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode) */
4910#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
4911#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
4912#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
4913#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
4914#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
4915#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
4916#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
4917#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
4918#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
4919#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
4920#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
4921#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
4922#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
4923
4924/****************** Bit definition for I2C_ICR register *********************/
4925#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
4926#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
4927#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
4928#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
4929#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
4930#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
4931#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
4932#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
4933#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
4934
4935/****************** Bit definition for I2C_PECR register *********************/
4936#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
4937
4938/****************** Bit definition for I2C_RXDR register *********************/
4939#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
4940
4941/****************** Bit definition for I2C_TXDR register *********************/
4942#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
4943
4944
4945/******************************************************************************/
4946/* */
4947/* Independent WATCHDOG */
4948/* */
4949/******************************************************************************/
4950/******************* Bit definition for IWDG_KR register ********************/
4951#define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
4952
4953/******************* Bit definition for IWDG_PR register ********************/
4954#define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
4955#define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
4956#define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
4957#define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
4958
4959/******************* Bit definition for IWDG_RLR register *******************/
4960#define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
4961
4962/******************* Bit definition for IWDG_SR register ********************/
4963#define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
4964#define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
4965#define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
4966
4967/******************* Bit definition for IWDG_KR register ********************/
4968#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
4969
4970/******************************************************************************/
4971/* */
4972/* LCD-TFT Display Controller (LTDC) */
4973/* */
4974/******************************************************************************/
4975
4976/******************** Bit definition for LTDC_SSCR register *****************/
4977
4978#define LTDC_SSCR_VSH ((uint32_t)0x000007FF) /*!< Vertical Synchronization Height */
4979#define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) /*!< Horizontal Synchronization Width */
4980
4981/******************** Bit definition for LTDC_BPCR register *****************/
4982
4983#define LTDC_BPCR_AVBP ((uint32_t)0x000007FF) /*!< Accumulated Vertical Back Porch */
4984#define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) /*!< Accumulated Horizontal Back Porch */
4985
4986/******************** Bit definition for LTDC_AWCR register *****************/
4987
4988#define LTDC_AWCR_AAH ((uint32_t)0x000007FF) /*!< Accumulated Active heigh */
4989#define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) /*!< Accumulated Active Width */
4990
4991/******************** Bit definition for LTDC_TWCR register *****************/
4992
4993#define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) /*!< Total Heigh */
4994#define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) /*!< Total Width */
4995
4996/******************** Bit definition for LTDC_GCR register ******************/
4997
4998#define LTDC_GCR_LTDCEN ((uint32_t)0x00000001) /*!< LCD-TFT controller enable bit */
4999#define LTDC_GCR_DBW ((uint32_t)0x00000070) /*!< Dither Blue Width */
5000#define LTDC_GCR_DGW ((uint32_t)0x00000700) /*!< Dither Green Width */
5001#define LTDC_GCR_DRW ((uint32_t)0x00007000) /*!< Dither Red Width */
5002#define LTDC_GCR_DTEN ((uint32_t)0x00010000) /*!< Dither Enable */
5003#define LTDC_GCR_PCPOL ((uint32_t)0x10000000) /*!< Pixel Clock Polarity */
5004#define LTDC_GCR_DEPOL ((uint32_t)0x20000000) /*!< Data Enable Polarity */
5005#define LTDC_GCR_VSPOL ((uint32_t)0x40000000) /*!< Vertical Synchronization Polarity */
5006#define LTDC_GCR_HSPOL ((uint32_t)0x80000000) /*!< Horizontal Synchronization Polarity */
5007
5008/******************** Bit definition for LTDC_SRCR register *****************/
5009
5010#define LTDC_SRCR_IMR ((uint32_t)0x00000001) /*!< Immediate Reload */
5011#define LTDC_SRCR_VBR ((uint32_t)0x00000002) /*!< Vertical Blanking Reload */
5012
5013/******************** Bit definition for LTDC_BCCR register *****************/
5014
5015#define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) /*!< Background Blue value */
5016#define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) /*!< Background Green value */
5017#define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) /*!< Background Red value */
5018
5019/******************** Bit definition for LTDC_IER register ******************/
5020
5021#define LTDC_IER_LIE ((uint32_t)0x00000001) /*!< Line Interrupt Enable */
5022#define LTDC_IER_FUIE ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Enable */
5023#define LTDC_IER_TERRIE ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Enable */
5024#define LTDC_IER_RRIE ((uint32_t)0x00000008) /*!< Register Reload interrupt enable */
5025
5026/******************** Bit definition for LTDC_ISR register ******************/
5027
5028#define LTDC_ISR_LIF ((uint32_t)0x00000001) /*!< Line Interrupt Flag */
5029#define LTDC_ISR_FUIF ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Flag */
5030#define LTDC_ISR_TERRIF ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Flag */
5031#define LTDC_ISR_RRIF ((uint32_t)0x00000008) /*!< Register Reload interrupt Flag */
5032
5033/******************** Bit definition for LTDC_ICR register ******************/
5034
5035#define LTDC_ICR_CLIF ((uint32_t)0x00000001) /*!< Clears the Line Interrupt Flag */
5036#define LTDC_ICR_CFUIF ((uint32_t)0x00000002) /*!< Clears the FIFO Underrun Interrupt Flag */
5037#define LTDC_ICR_CTERRIF ((uint32_t)0x00000004) /*!< Clears the Transfer Error Interrupt Flag */
5038#define LTDC_ICR_CRRIF ((uint32_t)0x00000008) /*!< Clears Register Reload interrupt Flag */
5039
5040/******************** Bit definition for LTDC_LIPCR register ****************/
5041
5042#define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) /*!< Line Interrupt Position */
5043
5044/******************** Bit definition for LTDC_CPSR register *****************/
5045
5046#define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) /*!< Current Y Position */
5047#define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) /*!< Current X Position */
5048
5049/******************** Bit definition for LTDC_CDSR register *****************/
5050
5051#define LTDC_CDSR_VDES ((uint32_t)0x00000001) /*!< Vertical Data Enable Status */
5052#define LTDC_CDSR_HDES ((uint32_t)0x00000002) /*!< Horizontal Data Enable Status */
5053#define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) /*!< Vertical Synchronization Status */
5054#define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) /*!< Horizontal Synchronization Status */
5055
5056/******************** Bit definition for LTDC_LxCR register *****************/
5057
5058#define LTDC_LxCR_LEN ((uint32_t)0x00000001) /*!< Layer Enable */
5059#define LTDC_LxCR_COLKEN ((uint32_t)0x00000002) /*!< Color Keying Enable */
5060#define LTDC_LxCR_CLUTEN ((uint32_t)0x00000010) /*!< Color Lockup Table Enable */
5061
5062/******************** Bit definition for LTDC_LxWHPCR register **************/
5063
5064#define LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF) /*!< Window Horizontal Start Position */
5065#define LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000) /*!< Window Horizontal Stop Position */
5066
5067/******************** Bit definition for LTDC_LxWVPCR register **************/
5068
5069#define LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF) /*!< Window Vertical Start Position */
5070#define LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000) /*!< Window Vertical Stop Position */
5071
5072/******************** Bit definition for LTDC_LxCKCR register ***************/
5073
5074#define LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF) /*!< Color Key Blue value */
5075#define LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00) /*!< Color Key Green value */
5076#define LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000) /*!< Color Key Red value */
5077
5078/******************** Bit definition for LTDC_LxPFCR register ***************/
5079
5080#define LTDC_LxPFCR_PF ((uint32_t)0x00000007) /*!< Pixel Format */
5081
5082/******************** Bit definition for LTDC_LxCACR register ***************/
5083
5084#define LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF) /*!< Constant Alpha */
5085
5086/******************** Bit definition for LTDC_LxDCCR register ***************/
5087
5088#define LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF) /*!< Default Color Blue */
5089#define LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00) /*!< Default Color Green */
5090#define LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000) /*!< Default Color Red */
5091#define LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000) /*!< Default Color Alpha */
5092
5093/******************** Bit definition for LTDC_LxBFCR register ***************/
5094
5095#define LTDC_LxBFCR_BF2 ((uint32_t)0x00000007) /*!< Blending Factor 2 */
5096#define LTDC_LxBFCR_BF1 ((uint32_t)0x00000700) /*!< Blending Factor 1 */
5097
5098/******************** Bit definition for LTDC_LxCFBAR register **************/
5099
5100#define LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF) /*!< Color Frame Buffer Start Address */
5101
5102/******************** Bit definition for LTDC_LxCFBLR register **************/
5103
5104#define LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF) /*!< Color Frame Buffer Line Length */
5105#define LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000) /*!< Color Frame Buffer Pitch in bytes */
5106
5107/******************** Bit definition for LTDC_LxCFBLNR register *************/
5108
5109#define LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF) /*!< Frame Buffer Line Number */
5110
5111/******************** Bit definition for LTDC_LxCLUTWR register *************/
5112
5113#define LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF) /*!< Blue value */
5114#define LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00) /*!< Green value */
5115#define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) /*!< Red value */
5116#define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) /*!< CLUT address */
5117
5118
5119/******************************************************************************/
5120/* */
5121/* Power Control */
5122/* */
5123/******************************************************************************/
5124/******************** Bit definition for PWR_CR1 register ********************/
5125#define PWR_CR1_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
5126#define PWR_CR1_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
5127#define PWR_CR1_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
5128#define PWR_CR1_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
5129
5130#define PWR_CR1_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
5131#define PWR_CR1_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
5132#define PWR_CR1_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
5133#define PWR_CR1_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
5134
5135/*!< PVD level configuration */
5136#define PWR_CR1_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
5137#define PWR_CR1_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
5138#define PWR_CR1_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
5139#define PWR_CR1_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
5140#define PWR_CR1_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
5141#define PWR_CR1_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
5142#define PWR_CR1_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
5143#define PWR_CR1_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
5144
5145#define PWR_CR1_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
5146#define PWR_CR1_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
5147
5148#define PWR_CR1_LPUDS ((uint32_t)0x00000400) /*!< Low-power regulator in deepsleep under-drive mode */
5149#define PWR_CR1_MRUDS ((uint32_t)0x00000800) /*!< Main regulator in deepsleep under-drive mode */
5150
5151#define PWR_CR1_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
5152
5153#define PWR_CR1_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
5154#define PWR_CR1_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
5155#define PWR_CR1_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
5156
5157#define PWR_CR1_ODEN ((uint32_t)0x00010000) /*!< Over Drive enable */
5158#define PWR_CR1_ODSWEN ((uint32_t)0x00020000) /*!< Over Drive switch enabled */
5159#define PWR_CR1_UDEN ((uint32_t)0x000C0000) /*!< Under Drive enable in stop mode */
5160#define PWR_CR1_UDEN_0 ((uint32_t)0x00040000) /*!< Bit 0 */
5161#define PWR_CR1_UDEN_1 ((uint32_t)0x00080000) /*!< Bit 1 */
5162
5163/******************* Bit definition for PWR_CSR1 register ********************/
5164#define PWR_CSR1_WUIF ((uint32_t)0x00000001) /*!< Wake up internal Flag */
5165#define PWR_CSR1_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
5166#define PWR_CSR1_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
5167#define PWR_CSR1_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
5168#define PWR_CSR1_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
5169#define PWR_CSR1_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
5170
5171#define PWR_CSR1_ODRDY ((uint32_t)0x00010000) /*!< Over Drive generator ready */
5172#define PWR_CSR1_ODSWRDY ((uint32_t)0x00020000) /*!< Over Drive Switch ready */
5173#define PWR_CSR1_UDSWRDY ((uint32_t)0x000C0000) /*!< Under Drive ready */
5174
5175/******************** Bit definition for PWR_CR2 register ********************/
5176#define PWR_CR2_CWUPF1 ((uint32_t)0x00000001) /*!< Clear Wakeup Pin Flag for PA0 */
5177#define PWR_CR2_CWUPF2 ((uint32_t)0x00000002) /*!< Clear Wakeup Pin Flag for PA2 */
5178#define PWR_CR2_CWUPF3 ((uint32_t)0x00000004) /*!< Clear Wakeup Pin Flag for PC1 */
5179#define PWR_CR2_CWUPF4 ((uint32_t)0x00000008) /*!< Clear Wakeup Pin Flag for PC13 */
5180#define PWR_CR2_CWUPF5 ((uint32_t)0x00000010) /*!< Clear Wakeup Pin Flag for PI8 */
5181#define PWR_CR2_CWUPF6 ((uint32_t)0x00000020) /*!< Clear Wakeup Pin Flag for PI11 */
5182
5183#define PWR_CR2_WUPP1 ((uint32_t)0x00000100) /*!< Wakeup Pin Polarity bit for PA0 */
5184#define PWR_CR2_WUPP2 ((uint32_t)0x00000200) /*!< Wakeup Pin Polarity bit for PA2 */
5185#define PWR_CR2_WUPP3 ((uint32_t)0x00000400) /*!< Wakeup Pin Polarity bit for PC1 */
5186#define PWR_CR2_WUPP4 ((uint32_t)0x00000800) /*!< Wakeup Pin Polarity bit for PC13 */
5187#define PWR_CR2_WUPP5 ((uint32_t)0x00001000) /*!< Wakeup Pin Polarity bit for PI8 */
5188#define PWR_CR2_WUPP6 ((uint32_t)0x00002000) /*!< Wakeup Pin Polarity bit for PI11 */
5189
5190/******************* Bit definition for PWR_CSR2 register ********************/
5191#define PWR_CSR2_WUPF1 ((uint32_t)0x00000001) /*!< Wakeup Pin Flag for PA0 */
5192#define PWR_CSR2_WUPF2 ((uint32_t)0x00000002) /*!< Wakeup Pin Flag for PA2 */
5193#define PWR_CSR2_WUPF3 ((uint32_t)0x00000004) /*!< Wakeup Pin Flag for PC1 */
5194#define PWR_CSR2_WUPF4 ((uint32_t)0x00000008) /*!< Wakeup Pin Flag for PC13 */
5195#define PWR_CSR2_WUPF5 ((uint32_t)0x00000010) /*!< Wakeup Pin Flag for PI8 */
5196#define PWR_CSR2_WUPF6 ((uint32_t)0x00000020) /*!< Wakeup Pin Flag for PI11 */
5197
5198#define PWR_CSR2_EWUP1 ((uint32_t)0x00000100) /*!< Enable Wakeup Pin PA0 */
5199#define PWR_CSR2_EWUP2 ((uint32_t)0x00000200) /*!< Enable Wakeup Pin PA2 */
5200#define PWR_CSR2_EWUP3 ((uint32_t)0x00000400) /*!< Enable Wakeup Pin PC1 */
5201#define PWR_CSR2_EWUP4 ((uint32_t)0x00000800) /*!< Enable Wakeup Pin PC13 */
5202#define PWR_CSR2_EWUP5 ((uint32_t)0x00001000) /*!< Enable Wakeup Pin PI8 */
5203#define PWR_CSR2_EWUP6 ((uint32_t)0x00002000) /*!< Enable Wakeup Pin PI11 */
5204
5205/******************************************************************************/
5206/* */
5207/* QUADSPI */
5208/* */
5209/******************************************************************************/
5210/***************** Bit definition for QUADSPI_CR register *******************/
5211#define QUADSPI_CR_EN ((uint32_t)0x00000001) /*!< Enable */
5212#define QUADSPI_CR_ABORT ((uint32_t)0x00000002) /*!< Abort request */
5213#define QUADSPI_CR_DMAEN ((uint32_t)0x00000004) /*!< DMA Enable */
5214#define QUADSPI_CR_TCEN ((uint32_t)0x00000008) /*!< Timeout Counter Enable */
5215#define QUADSPI_CR_SSHIFT ((uint32_t)0x00000010) /*!< Sample Shift */
5216#define QUADSPI_CR_DFM ((uint32_t)0x00000040) /*!< Dual Flash Mode */
5217#define QUADSPI_CR_FSEL ((uint32_t)0x00000080) /*!< Flash Select */
5218#define QUADSPI_CR_FTHRES ((uint32_t)0x00000F00) /*!< FTHRES[3:0] FIFO Level */
5219#define QUADSPI_CR_FTHRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */
5220#define QUADSPI_CR_FTHRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */
5221#define QUADSPI_CR_FTHRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */
5222#define QUADSPI_CR_FTHRES_3 ((uint32_t)0x00000800) /*!< Bit 3 */
5223#define QUADSPI_CR_TEIE ((uint32_t)0x00010000) /*!< Transfer Error Interrupt Enable */
5224#define QUADSPI_CR_TCIE ((uint32_t)0x00020000) /*!< Transfer Complete Interrupt Enable */
5225#define QUADSPI_CR_FTIE ((uint32_t)0x00040000) /*!< FIFO Threshold Interrupt Enable */
5226#define QUADSPI_CR_SMIE ((uint32_t)0x00080000) /*!< Status Match Interrupt Enable */
5227#define QUADSPI_CR_TOIE ((uint32_t)0x00100000) /*!< TimeOut Interrupt Enable */
5228#define QUADSPI_CR_APMS ((uint32_t)0x00400000) /*!< Bit 1 */
5229#define QUADSPI_CR_PMM ((uint32_t)0x00800000) /*!< Polling Match Mode */
5230#define QUADSPI_CR_PRESCALER ((uint32_t)0xFF000000) /*!< PRESCALER[7:0] Clock prescaler */
5231#define QUADSPI_CR_PRESCALER_0 ((uint32_t)0x01000000) /*!< Bit 0 */
5232#define QUADSPI_CR_PRESCALER_1 ((uint32_t)0x02000000) /*!< Bit 1 */
5233#define QUADSPI_CR_PRESCALER_2 ((uint32_t)0x04000000) /*!< Bit 2 */
5234#define QUADSPI_CR_PRESCALER_3 ((uint32_t)0x08000000) /*!< Bit 3 */
5235#define QUADSPI_CR_PRESCALER_4 ((uint32_t)0x10000000) /*!< Bit 4 */
5236#define QUADSPI_CR_PRESCALER_5 ((uint32_t)0x20000000) /*!< Bit 5 */
5237#define QUADSPI_CR_PRESCALER_6 ((uint32_t)0x40000000) /*!< Bit 6 */
5238#define QUADSPI_CR_PRESCALER_7 ((uint32_t)0x80000000) /*!< Bit 7 */
5239
5240/***************** Bit definition for QUADSPI_DCR register ******************/
5241#define QUADSPI_DCR_CKMODE ((uint32_t)0x00000001) /*!< Mode 0 / Mode 3 */
5242#define QUADSPI_DCR_CSHT ((uint32_t)0x00000700) /*!< CSHT[2:0]: ChipSelect High Time */
5243#define QUADSPI_DCR_CSHT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
5244#define QUADSPI_DCR_CSHT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
5245#define QUADSPI_DCR_CSHT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
5246#define QUADSPI_DCR_FSIZE ((uint32_t)0x001F0000) /*!< FSIZE[4:0]: Flash Size */
5247#define QUADSPI_DCR_FSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
5248#define QUADSPI_DCR_FSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
5249#define QUADSPI_DCR_FSIZE_2 ((uint32_t)0x00040000) /*!< Bit 2 */
5250#define QUADSPI_DCR_FSIZE_3 ((uint32_t)0x00080000) /*!< Bit 3 */
5251#define QUADSPI_DCR_FSIZE_4 ((uint32_t)0x00100000) /*!< Bit 4 */
5252
5253/****************** Bit definition for QUADSPI_SR register *******************/
5254#define QUADSPI_SR_TEF ((uint32_t)0x00000001) /*!< Transfer Error Flag */
5255#define QUADSPI_SR_TCF ((uint32_t)0x00000002) /*!< Transfer Complete Flag */
5256#define QUADSPI_SR_FTF ((uint32_t)0x00000004) /*!< FIFO Threshlod Flag */
5257#define QUADSPI_SR_SMF ((uint32_t)0x00000008) /*!< Status Match Flag */
5258#define QUADSPI_SR_TOF ((uint32_t)0x00000010) /*!< Timeout Flag */
5259#define QUADSPI_SR_BUSY ((uint32_t)0x00000020) /*!< Busy */
5260#define QUADSPI_SR_FLEVEL ((uint32_t)0x00001F00) /*!< FIFO Threshlod Flag */
5261#define QUADSPI_SR_FLEVEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
5262#define QUADSPI_SR_FLEVEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
5263#define QUADSPI_SR_FLEVEL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
5264#define QUADSPI_SR_FLEVEL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
5265#define QUADSPI_SR_FLEVEL_4 ((uint32_t)0x00001000) /*!< Bit 4 */
5266
5267/****************** Bit definition for QUADSPI_FCR register ******************/
5268#define QUADSPI_FCR_CTEF ((uint32_t)0x00000001) /*!< Clear Transfer Error Flag */
5269#define QUADSPI_FCR_CTCF ((uint32_t)0x00000002) /*!< Clear Transfer Complete Flag */
5270#define QUADSPI_FCR_CSMF ((uint32_t)0x00000008) /*!< Clear Status Match Flag */
5271#define QUADSPI_FCR_CTOF ((uint32_t)0x00000010) /*!< Clear Timeout Flag */
5272
5273/****************** Bit definition for QUADSPI_DLR register ******************/
5274#define QUADSPI_DLR_DL ((uint32_t)0xFFFFFFFF) /*!< DL[31:0]: Data Length */
5275
5276/****************** Bit definition for QUADSPI_CCR register ******************/
5277#define QUADSPI_CCR_INSTRUCTION ((uint32_t)0x000000FF) /*!< INSTRUCTION[7:0]: Instruction */
5278#define QUADSPI_CCR_INSTRUCTION_0 ((uint32_t)0x00000001) /*!< Bit 0 */
5279#define QUADSPI_CCR_INSTRUCTION_1 ((uint32_t)0x00000002) /*!< Bit 1 */
5280#define QUADSPI_CCR_INSTRUCTION_2 ((uint32_t)0x00000004) /*!< Bit 2 */
5281#define QUADSPI_CCR_INSTRUCTION_3 ((uint32_t)0x00000008) /*!< Bit 3 */
5282#define QUADSPI_CCR_INSTRUCTION_4 ((uint32_t)0x00000010) /*!< Bit 4 */
5283#define QUADSPI_CCR_INSTRUCTION_5 ((uint32_t)0x00000020) /*!< Bit 5 */
5284#define QUADSPI_CCR_INSTRUCTION_6 ((uint32_t)0x00000040) /*!< Bit 6 */
5285#define QUADSPI_CCR_INSTRUCTION_7 ((uint32_t)0x00000080) /*!< Bit 7 */
5286#define QUADSPI_CCR_IMODE ((uint32_t)0x00000300) /*!< IMODE[1:0]: Instruction Mode */
5287#define QUADSPI_CCR_IMODE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
5288#define QUADSPI_CCR_IMODE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
5289#define QUADSPI_CCR_ADMODE ((uint32_t)0x00000C00) /*!< ADMODE[1:0]: Address Mode */
5290#define QUADSPI_CCR_ADMODE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5291#define QUADSPI_CCR_ADMODE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5292#define QUADSPI_CCR_ADSIZE ((uint32_t)0x00003000) /*!< ADSIZE[1:0]: Address Size */
5293#define QUADSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000) /*!< Bit 0 */
5294#define QUADSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000) /*!< Bit 1 */
5295#define QUADSPI_CCR_ABMODE ((uint32_t)0x0000C000) /*!< ABMODE[1:0]: Alternate Bytes Mode */
5296#define QUADSPI_CCR_ABMODE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
5297#define QUADSPI_CCR_ABMODE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
5298#define QUADSPI_CCR_ABSIZE ((uint32_t)0x00030000) /*!< ABSIZE[1:0]: Instruction Mode */
5299#define QUADSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
5300#define QUADSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
5301#define QUADSPI_CCR_DCYC ((uint32_t)0x007C0000) /*!< DCYC[4:0]: Dummy Cycles */
5302#define QUADSPI_CCR_DCYC_0 ((uint32_t)0x00040000) /*!< Bit 0 */
5303#define QUADSPI_CCR_DCYC_1 ((uint32_t)0x00080000) /*!< Bit 1 */
5304#define QUADSPI_CCR_DCYC_2 ((uint32_t)0x00100000) /*!< Bit 2 */
5305#define QUADSPI_CCR_DCYC_3 ((uint32_t)0x00200000) /*!< Bit 3 */
5306#define QUADSPI_CCR_DCYC_4 ((uint32_t)0x00400000) /*!< Bit 4 */
5307#define QUADSPI_CCR_DMODE ((uint32_t)0x03000000) /*!< DMODE[1:0]: Data Mode */
5308#define QUADSPI_CCR_DMODE_0 ((uint32_t)0x01000000) /*!< Bit 0 */
5309#define QUADSPI_CCR_DMODE_1 ((uint32_t)0x02000000) /*!< Bit 1 */
5310#define QUADSPI_CCR_FMODE ((uint32_t)0x0C000000) /*!< FMODE[1:0]: Functional Mode */
5311#define QUADSPI_CCR_FMODE_0 ((uint32_t)0x04000000) /*!< Bit 0 */
5312#define QUADSPI_CCR_FMODE_1 ((uint32_t)0x08000000) /*!< Bit 1 */
5313#define QUADSPI_CCR_SIOO ((uint32_t)0x10000000) /*!< SIOO: Send Instruction Only Once Mode */
5314#define QUADSPI_CCR_DHHC ((uint32_t)0x40000000) /*!< DHHC: Delay Half Hclk Cycle */
5315#define QUADSPI_CCR_DDRM ((uint32_t)0x80000000) /*!< DDRM: Double Data Rate Mode */
5316/****************** Bit definition for QUADSPI_AR register *******************/
5317#define QUADSPI_AR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< ADDRESS[31:0]: Address */
5318
5319/****************** Bit definition for QUADSPI_ABR register ******************/
5320#define QUADSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFF) /*!< ALTERNATE[31:0]: Alternate Bytes */
5321
5322/****************** Bit definition for QUADSPI_DR register *******************/
5323#define QUADSPI_DR_DATA ((uint32_t)0xFFFFFFFF) /*!< DATA[31:0]: Data */
5324
5325/****************** Bit definition for QUADSPI_PSMKR register ****************/
5326#define QUADSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFF) /*!< MASK[31:0]: Status Mask */
5327
5328/****************** Bit definition for QUADSPI_PSMAR register ****************/
5329#define QUADSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFF) /*!< MATCH[31:0]: Status Match */
5330
5331/****************** Bit definition for QUADSPI_PIR register *****************/
5332#define QUADSPI_PIR_INTERVAL ((uint32_t)0x0000FFFF) /*!< INTERVAL[15:0]: Polling Interval */
5333
5334/****************** Bit definition for QUADSPI_LPTR register *****************/
5335#define QUADSPI_LPTR_TIMEOUT ((uint32_t)0x0000FFFF) /*!< TIMEOUT[15:0]: Timeout period */
5336
5337/******************************************************************************/
5338/* */
5339/* Reset and Clock Control */
5340/* */
5341/******************************************************************************/
5342/******************** Bit definition for RCC_CR register ********************/
5343#define RCC_CR_HSION ((uint32_t)0x00000001)
5344#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
5345
5346#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
5347#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
5348#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
5349#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
5350#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
5351#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
5352
5353#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
5354#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5355#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5356#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5357#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5358#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5359#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5360#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5361#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5362
5363#define RCC_CR_HSEON ((uint32_t)0x00010000)
5364#define RCC_CR_HSERDY ((uint32_t)0x00020000)
5365#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
5366#define RCC_CR_CSSON ((uint32_t)0x00080000)
5367#define RCC_CR_PLLON ((uint32_t)0x01000000)
5368#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
5369#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
5370#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
5371#define RCC_CR_PLLSAION ((uint32_t)0x10000000)
5372#define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
5373
5374/******************** Bit definition for RCC_PLLCFGR register ***************/
5375#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
5376#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
5377#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
5378#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
5379#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
5380#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
5381#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
5382
5383#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
5384#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
5385#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
5386#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
5387#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
5388#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
5389#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
5390#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
5391#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
5392#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
5393
5394#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
5395#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
5396#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
5397
5398#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
5399#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
5400#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
5401
5402#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
5403#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
5404#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
5405#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
5406#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
5407
5408/******************** Bit definition for RCC_CFGR register ******************/
5409/*!< SW configuration */
5410#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
5411#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
5412#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
5413
5414#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
5415#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
5416#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
5417
5418/*!< SWS configuration */
5419#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
5420#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
5421#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
5422
5423#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
5424#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
5425#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
5426
5427/*!< HPRE configuration */
5428#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
5429#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
5430#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
5431#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
5432#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
5433
5434#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
5435#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
5436#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
5437#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
5438#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
5439#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
5440#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
5441#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
5442#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
5443
5444/*!< PPRE1 configuration */
5445#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
5446#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5447#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5448#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
5449
5450#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
5451#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
5452#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
5453#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
5454#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
5455
5456/*!< PPRE2 configuration */
5457#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
5458#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
5459#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
5460#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
5461
5462#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
5463#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
5464#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
5465#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
5466#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
5467
5468/*!< RTCPRE configuration */
5469#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
5470#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
5471#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
5472#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
5473#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
5474#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
5475
5476/*!< MCO1 configuration */
5477#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
5478#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
5479#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
5480
5481#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
5482
5483#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
5484#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
5485#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
5486#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
5487
5488#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
5489#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
5490#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
5491#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
5492
5493#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
5494#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
5495#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
5496
5497/******************** Bit definition for RCC_CIR register *******************/
5498#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
5499#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
5500#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
5501#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
5502#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
5503#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
5504#define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)
5505#define RCC_CIR_CSSF ((uint32_t)0x00000080)
5506#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
5507#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
5508#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
5509#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
5510#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
5511#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
5512#define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
5513#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
5514#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
5515#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
5516#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
5517#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
5518#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
5519#define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)
5520#define RCC_CIR_CSSC ((uint32_t)0x00800000)
5521
5522/******************** Bit definition for RCC_AHB1RSTR register **************/
5523#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
5524#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
5525#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
5526#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
5527#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
5528#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
5529#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
5530#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
5531#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
5532#define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)
5533#define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)
5534#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
5535#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
5536#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
5537#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
5538#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
5539#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
5540
5541/******************** Bit definition for RCC_AHB2RSTR register **************/
5542#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
5543#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
5544#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
5545
5546/******************** Bit definition for RCC_AHB3RSTR register **************/
5547
5548#define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
5549#define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000002)
5550
5551/******************** Bit definition for RCC_APB1RSTR register **************/
5552#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
5553#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
5554#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
5555#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
5556#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
5557#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
5558#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
5559#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
5560#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
5561#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x00000200)
5562#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
5563#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
5564#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
5565#define RCC_APB1RSTR_SPDIFRXRST ((uint32_t)0x00010000)
5566#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
5567#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
5568#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
5569#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
5570#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
5571#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
5572#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
5573#define RCC_APB1RSTR_I2C4RST ((uint32_t)0x01000000)
5574#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
5575#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
5576#define RCC_APB1RSTR_CECRST ((uint32_t)0x08000000)
5577#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
5578#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
5579#define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
5580#define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
5581
5582/******************** Bit definition for RCC_APB2RSTR register **************/
5583#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
5584#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
5585#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
5586#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
5587#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
5588#define RCC_APB2RSTR_SDMMC1RST ((uint32_t)0x00000800)
5589#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
5590#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
5591#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
5592#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
5593#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
5594#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
5595#define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
5596#define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
5597#define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
5598#define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00800000)
5599#define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)
5600
5601/******************** Bit definition for RCC_AHB1ENR register ***************/
5602#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
5603#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
5604#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
5605#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
5606#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
5607#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
5608#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
5609#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
5610#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
5611#define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)
5612#define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)
5613#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
5614#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
5615#define RCC_AHB1ENR_DTCMRAMEN ((uint32_t)0x00100000)
5616#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
5617#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
5618#define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)
5619#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
5620#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
5621#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
5622#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
5623#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
5624#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
5625
5626/******************** Bit definition for RCC_AHB2ENR register ***************/
5627#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
5628#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
5629#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
5630
5631/******************** Bit definition for RCC_AHB3ENR register ***************/
5632
5633#define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
5634#define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000002)
5635
5636/******************** Bit definition for RCC_APB1ENR register ***************/
5637#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
5638#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
5639#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
5640#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
5641#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
5642#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
5643#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
5644#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
5645#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
5646#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x00000200)
5647#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
5648#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
5649#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
5650#define RCC_APB1ENR_SPDIFRXEN ((uint32_t)0x00010000)
5651#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
5652#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
5653#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
5654#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
5655#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
5656#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
5657#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
5658#define RCC_APB1ENR_I2C4EN ((uint32_t)0x01000000)
5659#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
5660#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
5661#define RCC_APB1ENR_CECEN ((uint32_t)0x08000000)
5662#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
5663#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
5664#define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)
5665#define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
5666
5667/******************** Bit definition for RCC_APB2ENR register ***************/
5668#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
5669#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
5670#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
5671#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
5672#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
5673#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
5674#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
5675#define RCC_APB2ENR_SDMMC1EN ((uint32_t)0x00000800)
5676#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
5677#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
5678#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
5679#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
5680#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
5681#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
5682#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
5683#define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
5684#define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)
5685#define RCC_APB2ENR_SAI2EN ((uint32_t)0x00800000)
5686#define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)
5687
5688/******************** Bit definition for RCC_AHB1LPENR register *************/
5689#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
5690#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
5691#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
5692#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
5693#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
5694#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
5695#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
5696#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
5697#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
5698#define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
5699#define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)
5700
5701#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
5702#define RCC_AHB1LPENR_AXILPEN ((uint32_t)0x00002000)
5703#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
5704#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
5705#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
5706#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
5707#define RCC_AHB1LPENR_DTCMLPEN ((uint32_t)0x00100000)
5708#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
5709#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
5710#define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)
5711#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
5712#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
5713#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
5714#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
5715#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
5716#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
5717
5718/******************** Bit definition for RCC_AHB2LPENR register *************/
5719#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
5720#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
5721#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
5722
5723/******************** Bit definition for RCC_AHB3LPENR register *************/
5724#define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
5725#define RCC_AHB3LPENR_QSPILPEN ((uint32_t)0x00000002)
5726/******************** Bit definition for RCC_APB1LPENR register *************/
5727#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
5728#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
5729#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
5730#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
5731#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
5732#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
5733#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
5734#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
5735#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
5736#define RCC_APB1LPENR_LPTIM1LPEN ((uint32_t)0x00000200)
5737#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
5738#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
5739#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
5740#define RCC_APB1LPENR_SPDIFRXLPEN ((uint32_t)0x00010000)
5741#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
5742#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
5743#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
5744#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
5745#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
5746#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
5747#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
5748#define RCC_APB1LPENR_I2C4LPEN ((uint32_t)0x01000000)
5749#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
5750#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
5751#define RCC_APB1LPENR_CECLPEN ((uint32_t)0x08000000)
5752#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
5753#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
5754#define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
5755#define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
5756
5757/******************** Bit definition for RCC_APB2LPENR register *************/
5758#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
5759#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
5760#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
5761#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
5762#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
5763#define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
5764#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
5765#define RCC_APB2LPENR_SDMMC1LPEN ((uint32_t)0x00000800)
5766#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
5767#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
5768#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
5769#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
5770#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
5771#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
5772#define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
5773#define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
5774#define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)
5775#define RCC_APB2LPENR_SAI2LPEN ((uint32_t)0x00800000)
5776#define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)
5777
5778/******************** Bit definition for RCC_BDCR register ******************/
5779#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
5780#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
5781#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
5782#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018)
5783#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008)
5784#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010)
5785#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
5786#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
5787#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
5788#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
5789#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
5790
5791/******************** Bit definition for RCC_CSR register *******************/
5792#define RCC_CSR_LSION ((uint32_t)0x00000001)
5793#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
5794#define RCC_CSR_RMVF ((uint32_t)0x01000000)
5795#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
5796#define RCC_CSR_PINRSTF ((uint32_t)0x04000000)
5797#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
5798#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
5799#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000)
5800#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
5801#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
5802
5803/******************** Bit definition for RCC_SSCGR register *****************/
5804#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
5805#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
5806#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
5807#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
5808
5809/******************** Bit definition for RCC_PLLI2SCFGR register ************/
5810#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
5811#define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
5812#define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
5813#define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
5814#define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
5815#define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
5816#define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
5817#define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
5818#define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
5819#define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
5820
5821#define RCC_PLLI2SCFGR_PLLI2SP ((uint32_t)0x00030000)
5822#define RCC_PLLI2SCFGR_PLLI2SP_0 ((uint32_t)0x00010000)
5823#define RCC_PLLI2SCFGR_PLLI2SP_1 ((uint32_t)0x00020000)
5824
5825#define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
5826#define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)
5827#define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)
5828#define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)
5829#define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)
5830
5831#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
5832#define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
5833#define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
5834#define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
5835
5836/******************** Bit definition for RCC_PLLSAICFGR register ************/
5837#define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)
5838#define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)
5839#define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)
5840#define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)
5841#define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)
5842#define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400)
5843#define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)
5844#define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)
5845#define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)
5846#define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)
5847
5848#define RCC_PLLSAICFGR_PLLSAIP ((uint32_t)0x00030000)
5849#define RCC_PLLSAICFGR_PLLSAIP_0 ((uint32_t)0x00010000)
5850#define RCC_PLLSAICFGR_PLLSAIP_1 ((uint32_t)0x00020000)
5851
5852#define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)
5853#define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)
5854#define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)
5855#define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000)
5856#define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)
5857
5858#define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000)
5859#define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000)
5860#define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000)
5861#define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000)
5862
5863/******************** Bit definition for RCC_DCKCFGR1 register ***************/
5864#define RCC_DCKCFGR1_PLLI2SDIVQ ((uint32_t)0x0000001F)
5865#define RCC_DCKCFGR1_PLLI2SDIVQ_0 ((uint32_t)0x00000001)
5866#define RCC_DCKCFGR1_PLLI2SDIVQ_1 ((uint32_t)0x00000002)
5867#define RCC_DCKCFGR1_PLLI2SDIVQ_2 ((uint32_t)0x00000004)
5868#define RCC_DCKCFGR1_PLLI2SDIVQ_3 ((uint32_t)0x00000008)
5869#define RCC_DCKCFGR1_PLLI2SDIVQ_4 ((uint32_t)0x00000010)
5870
5871#define RCC_DCKCFGR1_PLLSAIDIVQ ((uint32_t)0x00001F00)
5872#define RCC_DCKCFGR1_PLLSAIDIVQ_0 ((uint32_t)0x00000100)
5873#define RCC_DCKCFGR1_PLLSAIDIVQ_1 ((uint32_t)0x00000200)
5874#define RCC_DCKCFGR1_PLLSAIDIVQ_2 ((uint32_t)0x00000400)
5875#define RCC_DCKCFGR1_PLLSAIDIVQ_3 ((uint32_t)0x00000800)
5876#define RCC_DCKCFGR1_PLLSAIDIVQ_4 ((uint32_t)0x00001000)
5877
5878#define RCC_DCKCFGR1_PLLSAIDIVR ((uint32_t)0x00030000)
5879#define RCC_DCKCFGR1_PLLSAIDIVR_0 ((uint32_t)0x00010000)
5880#define RCC_DCKCFGR1_PLLSAIDIVR_1 ((uint32_t)0x00020000)
5881
5882#define RCC_DCKCFGR1_SAI1SEL ((uint32_t)0x00300000)
5883#define RCC_DCKCFGR1_SAI1SEL_0 ((uint32_t)0x00100000)
5884#define RCC_DCKCFGR1_SAI1SEL_1 ((uint32_t)0x00200000)
5885
5886#define RCC_DCKCFGR1_SAI2SEL ((uint32_t)0x00C00000)
5887#define RCC_DCKCFGR1_SAI2SEL_0 ((uint32_t)0x00400000)
5888#define RCC_DCKCFGR1_SAI2SEL_1 ((uint32_t)0x00800000)
5889
5890#define RCC_DCKCFGR1_TIMPRE ((uint32_t)0x01000000)
5891
5892/******************** Bit definition for RCC_DCKCFGR2 register ***************/
5893#define RCC_DCKCFGR2_USART1SEL ((uint32_t)0x00000003)
5894#define RCC_DCKCFGR2_USART1SEL_0 ((uint32_t)0x00000001)
5895#define RCC_DCKCFGR2_USART1SEL_1 ((uint32_t)0x00000002)
5896#define RCC_DCKCFGR2_USART2SEL ((uint32_t)0x0000000C)
5897#define RCC_DCKCFGR2_USART2SEL_0 ((uint32_t)0x00000004)
5898#define RCC_DCKCFGR2_USART2SEL_1 ((uint32_t)0x00000008)
5899#define RCC_DCKCFGR2_USART3SEL ((uint32_t)0x00000030)
5900#define RCC_DCKCFGR2_USART3SEL_0 ((uint32_t)0x00000010)
5901#define RCC_DCKCFGR2_USART3SEL_1 ((uint32_t)0x00000020)
5902#define RCC_DCKCFGR2_UART4SEL ((uint32_t)0x000000C0)
5903#define RCC_DCKCFGR2_UART4SEL_0 ((uint32_t)0x00000040)
5904#define RCC_DCKCFGR2_UART4SEL_1 ((uint32_t)0x00000080)
5905#define RCC_DCKCFGR2_UART5SEL ((uint32_t)0x00000300)
5906#define RCC_DCKCFGR2_UART5SEL_0 ((uint32_t)0x00000100)
5907#define RCC_DCKCFGR2_UART5SEL_1 ((uint32_t)0x00000200)
5908#define RCC_DCKCFGR2_USART6SEL ((uint32_t)0x00000C00)
5909#define RCC_DCKCFGR2_USART6SEL_0 ((uint32_t)0x00000400)
5910#define RCC_DCKCFGR2_USART6SEL_1 ((uint32_t)0x00000800)
5911#define RCC_DCKCFGR2_UART7SEL ((uint32_t)0x00003000)
5912#define RCC_DCKCFGR2_UART7SEL_0 ((uint32_t)0x00001000)
5913#define RCC_DCKCFGR2_UART7SEL_1 ((uint32_t)0x00002000)
5914#define RCC_DCKCFGR2_UART8SEL ((uint32_t)0x0000C000)
5915#define RCC_DCKCFGR2_UART8SEL_0 ((uint32_t)0x00004000)
5916#define RCC_DCKCFGR2_UART8SEL_1 ((uint32_t)0x00008000)
5917#define RCC_DCKCFGR2_I2C1SEL ((uint32_t)0x00030000)
5918#define RCC_DCKCFGR2_I2C1SEL_0 ((uint32_t)0x00010000)
5919#define RCC_DCKCFGR2_I2C1SEL_1 ((uint32_t)0x00020000)
5920#define RCC_DCKCFGR2_I2C2SEL ((uint32_t)0x000C0000)
5921#define RCC_DCKCFGR2_I2C2SEL_0 ((uint32_t)0x00040000)
5922#define RCC_DCKCFGR2_I2C2SEL_1 ((uint32_t)0x00080000)
5923#define RCC_DCKCFGR2_I2C3SEL ((uint32_t)0x00300000)
5924#define RCC_DCKCFGR2_I2C3SEL_0 ((uint32_t)0x00100000)
5925#define RCC_DCKCFGR2_I2C3SEL_1 ((uint32_t)0x00200000)
5926#define RCC_DCKCFGR2_I2C4SEL ((uint32_t)0x00C00000)
5927#define RCC_DCKCFGR2_I2C4SEL_0 ((uint32_t)0x00400000)
5928#define RCC_DCKCFGR2_I2C4SEL_1 ((uint32_t)0x00800000)
5929#define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0x03000000)
5930#define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x01000000)
5931#define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x02000000)
5932#define RCC_DCKCFGR2_CECSEL ((uint32_t)0x04000000)
5933#define RCC_DCKCFGR2_CK48MSEL ((uint32_t)0x08000000)
5934#define RCC_DCKCFGR2_SDMMC1SEL ((uint32_t)0x10000000)
5935
5936/******************************************************************************/
5937/* */
5938/* RNG */
5939/* */
5940/******************************************************************************/
5941/******************** Bits definition for RNG_CR register *******************/
5942#define RNG_CR_RNGEN ((uint32_t)0x00000004)
5943#define RNG_CR_IE ((uint32_t)0x00000008)
5944
5945/******************** Bits definition for RNG_SR register *******************/
5946#define RNG_SR_DRDY ((uint32_t)0x00000001)
5947#define RNG_SR_CECS ((uint32_t)0x00000002)
5948#define RNG_SR_SECS ((uint32_t)0x00000004)
5949#define RNG_SR_CEIS ((uint32_t)0x00000020)
5950#define RNG_SR_SEIS ((uint32_t)0x00000040)
5951
5952/******************************************************************************/
5953/* */
5954/* Real-Time Clock (RTC) */
5955/* */
5956/******************************************************************************/
5957/******************** Bits definition for RTC_TR register *******************/
5958#define RTC_TR_PM ((uint32_t)0x00400000)
5959#define RTC_TR_HT ((uint32_t)0x00300000)
5960#define RTC_TR_HT_0 ((uint32_t)0x00100000)
5961#define RTC_TR_HT_1 ((uint32_t)0x00200000)
5962#define RTC_TR_HU ((uint32_t)0x000F0000)
5963#define RTC_TR_HU_0 ((uint32_t)0x00010000)
5964#define RTC_TR_HU_1 ((uint32_t)0x00020000)
5965#define RTC_TR_HU_2 ((uint32_t)0x00040000)
5966#define RTC_TR_HU_3 ((uint32_t)0x00080000)
5967#define RTC_TR_MNT ((uint32_t)0x00007000)
5968#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
5969#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
5970#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
5971#define RTC_TR_MNU ((uint32_t)0x00000F00)
5972#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
5973#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
5974#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
5975#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
5976#define RTC_TR_ST ((uint32_t)0x00000070)
5977#define RTC_TR_ST_0 ((uint32_t)0x00000010)
5978#define RTC_TR_ST_1 ((uint32_t)0x00000020)
5979#define RTC_TR_ST_2 ((uint32_t)0x00000040)
5980#define RTC_TR_SU ((uint32_t)0x0000000F)
5981#define RTC_TR_SU_0 ((uint32_t)0x00000001)
5982#define RTC_TR_SU_1 ((uint32_t)0x00000002)
5983#define RTC_TR_SU_2 ((uint32_t)0x00000004)
5984#define RTC_TR_SU_3 ((uint32_t)0x00000008)
5985
5986/******************** Bits definition for RTC_DR register *******************/
5987#define RTC_DR_YT ((uint32_t)0x00F00000)
5988#define RTC_DR_YT_0 ((uint32_t)0x00100000)
5989#define RTC_DR_YT_1 ((uint32_t)0x00200000)
5990#define RTC_DR_YT_2 ((uint32_t)0x00400000)
5991#define RTC_DR_YT_3 ((uint32_t)0x00800000)
5992#define RTC_DR_YU ((uint32_t)0x000F0000)
5993#define RTC_DR_YU_0 ((uint32_t)0x00010000)
5994#define RTC_DR_YU_1 ((uint32_t)0x00020000)
5995#define RTC_DR_YU_2 ((uint32_t)0x00040000)
5996#define RTC_DR_YU_3 ((uint32_t)0x00080000)
5997#define RTC_DR_WDU ((uint32_t)0x0000E000)
5998#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
5999#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
6000#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
6001#define RTC_DR_MT ((uint32_t)0x00001000)
6002#define RTC_DR_MU ((uint32_t)0x00000F00)
6003#define RTC_DR_MU_0 ((uint32_t)0x00000100)
6004#define RTC_DR_MU_1 ((uint32_t)0x00000200)
6005#define RTC_DR_MU_2 ((uint32_t)0x00000400)
6006#define RTC_DR_MU_3 ((uint32_t)0x00000800)
6007#define RTC_DR_DT ((uint32_t)0x00000030)
6008#define RTC_DR_DT_0 ((uint32_t)0x00000010)
6009#define RTC_DR_DT_1 ((uint32_t)0x00000020)
6010#define RTC_DR_DU ((uint32_t)0x0000000F)
6011#define RTC_DR_DU_0 ((uint32_t)0x00000001)
6012#define RTC_DR_DU_1 ((uint32_t)0x00000002)
6013#define RTC_DR_DU_2 ((uint32_t)0x00000004)
6014#define RTC_DR_DU_3 ((uint32_t)0x00000008)
6015
6016/******************** Bits definition for RTC_CR register *******************/
6017#define RTC_CR_ITSE ((uint32_t)0x01000000)
6018#define RTC_CR_COE ((uint32_t)0x00800000)
6019#define RTC_CR_OSEL ((uint32_t)0x00600000)
6020#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
6021#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
6022#define RTC_CR_POL ((uint32_t)0x00100000)
6023#define RTC_CR_COSEL ((uint32_t)0x00080000)
6024#define RTC_CR_BCK ((uint32_t)0x00040000)
6025#define RTC_CR_SUB1H ((uint32_t)0x00020000)
6026#define RTC_CR_ADD1H ((uint32_t)0x00010000)
6027#define RTC_CR_TSIE ((uint32_t)0x00008000)
6028#define RTC_CR_WUTIE ((uint32_t)0x00004000)
6029#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
6030#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
6031#define RTC_CR_TSE ((uint32_t)0x00000800)
6032#define RTC_CR_WUTE ((uint32_t)0x00000400)
6033#define RTC_CR_ALRBE ((uint32_t)0x00000200)
6034#define RTC_CR_ALRAE ((uint32_t)0x00000100)
6035#define RTC_CR_FMT ((uint32_t)0x00000040)
6036#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
6037#define RTC_CR_REFCKON ((uint32_t)0x00000010)
6038#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
6039#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
6040#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
6041#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
6042#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
6043
6044/******************** Bits definition for RTC_ISR register ******************/
6045#define RTC_ISR_ITSF ((uint32_t)0x00020000)
6046#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
6047#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
6048#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
6049#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
6050#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
6051#define RTC_ISR_TSF ((uint32_t)0x00000800)
6052#define RTC_ISR_WUTF ((uint32_t)0x00000400)
6053#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
6054#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
6055#define RTC_ISR_INIT ((uint32_t)0x00000080)
6056#define RTC_ISR_INITF ((uint32_t)0x00000040)
6057#define RTC_ISR_RSF ((uint32_t)0x00000020)
6058#define RTC_ISR_INITS ((uint32_t)0x00000010)
6059#define RTC_ISR_SHPF ((uint32_t)0x00000008)
6060#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
6061#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
6062#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
6063
6064/******************** Bits definition for RTC_PRER register *****************/
6065#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
6066#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
6067
6068/******************** Bits definition for RTC_WUTR register *****************/
6069#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
6070
6071/******************** Bits definition for RTC_ALRMAR register ***************/
6072#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
6073#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
6074#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
6075#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
6076#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
6077#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
6078#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
6079#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
6080#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
6081#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
6082#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
6083#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
6084#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
6085#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
6086#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
6087#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
6088#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
6089#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
6090#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
6091#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
6092#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
6093#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
6094#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
6095#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
6096#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
6097#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
6098#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
6099#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
6100#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
6101#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
6102#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
6103#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
6104#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
6105#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
6106#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
6107#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
6108#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
6109#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
6110#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
6111#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
6112
6113/******************** Bits definition for RTC_ALRMBR register ***************/
6114#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
6115#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
6116#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
6117#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
6118#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
6119#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
6120#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
6121#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
6122#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
6123#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
6124#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
6125#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
6126#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
6127#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
6128#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
6129#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
6130#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
6131#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
6132#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
6133#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
6134#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
6135#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
6136#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
6137#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
6138#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
6139#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
6140#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
6141#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
6142#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
6143#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
6144#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
6145#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
6146#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
6147#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
6148#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
6149#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
6150#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
6151#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
6152#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
6153#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
6154
6155/******************** Bits definition for RTC_WPR register ******************/
6156#define RTC_WPR_KEY ((uint32_t)0x000000FF)
6157
6158/******************** Bits definition for RTC_SSR register ******************/
6159#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
6160
6161/******************** Bits definition for RTC_SHIFTR register ***************/
6162#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
6163#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
6164
6165/******************** Bits definition for RTC_TSTR register *****************/
6166#define RTC_TSTR_PM ((uint32_t)0x00400000)
6167#define RTC_TSTR_HT ((uint32_t)0x00300000)
6168#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
6169#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
6170#define RTC_TSTR_HU ((uint32_t)0x000F0000)
6171#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
6172#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
6173#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
6174#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
6175#define RTC_TSTR_MNT ((uint32_t)0x00007000)
6176#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
6177#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
6178#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
6179#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
6180#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
6181#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
6182#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
6183#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
6184#define RTC_TSTR_ST ((uint32_t)0x00000070)
6185#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
6186#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
6187#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
6188#define RTC_TSTR_SU ((uint32_t)0x0000000F)
6189#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
6190#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
6191#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
6192#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
6193
6194/******************** Bits definition for RTC_TSDR register *****************/
6195#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
6196#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
6197#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
6198#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
6199#define RTC_TSDR_MT ((uint32_t)0x00001000)
6200#define RTC_TSDR_MU ((uint32_t)0x00000F00)
6201#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
6202#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
6203#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
6204#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
6205#define RTC_TSDR_DT ((uint32_t)0x00000030)
6206#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
6207#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
6208#define RTC_TSDR_DU ((uint32_t)0x0000000F)
6209#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
6210#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
6211#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
6212#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
6213
6214/******************** Bits definition for RTC_TSSSR register ****************/
6215#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
6216
6217/******************** Bits definition for RTC_CAL register *****************/
6218#define RTC_CALR_CALP ((uint32_t)0x00008000)
6219#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
6220#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
6221#define RTC_CALR_CALM ((uint32_t)0x000001FF)
6222#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
6223#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
6224#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
6225#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
6226#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
6227#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
6228#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
6229#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
6230#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
6231
6232/******************** Bits definition for RTC_TAMPCR register ****************/
6233#define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000)
6234#define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000)
6235#define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000)
6236#define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000)
6237#define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000)
6238#define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000)
6239#define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000)
6240#define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000)
6241#define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000)
6242#define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000)
6243#define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000)
6244#define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000)
6245#define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000)
6246#define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800)
6247#define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800)
6248#define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000)
6249#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700)
6250#define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100)
6251#define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200)
6252#define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400)
6253#define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080)
6254#define RTC_TAMPCR_TAMP3_TRG ((uint32_t)0x00000040)
6255#define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020)
6256#define RTC_TAMPCR_TAMP2_TRG ((uint32_t)0x00000010)
6257#define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008)
6258#define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004)
6259#define RTC_TAMPCR_TAMP1_TRG ((uint32_t)0x00000002)
6260#define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001)
6261
6262/******************** Bits definition for RTC_ALRMASSR register *************/
6263#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
6264#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
6265#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
6266#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
6267#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
6268#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
6269
6270/******************** Bits definition for RTC_ALRMBSSR register *************/
6271#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
6272#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
6273#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
6274#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
6275#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
6276#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
6277
6278/******************** Bits definition for RTC_OR register ****************/
6279#define RTC_OR_TSINSEL ((uint32_t)0x00000006)
6280#define RTC_OR_TSINSEL_0 ((uint32_t)0x00000002)
6281#define RTC_OR_TSINSEL_1 ((uint32_t)0x00000004)
6282#define RTC_OR_ALARMTYPE ((uint32_t)0x00000008)
6283
6284
6285/******************** Bits definition for RTC_BKP0R register ****************/
6286#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
6287
6288/******************** Bits definition for RTC_BKP1R register ****************/
6289#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
6290
6291/******************** Bits definition for RTC_BKP2R register ****************/
6292#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
6293
6294/******************** Bits definition for RTC_BKP3R register ****************/
6295#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
6296
6297/******************** Bits definition for RTC_BKP4R register ****************/
6298#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
6299
6300/******************** Bits definition for RTC_BKP5R register ****************/
6301#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
6302
6303/******************** Bits definition for RTC_BKP6R register ****************/
6304#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
6305
6306/******************** Bits definition for RTC_BKP7R register ****************/
6307#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
6308
6309/******************** Bits definition for RTC_BKP8R register ****************/
6310#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
6311
6312/******************** Bits definition for RTC_BKP9R register ****************/
6313#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
6314
6315/******************** Bits definition for RTC_BKP10R register ***************/
6316#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
6317
6318/******************** Bits definition for RTC_BKP11R register ***************/
6319#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
6320
6321/******************** Bits definition for RTC_BKP12R register ***************/
6322#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
6323
6324/******************** Bits definition for RTC_BKP13R register ***************/
6325#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
6326
6327/******************** Bits definition for RTC_BKP14R register ***************/
6328#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
6329
6330/******************** Bits definition for RTC_BKP15R register ***************/
6331#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
6332
6333/******************** Bits definition for RTC_BKP16R register ***************/
6334#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
6335
6336/******************** Bits definition for RTC_BKP17R register ***************/
6337#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
6338
6339/******************** Bits definition for RTC_BKP18R register ***************/
6340#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
6341
6342/******************** Bits definition for RTC_BKP19R register ***************/
6343#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
6344
6345/******************** Bits definition for RTC_BKP20R register ***************/
6346#define RTC_BKP20R ((uint32_t)0xFFFFFFFF)
6347
6348/******************** Bits definition for RTC_BKP21R register ***************/
6349#define RTC_BKP21R ((uint32_t)0xFFFFFFFF)
6350
6351/******************** Bits definition for RTC_BKP22R register ***************/
6352#define RTC_BKP22R ((uint32_t)0xFFFFFFFF)
6353
6354/******************** Bits definition for RTC_BKP23R register ***************/
6355#define RTC_BKP23R ((uint32_t)0xFFFFFFFF)
6356
6357/******************** Bits definition for RTC_BKP24R register ***************/
6358#define RTC_BKP24R ((uint32_t)0xFFFFFFFF)
6359
6360/******************** Bits definition for RTC_BKP25R register ***************/
6361#define RTC_BKP25R ((uint32_t)0xFFFFFFFF)
6362
6363/******************** Bits definition for RTC_BKP26R register ***************/
6364#define RTC_BKP26R ((uint32_t)0xFFFFFFFF)
6365
6366/******************** Bits definition for RTC_BKP27R register ***************/
6367#define RTC_BKP27R ((uint32_t)0xFFFFFFFF)
6368
6369/******************** Bits definition for RTC_BKP28R register ***************/
6370#define RTC_BKP28R ((uint32_t)0xFFFFFFFF)
6371
6372/******************** Bits definition for RTC_BKP29R register ***************/
6373#define RTC_BKP29R ((uint32_t)0xFFFFFFFF)
6374
6375/******************** Bits definition for RTC_BKP30R register ***************/
6376#define RTC_BKP30R ((uint32_t)0xFFFFFFFF)
6377
6378/******************** Bits definition for RTC_BKP31R register ***************/
6379#define RTC_BKP31R ((uint32_t)0xFFFFFFFF)
6380
6381/******************** Number of backup registers ******************************/
6382#define RTC_BKP_NUMBER ((uint32_t)0x00000020)
6383
6384
6385/******************************************************************************/
6386/* */
6387/* Serial Audio Interface */
6388/* */
6389/******************************************************************************/
6390/******************** Bit definition for SAI_GCR register *******************/
6391#define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
6392#define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /*!<Bit 0 */
6393#define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /*!<Bit 1 */
6394
6395#define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
6396#define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /*!<Bit 0 */
6397#define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /*!<Bit 1 */
6398
6399/******************* Bit definition for SAI_xCR1 register *******************/
6400#define SAI_xCR1_MODE ((uint32_t)0x00000003) /*!<MODE[1:0] bits (Audio Block Mode) */
6401#define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
6402#define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
6403
6404#define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /*!<PRTCFG[1:0] bits (Protocol Configuration) */
6405#define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /*!<Bit 0 */
6406#define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /*!<Bit 1 */
6407
6408#define SAI_xCR1_DS ((uint32_t)0x000000E0) /*!<DS[1:0] bits (Data Size) */
6409#define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
6410#define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
6411#define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
6412
6413#define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /*!<LSB First Configuration */
6414#define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /*!<ClocK STRobing edge */
6415
6416#define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /*!<SYNCEN[1:0](SYNChronization ENable) */
6417#define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /*!<Bit 0 */
6418#define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /*!<Bit 1 */
6419
6420#define SAI_xCR1_MONO ((uint32_t)0x00001000) /*!<Mono mode */
6421#define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /*!<Output Drive */
6422#define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /*!<Audio Block enable */
6423#define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
6424#define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
6425
6426#define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
6427#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
6428#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
6429#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
6430#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
6431
6432/******************* Bit definition for SAI_xCR2 register *******************/
6433#define SAI_xCR2_FTH ((uint32_t)0x00000007) /*!<FTH[2:0](Fifo THreshold) */
6434#define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
6435#define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
6436#define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
6437
6438#define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
6439#define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
6440#define SAI_xCR2_MUTE ((uint32_t)0x00000020) /*!<Mute mode */
6441#define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /*!<Muate value */
6442
6443#define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /*!<MUTECNT[5:0] (MUTE counter) */
6444#define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /*!<Bit 0 */
6445#define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /*!<Bit 1 */
6446#define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /*!<Bit 2 */
6447#define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /*!<Bit 3 */
6448#define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */
6449#define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */
6450
6451#define SAI_xCR2_CPL ((uint32_t)0x00080000) /*!< Complement Bit */
6452
6453#define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */
6454#define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */
6455#define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /*!<Bit 1 */
6456
6457/****************** Bit definition for SAI_xFRCR register *******************/
6458#define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /*!<FRL[1:0](Frame length) */
6459#define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
6460#define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
6461#define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
6462#define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /*!<Bit 3 */
6463#define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /*!<Bit 4 */
6464#define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /*!<Bit 5 */
6465#define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /*!<Bit 6 */
6466#define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /*!<Bit 7 */
6467
6468#define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /*!<FRL[1:0] (Frame synchronization active level length) */
6469#define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
6470#define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
6471#define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
6472#define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
6473#define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
6474#define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
6475#define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
6476
6477#define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /*!< Frame Synchronization Definition */
6478#define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /*!<Frame Synchronization POLarity */
6479#define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /*!<Frame Synchronization OFFset */
6480
6481/****************** Bit definition for SAI_xSLOTR register *******************/
6482#define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /*!<FRL[4:0](First Bit Offset) */
6483#define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /*!<Bit 0 */
6484#define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /*!<Bit 1 */
6485#define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /*!<Bit 2 */
6486#define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /*!<Bit 3 */
6487#define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /*!<Bit 4 */
6488
6489#define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /*!<SLOTSZ[1:0] (Slot size) */
6490#define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /*!<Bit 0 */
6491#define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /*!<Bit 1 */
6492
6493#define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
6494#define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /*!<Bit 0 */
6495#define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /*!<Bit 1 */
6496#define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /*!<Bit 2 */
6497#define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /*!<Bit 3 */
6498
6499#define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /*!<SLOTEN[15:0] (Slot Enable) */
6500
6501/******************* Bit definition for SAI_xIMR register *******************/
6502#define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /*!<Overrun underrun interrupt enable */
6503#define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /*!<Mute detection interrupt enable */
6504#define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /*!<Wrong Clock Configuration interrupt enable */
6505#define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /*!<FIFO request interrupt enable */
6506#define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /*!<Codec not ready interrupt enable */
6507#define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection interrupt enable */
6508#define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /*!<Late frame synchronization detection interrupt enable */
6509
6510/******************** Bit definition for SAI_xSR register *******************/
6511#define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /*!<Overrun underrun */
6512#define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /*!<Mute detection */
6513#define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /*!<Wrong Clock Configuration */
6514#define SAI_xSR_FREQ ((uint32_t)0x00000008) /*!<FIFO request */
6515#define SAI_xSR_CNRDY ((uint32_t)0x00000010) /*!<Codec not ready */
6516#define SAI_xSR_AFSDET ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection */
6517#define SAI_xSR_LFSDET ((uint32_t)0x00000040) /*!<Late frame synchronization detection */
6518
6519#define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
6520#define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
6521#define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
6522#define SAI_xSR_FLVL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
6523
6524/****************** Bit definition for SAI_xCLRFR register ******************/
6525#define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */
6526#define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /*!<Clear Mute detection */
6527#define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /*!<Clear Wrong Clock Configuration */
6528#define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /*!<Clear FIFO request */
6529#define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /*!<Clear Codec not ready */
6530#define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /*!<Clear Anticipated frame synchronization detection */
6531#define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /*!<Clear Late frame synchronization detection */
6532
6533/****************** Bit definition for SAI_xDR register *********************/
6534#define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF)
6535
6536/******************************************************************************/
6537/* */
6538/* SPDIF-RX Interface */
6539/* */
6540/******************************************************************************/
6541/******************** Bit definition for SPDIF_CR register *******************/
6542#define SPDIFRX_CR_SPDIFEN ((uint32_t)0x00000003) /*!<Peripheral Block Enable */
6543#define SPDIFRX_CR_RXDMAEN ((uint32_t)0x00000004) /*!<Receiver DMA Enable for data flow */
6544#define SPDIFRX_CR_RXSTEO ((uint32_t)0x00000008) /*!<Stereo Mode */
6545#define SPDIFRX_CR_DRFMT ((uint32_t)0x00000030) /*!<RX Data format */
6546#define SPDIFRX_CR_PMSK ((uint32_t)0x00000040) /*!<Mask Parity error bit */
6547#define SPDIFRX_CR_VMSK ((uint32_t)0x00000080) /*!<Mask of Validity bit */
6548#define SPDIFRX_CR_CUMSK ((uint32_t)0x00000100) /*!<Mask of channel status and user bits */
6549#define SPDIFRX_CR_PTMSK ((uint32_t)0x00000200) /*!<Mask of Preamble Type bits */
6550#define SPDIFRX_CR_CBDMAEN ((uint32_t)0x00000400) /*!<Control Buffer DMA ENable for control flow */
6551#define SPDIFRX_CR_CHSEL ((uint32_t)0x00000800) /*!<Channel Selection */
6552#define SPDIFRX_CR_NBTR ((uint32_t)0x00003000) /*!<Maximum allowed re-tries during synchronization phase */
6553#define SPDIFRX_CR_WFA ((uint32_t)0x00004000) /*!<Wait For Activity */
6554#define SPDIFRX_CR_INSEL ((uint32_t)0x00070000) /*!<SPDIF input selection */
6555
6556/******************* Bit definition for SPDIFRX_IMR register *******************/
6557#define SPDIFRX_IMR_RXNEIE ((uint32_t)0x00000001) /*!<RXNE interrupt enable */
6558#define SPDIFRX_IMR_CSRNEIE ((uint32_t)0x00000002) /*!<Control Buffer Ready Interrupt Enable */
6559#define SPDIFRX_IMR_PERRIE ((uint32_t)0x00000004) /*!<Parity error interrupt enable */
6560#define SPDIFRX_IMR_OVRIE ((uint32_t)0x00000008) /*!<Overrun error Interrupt Enable */
6561#define SPDIFRX_IMR_SBLKIE ((uint32_t)0x00000010) /*!<Synchronization Block Detected Interrupt Enable */
6562#define SPDIFRX_IMR_SYNCDIE ((uint32_t)0x00000020) /*!<Synchronization Done */
6563#define SPDIFRX_IMR_IFEIE ((uint32_t)0x00000040) /*!<Serial Interface Error Interrupt Enable */
6564
6565/******************* Bit definition for SPDIFRX_SR register *******************/
6566#define SPDIFRX_SR_RXNE ((uint32_t)0x00000001) /*!<Read data register not empty */
6567#define SPDIFRX_SR_CSRNE ((uint32_t)0x00000002) /*!<The Control Buffer register is not empty */
6568#define SPDIFRX_SR_PERR ((uint32_t)0x00000004) /*!<Parity error */
6569#define SPDIFRX_SR_OVR ((uint32_t)0x00000008) /*!<Overrun error */
6570#define SPDIFRX_SR_SBD ((uint32_t)0x00000010) /*!<Synchronization Block Detected */
6571#define SPDIFRX_SR_SYNCD ((uint32_t)0x00000020) /*!<Synchronization Done */
6572#define SPDIFRX_SR_FERR ((uint32_t)0x00000040) /*!<Framing error */
6573#define SPDIFRX_SR_SERR ((uint32_t)0x00000080) /*!<Synchronization error */
6574#define SPDIFRX_SR_TERR ((uint32_t)0x00000100) /*!<Time-out error */
6575#define SPDIFRX_SR_WIDTH5 ((uint32_t)0x7FFF0000) /*!<Duration of 5 symbols counted with spdif_clk */
6576
6577/******************* Bit definition for SPDIFRX_IFCR register *******************/
6578#define SPDIFRX_IFCR_PERRCF ((uint32_t)0x00000004) /*!<Clears the Parity error flag */
6579#define SPDIFRX_IFCR_OVRCF ((uint32_t)0x00000008) /*!<Clears the Overrun error flag */
6580#define SPDIFRX_IFCR_SBDCF ((uint32_t)0x00000010) /*!<Clears the Synchronization Block Detected flag */
6581#define SPDIFRX_IFCR_SYNCDCF ((uint32_t)0x00000020) /*!<Clears the Synchronization Done flag */
6582
6583/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
6584#define SPDIFRX_DR0_DR ((uint32_t)0x00FFFFFF) /*!<Data value */
6585#define SPDIFRX_DR0_PE ((uint32_t)0x01000000) /*!<Parity Error bit */
6586#define SPDIFRX_DR0_V ((uint32_t)0x02000000) /*!<Validity bit */
6587#define SPDIFRX_DR0_U ((uint32_t)0x04000000) /*!<User bit */
6588#define SPDIFRX_DR0_C ((uint32_t)0x08000000) /*!<Channel Status bit */
6589#define SPDIFRX_DR0_PT ((uint32_t)0x30000000) /*!<Preamble Type */
6590
6591/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
6592#define SPDIFRX_DR1_DR ((uint32_t)0xFFFFFF00) /*!<Data value */
6593#define SPDIFRX_DR1_PT ((uint32_t)0x00000030) /*!<Preamble Type */
6594#define SPDIFRX_DR1_C ((uint32_t)0x00000008) /*!<Channel Status bit */
6595#define SPDIFRX_DR1_U ((uint32_t)0x00000004) /*!<User bit */
6596#define SPDIFRX_DR1_V ((uint32_t)0x00000002) /*!<Validity bit */
6597#define SPDIFRX_DR1_PE ((uint32_t)0x00000001) /*!<Parity Error bit */
6598
6599/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
6600#define SPDIFRX_DR1_DRNL1 ((uint32_t)0xFFFF0000) /*!<Data value Channel B */
6601#define SPDIFRX_DR1_DRNL2 ((uint32_t)0x0000FFFF) /*!<Data value Channel A */
6602
6603/******************* Bit definition for SPDIFRX_CSR register *******************/
6604#define SPDIFRX_CSR_USR ((uint32_t)0x0000FFFF) /*!<User data information */
6605#define SPDIFRX_CSR_CS ((uint32_t)0x00FF0000) /*!<Channel A status information */
6606#define SPDIFRX_CSR_SOB ((uint32_t)0x01000000) /*!<Start Of Block */
6607
6608/******************* Bit definition for SPDIFRX_DIR register *******************/
6609#define SPDIFRX_DIR_THI ((uint32_t)0x000013FF) /*!<Threshold LOW */
6610#define SPDIFRX_DIR_TLO ((uint32_t)0x1FFF0000) /*!<Threshold HIGH */
6611
6612
6613/******************************************************************************/
6614/* */
6615/* SD host Interface */
6616/* */
6617/******************************************************************************/
6618/****************** Bit definition for SDMMC_POWER register ******************/
6619#define SDMMC_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
6620#define SDMMC_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
6621#define SDMMC_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
6622
6623/****************** Bit definition for SDMMC_CLKCR register ******************/
6624#define SDMMC_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
6625#define SDMMC_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
6626#define SDMMC_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
6627#define SDMMC_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
6628
6629#define SDMMC_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
6630#define SDMMC_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
6631#define SDMMC_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
6632
6633#define SDMMC_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDMMC_CK dephasing selection bit */
6634#define SDMMC_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
6635
6636/******************* Bit definition for SDMMC_ARG register *******************/
6637#define SDMMC_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
6638
6639/******************* Bit definition for SDMMC_CMD register *******************/
6640#define SDMMC_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
6641
6642#define SDMMC_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
6643#define SDMMC_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
6644#define SDMMC_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
6645
6646#define SDMMC_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
6647#define SDMMC_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
6648#define SDMMC_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
6649#define SDMMC_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
6650
6651/***************** Bit definition for SDMMC_RESPCMD register *****************/
6652#define SDMMC_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
6653
6654/****************** Bit definition for SDMMC_RESP0 register ******************/
6655#define SDMMC_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
6656
6657/****************** Bit definition for SDMMC_RESP1 register ******************/
6658#define SDMMC_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
6659
6660/****************** Bit definition for SDMMC_RESP2 register ******************/
6661#define SDMMC_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
6662
6663/****************** Bit definition for SDMMC_RESP3 register ******************/
6664#define SDMMC_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
6665
6666/****************** Bit definition for SDMMC_RESP4 register ******************/
6667#define SDMMC_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
6668
6669/****************** Bit definition for SDMMC_DTIMER register *****************/
6670#define SDMMC_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
6671
6672/****************** Bit definition for SDMMC_DLEN register *******************/
6673#define SDMMC_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
6674
6675/****************** Bit definition for SDMMC_DCTRL register ******************/
6676#define SDMMC_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
6677#define SDMMC_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
6678#define SDMMC_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
6679#define SDMMC_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
6680
6681#define SDMMC_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
6682#define SDMMC_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
6683#define SDMMC_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
6684#define SDMMC_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
6685#define SDMMC_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
6686
6687#define SDMMC_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
6688#define SDMMC_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
6689#define SDMMC_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
6690#define SDMMC_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
6691
6692/****************** Bit definition for SDMMC_DCOUNT register *****************/
6693#define SDMMC_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
6694
6695/****************** Bit definition for SDMMC_STA register ********************/
6696#define SDMMC_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
6697#define SDMMC_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
6698#define SDMMC_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
6699#define SDMMC_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
6700#define SDMMC_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
6701#define SDMMC_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
6702#define SDMMC_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
6703#define SDMMC_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
6704#define SDMMC_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
6705#define SDMMC_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
6706#define SDMMC_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
6707#define SDMMC_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
6708#define SDMMC_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
6709#define SDMMC_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
6710#define SDMMC_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
6711#define SDMMC_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
6712#define SDMMC_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
6713#define SDMMC_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
6714#define SDMMC_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
6715#define SDMMC_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
6716#define SDMMC_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
6717#define SDMMC_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDMMC interrupt received */
6718
6719/******************* Bit definition for SDMMC_ICR register *******************/
6720#define SDMMC_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
6721#define SDMMC_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
6722#define SDMMC_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
6723#define SDMMC_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
6724#define SDMMC_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
6725#define SDMMC_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
6726#define SDMMC_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
6727#define SDMMC_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
6728#define SDMMC_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
6729#define SDMMC_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
6730#define SDMMC_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDMMCIT flag clear bit */
6731
6732/****************** Bit definition for SDMMC_MASK register *******************/
6733#define SDMMC_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
6734#define SDMMC_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
6735#define SDMMC_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
6736#define SDMMC_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
6737#define SDMMC_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
6738#define SDMMC_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
6739#define SDMMC_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
6740#define SDMMC_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
6741#define SDMMC_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
6742#define SDMMC_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
6743#define SDMMC_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
6744#define SDMMC_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
6745#define SDMMC_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
6746#define SDMMC_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
6747#define SDMMC_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
6748#define SDMMC_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
6749#define SDMMC_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
6750#define SDMMC_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
6751#define SDMMC_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
6752#define SDMMC_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
6753#define SDMMC_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
6754#define SDMMC_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDMMC Mode Interrupt Received interrupt Enable */
6755
6756/***************** Bit definition for SDMMC_FIFOCNT register *****************/
6757#define SDMMC_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
6758
6759/****************** Bit definition for SDMMC_FIFO register *******************/
6760#define SDMMC_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
6761
6762/******************************************************************************/
6763/* */
6764/* Serial Peripheral Interface (SPI) */
6765/* */
6766/******************************************************************************/
6767/******************* Bit definition for SPI_CR1 register ********************/
6768#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
6769#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
6770#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
6771#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
6772#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
6773#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
6774#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
6775#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
6776#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
6777#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
6778#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
6779#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
6780#define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
6781#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
6782#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
6783#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
6784#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
6785
6786/******************* Bit definition for SPI_CR2 register ********************/
6787#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
6788#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
6789#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
6790#define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
6791#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
6792#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
6793#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
6794#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
6795#define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
6796#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
6797#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
6798#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
6799#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
6800#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
6801#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
6802#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
6803
6804/******************** Bit definition for SPI_SR register ********************/
6805#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
6806#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
6807#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
6808#define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
6809#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
6810#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
6811#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
6812#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
6813#define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
6814#define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
6815#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
6816#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
6817#define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
6818#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
6819#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
6820
6821/******************** Bit definition for SPI_DR register ********************/
6822#define SPI_DR_DR ((uint32_t)0xFFFF) /*!< Data Register */
6823
6824/******************* Bit definition for SPI_CRCPR register ******************/
6825#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFF) /*!< CRC polynomial register */
6826
6827/****************** Bit definition for SPI_RXCRCR register ******************/
6828#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFF) /*!< Rx CRC Register */
6829
6830/****************** Bit definition for SPI_TXCRCR register ******************/
6831#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFF) /*!< Tx CRC Register */
6832
6833/****************** Bit definition for SPI_I2SCFGR register *****************/
6834#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
6835#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
6836#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
6837#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
6838#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
6839#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
6840#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
6841#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
6842#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
6843#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
6844#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
6845#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
6846#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
6847#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
6848#define SPI_I2SCFGR_ASTRTEN ((uint32_t)0x00001000) /*!<Asynchronous start enable */
6849
6850/****************** Bit definition for SPI_I2SPR register *******************/
6851#define SPI_I2SPR_I2SDIV ((uint32_t)0x00FF) /*!<I2S Linear prescaler */
6852#define SPI_I2SPR_ODD ((uint32_t)0x0100) /*!<Odd factor for the prescaler */
6853#define SPI_I2SPR_MCKOE ((uint32_t)0x0200) /*!<Master Clock Output Enable */
6854
6855
6856/******************************************************************************/
6857/* */
6858/* SYSCFG */
6859/* */
6860/******************************************************************************/
6861/****************** Bit definition for SYSCFG_MEMRMP register ***************/
6862#define SYSCFG_MEMRMP_MEM_BOOT ((uint32_t)0x00000001) /*!< Boot information after Reset */
6863
6864#define SYSCFG_MEMRMP_SWP_FMC ((uint32_t)0x00000C00) /*!< FMC Memory Mapping swapping */
6865#define SYSCFG_MEMRMP_SWP_FMC_0 ((uint32_t)0x00000400)
6866#define SYSCFG_MEMRMP_SWP_FMC_1 ((uint32_t)0x00000800)
6867
6868/****************** Bit definition for SYSCFG_PMC register ******************/
6869#define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */
6870#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
6871#define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */
6872#define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */
6873
6874#define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
6875
6876/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
6877#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
6878#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
6879#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
6880#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
6881/**
6882 * @brief EXTI0 configuration
6883 */
6884#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
6885#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
6886#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
6887#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
6888#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
6889#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
6890#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
6891#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
6892#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
6893#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x0009) /*!<PJ[0] pin */
6894#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x000A) /*!<PK[0] pin */
6895
6896/**
6897 * @brief EXTI1 configuration
6898 */
6899#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
6900#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
6901#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
6902#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
6903#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
6904#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
6905#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
6906#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
6907#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
6908#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x0090) /*!<PJ[1] pin */
6909#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x00A0) /*!<PK[1] pin */
6910
6911/**
6912 * @brief EXTI2 configuration
6913 */
6914#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
6915#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
6916#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
6917#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
6918#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
6919#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
6920#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
6921#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
6922#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
6923#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x0900) /*!<PJ[2] pin */
6924#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x0A00) /*!<PK[2] pin */
6925
6926/**
6927 * @brief EXTI3 configuration
6928 */
6929#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
6930#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
6931#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
6932#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
6933#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
6934#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
6935#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
6936#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
6937#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
6938#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x9000) /*!<PJ[3] pin */
6939#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0xA000) /*!<PK[3] pin */
6940
6941/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
6942#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
6943#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
6944#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
6945#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
6946/**
6947 * @brief EXTI4 configuration
6948 */
6949#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
6950#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
6951#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
6952#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
6953#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
6954#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
6955#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
6956#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
6957#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
6958#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x0009) /*!<PJ[4] pin */
6959#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x000A) /*!<PK[4] pin */
6960
6961/**
6962 * @brief EXTI5 configuration
6963 */
6964#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
6965#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
6966#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
6967#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
6968#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
6969#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
6970#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
6971#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
6972#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
6973#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x0090) /*!<PJ[5] pin */
6974#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x00A0) /*!<PK[5] pin */
6975
6976/**
6977 * @brief EXTI6 configuration
6978 */
6979#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
6980#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
6981#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
6982#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
6983#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
6984#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
6985#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
6986#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
6987#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
6988#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x0900) /*!<PJ[6] pin */
6989#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x0A00) /*!<PK[6] pin */
6990
6991/**
6992 * @brief EXTI7 configuration
6993 */
6994#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
6995#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
6996#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
6997#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
6998#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
6999#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
7000#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
7001#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
7002#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
7003#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x9000) /*!<PJ[7] pin */
7004#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0xA000) /*!<PK[7] pin */
7005
7006/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
7007#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
7008#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
7009#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
7010#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
7011
7012/**
7013 * @brief EXTI8 configuration
7014 */
7015#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
7016#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
7017#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
7018#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
7019#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
7020#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
7021#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
7022#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
7023#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
7024#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x0009) /*!<PJ[8] pin */
7025
7026/**
7027 * @brief EXTI9 configuration
7028 */
7029#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
7030#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
7031#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
7032#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
7033#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
7034#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
7035#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
7036#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
7037#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
7038#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x0090) /*!<PJ[9] pin */
7039
7040/**
7041 * @brief EXTI10 configuration
7042 */
7043#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
7044#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
7045#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
7046#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
7047#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
7048#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
7049#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
7050#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
7051#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
7052#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x0900) /*!<PJ[10] pin */
7053
7054/**
7055 * @brief EXTI11 configuration
7056 */
7057#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
7058#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
7059#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
7060#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
7061#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
7062#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
7063#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
7064#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
7065#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
7066#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x9000) /*!<PJ[11] pin */
7067
7068
7069/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
7070#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
7071#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
7072#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
7073#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
7074/**
7075 * @brief EXTI12 configuration
7076 */
7077#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
7078#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
7079#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
7080#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
7081#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
7082#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
7083#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
7084#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
7085#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x0008) /*!<PI[12] pin */
7086#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x0009) /*!<PJ[12] pin */
7087
7088/**
7089 * @brief EXTI13 configuration
7090 */
7091#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
7092#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
7093#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
7094#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
7095#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
7096#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
7097#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
7098#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
7099#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x0008) /*!<PI[13] pin */
7100#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x0009) /*!<PJ[13] pin */
7101
7102/**
7103 * @brief EXTI14 configuration
7104 */
7105#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
7106#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
7107#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
7108#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
7109#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
7110#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
7111#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
7112#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
7113#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x0800) /*!<PI[14] pin */
7114#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x0900) /*!<PJ[14] pin */
7115
7116/**
7117 * @brief EXTI15 configuration
7118 */
7119#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
7120#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
7121#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
7122#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
7123#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
7124#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
7125#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
7126#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
7127#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x8000) /*!<PI[15] pin */
7128#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x9000) /*!<PJ[15] pin */
7129
7130/****************** Bit definition for SYSCFG_CMPCR register ****************/
7131#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell power-down */
7132#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell ready flag*/
7133
7134/******************************************************************************/
7135/* */
7136/* TIM */
7137/* */
7138/******************************************************************************/
7139/******************* Bit definition for TIM_CR1 register ********************/
7140#define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
7141#define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
7142#define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
7143#define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
7144#define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
7145
7146#define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
7147#define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
7148#define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
7149
7150#define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
7151
7152#define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
7153#define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
7154#define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
7155#define TIM_CR1_UIFREMAP ((uint32_t)0x0800) /*!<UIF status bit */
7156
7157/******************* Bit definition for TIM_CR2 register ********************/
7158#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
7159#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
7160#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
7161
7162#define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */
7163#define TIM_CR2_OIS6 ((uint32_t)0x00040000) /*!<Output Idle state 4 (OC4 output) */
7164
7165#define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
7166#define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
7167#define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
7168#define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
7169
7170#define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */
7171#define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
7172#define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
7173#define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
7174#define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */
7175
7176#define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
7177#define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
7178#define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
7179#define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
7180#define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
7181#define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
7182#define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
7183#define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
7184
7185/******************* Bit definition for TIM_SMCR register *******************/
7186#define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */
7187#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
7188#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
7189#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
7190#define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */
7191#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
7192
7193#define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
7194#define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
7195#define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
7196#define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
7197
7198#define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
7199
7200#define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
7201#define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
7202#define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
7203#define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
7204#define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
7205
7206#define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
7207#define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
7208#define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
7209
7210
7211#define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
7212#define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
7213
7214/******************* Bit definition for TIM_DIER register *******************/
7215#define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
7216#define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
7217#define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
7218#define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
7219#define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
7220#define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
7221#define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
7222#define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
7223#define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
7224#define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
7225#define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
7226#define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
7227#define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
7228#define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
7229#define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
7230
7231/******************** Bit definition for TIM_SR register ********************/
7232#define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
7233#define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
7234#define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
7235#define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
7236#define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
7237#define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
7238#define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
7239#define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
7240#define TIM_SR_B2IF ((uint32_t)0x0100) /*!<Break2 interrupt Flag */
7241#define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
7242#define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
7243#define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
7244#define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
7245
7246/******************* Bit definition for TIM_EGR register ********************/
7247#define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
7248#define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
7249#define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
7250#define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
7251#define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
7252#define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
7253#define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
7254#define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
7255#define TIM_EGR_B2G ((uint32_t)0x00000100) /*!<Break2 Generation */
7256
7257/****************** Bit definition for TIM_CCMR1 register *******************/
7258#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
7259#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
7260#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
7261
7262#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
7263#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
7264
7265#define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
7266#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
7267#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
7268#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
7269#define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
7270
7271#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
7272
7273#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
7274#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
7275#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
7276
7277#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
7278#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
7279
7280#define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
7281#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
7282#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
7283#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
7284#define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
7285
7286#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
7287
7288/*----------------------------------------------------------------------------*/
7289
7290#define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
7291#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
7292#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
7293
7294#define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
7295#define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
7296#define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
7297#define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
7298#define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
7299
7300#define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
7301#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
7302#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
7303
7304#define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
7305#define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
7306#define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
7307#define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
7308#define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
7309
7310/****************** Bit definition for TIM_CCMR2 register *******************/
7311#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
7312#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
7313#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
7314
7315#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
7316#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
7317
7318#define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
7319#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
7320#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
7321#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
7322#define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
7323
7324
7325
7326#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
7327
7328#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
7329#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
7330#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
7331
7332#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
7333#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
7334
7335#define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
7336#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
7337#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
7338#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
7339#define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
7340
7341#define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
7342
7343/*----------------------------------------------------------------------------*/
7344
7345#define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
7346#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
7347#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
7348
7349#define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
7350#define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
7351#define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
7352#define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
7353#define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
7354
7355#define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
7356#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
7357#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
7358
7359#define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
7360#define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
7361#define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
7362#define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
7363#define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
7364
7365/******************* Bit definition for TIM_CCER register *******************/
7366#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
7367#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
7368#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
7369#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
7370#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
7371#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
7372#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
7373#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
7374#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
7375#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
7376#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
7377#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
7378#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
7379#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
7380#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
7381#define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */
7382#define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */
7383#define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */
7384#define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */
7385
7386
7387/******************* Bit definition for TIM_CNT register ********************/
7388#define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
7389
7390/******************* Bit definition for TIM_PSC register ********************/
7391#define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
7392
7393/******************* Bit definition for TIM_ARR register ********************/
7394#define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
7395
7396/******************* Bit definition for TIM_RCR register ********************/
7397#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
7398
7399/******************* Bit definition for TIM_CCR1 register *******************/
7400#define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
7401
7402/******************* Bit definition for TIM_CCR2 register *******************/
7403#define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
7404
7405/******************* Bit definition for TIM_CCR3 register *******************/
7406#define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
7407
7408/******************* Bit definition for TIM_CCR4 register *******************/
7409#define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
7410
7411/******************* Bit definition for TIM_BDTR register *******************/
7412#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
7413#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
7414#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
7415#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
7416#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
7417#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
7418#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
7419#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
7420#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
7421
7422#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
7423#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
7424#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
7425
7426#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
7427#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
7428#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
7429#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
7430#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
7431#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
7432#define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */
7433#define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */
7434#define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */
7435#define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */
7436
7437/******************* Bit definition for TIM_DCR register ********************/
7438#define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
7439#define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
7440#define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
7441#define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
7442#define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
7443#define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
7444
7445#define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
7446#define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
7447#define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
7448#define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
7449#define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
7450#define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
7451
7452/******************* Bit definition for TIM_DMAR register *******************/
7453#define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
7454
7455/******************* Bit definition for TIM_OR register *********************/
7456#define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
7457#define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
7458#define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
7459#define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
7460#define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
7461#define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
7462
7463/****************** Bit definition for TIM_CCMR3 register *******************/
7464#define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */
7465#define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */
7466
7467#define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
7468#define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
7469#define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
7470#define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
7471#define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
7472
7473#define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */
7474
7475#define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
7476#define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
7477
7478#define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
7479#define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
7480#define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
7481#define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
7482#define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
7483
7484#define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
7485
7486/******************* Bit definition for TIM_CCR5 register *******************/
7487#define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */
7488#define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */
7489#define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */
7490#define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */
7491
7492/******************* Bit definition for TIM_CCR6 register *******************/
7493#define TIM_CCR6_CCR6 ((uint16_t)0xFFFF) /*!<Capture/Compare 6 Value */
7494
7495/******************************************************************************/
7496/* */
7497/* Low Power Timer (LPTIM) */
7498/* */
7499/******************************************************************************/
7500/****************** Bit definition for LPTIM_ISR register *******************/
7501#define LPTIM_ISR_CMPM ((uint32_t)0x00000001) /*!< Compare match */
7502#define LPTIM_ISR_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */
7503#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */
7504#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) /*!< Compare register update OK */
7505#define LPTIM_ISR_ARROK ((uint32_t)0x00000010) /*!< Autoreload register update OK */
7506#define LPTIM_ISR_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */
7507#define LPTIM_ISR_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */
7508
7509/****************** Bit definition for LPTIM_ICR register *******************/
7510#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */
7511#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */
7512#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */
7513#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */
7514#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */
7515#define LPTIM_ICR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */
7516#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */
7517
7518/****************** Bit definition for LPTIM_IER register ********************/
7519#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */
7520#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */
7521#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */
7522#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */
7523#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */
7524#define LPTIM_IER_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */
7525#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */
7526
7527/****************** Bit definition for LPTIM_CFGR register *******************/
7528#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) /*!< Clock selector */
7529
7530#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) /*!< CKPOL[1:0] bits (Clock polarity) */
7531#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002) /*!< Bit 0 */
7532#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004) /*!< Bit 1 */
7533
7534#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
7535#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008) /*!< Bit 0 */
7536#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010) /*!< Bit 1 */
7537
7538#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
7539#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040) /*!< Bit 0 */
7540#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080) /*!< Bit 1 */
7541
7542#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) /*!< PRESC[2:0] bits (Clock prescaler) */
7543#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200) /*!< Bit 0 */
7544#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400) /*!< Bit 1 */
7545#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800) /*!< Bit 2 */
7546
7547#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
7548#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000) /*!< Bit 0 */
7549#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000) /*!< Bit 1 */
7550#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000) /*!< Bit 2 */
7551
7552#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
7553#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000) /*!< Bit 0 */
7554#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000) /*!< Bit 1 */
7555
7556#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) /*!< Timout enable */
7557#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */
7558#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */
7559#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) /*!< Reg update mode */
7560#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000) /*!< Counter mode enable */
7561#define LPTIM_CFGR_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */
7562
7563/****************** Bit definition for LPTIM_CR register ********************/
7564#define LPTIM_CR_ENABLE ((uint32_t)0x00000001) /*!< LPTIMer enable */
7565#define LPTIM_CR_SNGSTRT ((uint32_t)0x00080002) /*!< Timer start in single mode */
7566#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) /*!< Timer start in continuous mode */
7567
7568/****************** Bit definition for LPTIM_CMP register *******************/
7569#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFF) /*!< Compare register */
7570
7571/****************** Bit definition for LPTIM_ARR register *******************/
7572#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!< Auto reload register */
7573
7574/****************** Bit definition for LPTIM_CNT register *******************/
7575#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!< Counter register */
7576/******************************************************************************/
7577/* */
7578/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
7579/* */
7580/******************************************************************************/
7581/****************** Bit definition for USART_CR1 register *******************/
7582#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
7583#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
7584#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
7585#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
7586#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
7587#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
7588#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
7589#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
7590#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
7591#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
7592#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
7593#define USART_CR1_M ((uint32_t)0x10001000) /*!< Word length */
7594#define USART_CR1_M_0 ((uint32_t)0x00001000) /*!< Word length - Bit 0 */
7595#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
7596#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
7597#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
7598#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
7599#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
7600#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
7601#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
7602#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
7603#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
7604#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
7605#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
7606#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
7607#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
7608#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
7609#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
7610#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
7611#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
7612#define USART_CR1_M_1 ((uint32_t)0x10000000) /*!< Word length - Bit 1 */
7613
7614/****************** Bit definition for USART_CR2 register *******************/
7615#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
7616#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
7617#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
7618#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
7619#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
7620#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
7621#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
7622#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
7623#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
7624#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
7625#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
7626#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
7627#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
7628#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
7629#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
7630#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
7631#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable */
7632#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
7633#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
7634#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
7635#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
7636#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
7637
7638/****************** Bit definition for USART_CR3 register *******************/
7639#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
7640#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
7641#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
7642#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
7643#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
7644#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
7645#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
7646#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
7647#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
7648#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
7649#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
7650#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
7651#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
7652#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
7653#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
7654#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
7655#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
7656#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
7657#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
7658#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
7659
7660/****************** Bit definition for USART_BRR register *******************/
7661#define USART_BRR_DIV_FRACTION ((uint32_t)0x000F) /*!< Fraction of USARTDIV */
7662#define USART_BRR_DIV_MANTISSA ((uint32_t)0xFFF0) /*!< Mantissa of USARTDIV */
7663
7664/****************** Bit definition for USART_GTPR register ******************/
7665#define USART_GTPR_PSC ((uint32_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
7666#define USART_GTPR_GT ((uint32_t)0xFF00) /*!< GT[7:0] bits (Guard time value) */
7667
7668
7669/******************* Bit definition for USART_RTOR register *****************/
7670#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
7671#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
7672
7673/******************* Bit definition for USART_RQR register ******************/
7674#define USART_RQR_ABRRQ ((uint32_t)0x0001) /*!< Auto-Baud Rate Request */
7675#define USART_RQR_SBKRQ ((uint32_t)0x0002) /*!< Send Break Request */
7676#define USART_RQR_MMRQ ((uint32_t)0x0004) /*!< Mute Mode Request */
7677#define USART_RQR_RXFRQ ((uint32_t)0x0008) /*!< Receive Data flush Request */
7678#define USART_RQR_TXFRQ ((uint32_t)0x0010) /*!< Transmit data flush Request */
7679
7680/******************* Bit definition for USART_ISR register ******************/
7681#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
7682#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
7683#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
7684#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
7685#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
7686#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
7687#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
7688#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
7689#define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
7690#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
7691#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
7692#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
7693#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
7694#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
7695#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
7696#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
7697#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
7698#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
7699#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
7700#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
7701#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
7702#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
7703
7704/******************* Bit definition for USART_ICR register ******************/
7705#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
7706#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
7707#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
7708#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
7709#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
7710#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
7711#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
7712#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
7713#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
7714#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
7715#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
7716#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
7717
7718/******************* Bit definition for USART_RDR register ******************/
7719#define USART_RDR_RDR ((uint32_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
7720
7721/******************* Bit definition for USART_TDR register ******************/
7722#define USART_TDR_TDR ((uint32_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
7723
7724/******************************************************************************/
7725/* */
7726/* Window WATCHDOG */
7727/* */
7728/******************************************************************************/
7729/******************* Bit definition for WWDG_CR register ********************/
7730#define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
7731#define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
7732#define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
7733#define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
7734#define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
7735#define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
7736#define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
7737#define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
7738
7739#define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
7740
7741/******************* Bit definition for WWDG_CFR register *******************/
7742#define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
7743#define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
7744#define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
7745#define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
7746#define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
7747#define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
7748#define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
7749#define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
7750
7751#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
7752#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
7753#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
7754
7755#define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
7756
7757/******************* Bit definition for WWDG_SR register ********************/
7758#define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
7759
7760/******************************************************************************/
7761/* */
7762/* DBG */
7763/* */
7764/******************************************************************************/
7765/******************** Bit definition for DBGMCU_IDCODE register *************/
7766#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
7767#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
7768
7769/******************** Bit definition for DBGMCU_CR register *****************/
7770#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
7771#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
7772#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
7773#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
7774
7775#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
7776#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!<Bit 0 */
7777#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!<Bit 1 */
7778
7779/******************** Bit definition for DBGMCU_APB1_FZ register ************/
7780#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
7781#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
7782#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
7783#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
7784#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
7785#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
7786#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
7787#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
7788#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
7789#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
7790#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
7791#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
7792#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
7793#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
7794#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
7795#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
7796#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
7797
7798/******************** Bit definition for DBGMCU_APB2_FZ register ************/
7799#define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
7800#define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
7801#define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
7802#define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
7803#define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
7804
7805/******************************************************************************/
7806/* */
7807/* Ethernet MAC Registers bits definitions */
7808/* */
7809/******************************************************************************/
7810/* Bit definition for Ethernet MAC Control Register register */
7811#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
7812#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
7813#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
7814#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
7815#define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
7816#define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
7817#define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
7818#define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
7819#define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
7820#define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
7821#define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
7822#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
7823#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
7824#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
7825#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
7826#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
7827#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
7828#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
7829#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
7830#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
7831 a transmission attempt during retries after a collision: 0 =< r <2^k */
7832#define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
7833#define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
7834#define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
7835#define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
7836#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
7837#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
7838#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
7839
7840/* Bit definition for Ethernet MAC Frame Filter Register */
7841#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
7842#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
7843#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
7844#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
7845#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
7846#define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
7847#define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
7848#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
7849#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
7850#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
7851#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
7852#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
7853#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
7854#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
7855
7856/* Bit definition for Ethernet MAC Hash Table High Register */
7857#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
7858
7859/* Bit definition for Ethernet MAC Hash Table Low Register */
7860#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
7861
7862/* Bit definition for Ethernet MAC MII Address Register */
7863#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
7864#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
7865#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
7866#define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
7867#define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
7868#define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
7869#define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
7870#define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
7871#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
7872#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
7873
7874/* Bit definition for Ethernet MAC MII Data Register */
7875#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
7876
7877/* Bit definition for Ethernet MAC Flow Control Register */
7878#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
7879#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
7880#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
7881#define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
7882#define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
7883#define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
7884#define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
7885#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
7886#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
7887#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
7888#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
7889
7890/* Bit definition for Ethernet MAC VLAN Tag Register */
7891#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
7892#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
7893
7894/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
7895#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
7896/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
7897 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
7898/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
7899 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
7900 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
7901 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
7902 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
7903 RSVD - Filter1 Command - RSVD - Filter0 Command
7904 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
7905 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
7906 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
7907
7908/* Bit definition for Ethernet MAC PMT Control and Status Register */
7909#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
7910#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
7911#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
7912#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
7913#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
7914#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
7915#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
7916
7917/* Bit definition for Ethernet MAC Status Register */
7918#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
7919#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
7920#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
7921#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
7922#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
7923
7924/* Bit definition for Ethernet MAC Interrupt Mask Register */
7925#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
7926#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
7927
7928/* Bit definition for Ethernet MAC Address0 High Register */
7929#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
7930
7931/* Bit definition for Ethernet MAC Address0 Low Register */
7932#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
7933
7934/* Bit definition for Ethernet MAC Address1 High Register */
7935#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
7936#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
7937#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
7938#define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
7939#define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
7940#define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
7941#define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
7942#define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
7943#define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
7944#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
7945
7946/* Bit definition for Ethernet MAC Address1 Low Register */
7947#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
7948
7949/* Bit definition for Ethernet MAC Address2 High Register */
7950#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
7951#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
7952#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
7953#define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
7954#define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
7955#define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
7956#define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
7957#define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
7958#define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
7959#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
7960
7961/* Bit definition for Ethernet MAC Address2 Low Register */
7962#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
7963
7964/* Bit definition for Ethernet MAC Address3 High Register */
7965#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
7966#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
7967#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
7968#define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
7969#define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
7970#define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
7971#define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
7972#define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
7973#define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
7974#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
7975
7976/* Bit definition for Ethernet MAC Address3 Low Register */
7977#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
7978
7979/******************************************************************************/
7980/* Ethernet MMC Registers bits definition */
7981/******************************************************************************/
7982
7983/* Bit definition for Ethernet MMC Contol Register */
7984#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
7985#define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
7986#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
7987#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
7988#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
7989#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
7990
7991/* Bit definition for Ethernet MMC Receive Interrupt Register */
7992#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
7993#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
7994#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
7995
7996/* Bit definition for Ethernet MMC Transmit Interrupt Register */
7997#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
7998#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
7999#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
8000
8001/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
8002#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
8003#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
8004#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
8005
8006/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
8007#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
8008#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
8009#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
8010
8011/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
8012#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
8013
8014/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
8015#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
8016
8017/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
8018#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
8019
8020/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
8021#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
8022
8023/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
8024#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
8025
8026/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
8027#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
8028
8029/******************************************************************************/
8030/* Ethernet PTP Registers bits definition */
8031/******************************************************************************/
8032
8033/* Bit definition for Ethernet PTP Time Stamp Contol Register */
8034#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
8035#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
8036#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
8037#define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
8038#define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
8039#define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
8040#define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
8041#define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
8042#define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
8043
8044#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
8045#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
8046#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
8047#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
8048#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
8049#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
8050
8051/* Bit definition for Ethernet PTP Sub-Second Increment Register */
8052#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
8053
8054/* Bit definition for Ethernet PTP Time Stamp High Register */
8055#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
8056
8057/* Bit definition for Ethernet PTP Time Stamp Low Register */
8058#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
8059#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
8060
8061/* Bit definition for Ethernet PTP Time Stamp High Update Register */
8062#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
8063
8064/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
8065#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
8066#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
8067
8068/* Bit definition for Ethernet PTP Time Stamp Addend Register */
8069#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
8070
8071/* Bit definition for Ethernet PTP Target Time High Register */
8072#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
8073
8074/* Bit definition for Ethernet PTP Target Time Low Register */
8075#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
8076
8077/* Bit definition for Ethernet PTP Time Stamp Status Register */
8078#define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
8079#define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
8080
8081/******************************************************************************/
8082/* Ethernet DMA Registers bits definition */
8083/******************************************************************************/
8084
8085/* Bit definition for Ethernet DMA Bus Mode Register */
8086#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
8087#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
8088#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
8089#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
8090#define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
8091#define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
8092#define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
8093#define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
8094#define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
8095#define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
8096#define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
8097#define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
8098#define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
8099#define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
8100#define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
8101#define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
8102#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
8103#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
8104#define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
8105#define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
8106#define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
8107#define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
8108#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
8109#define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
8110#define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
8111#define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
8112#define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
8113#define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
8114#define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
8115#define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
8116#define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
8117#define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
8118#define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
8119#define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
8120#define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
8121#define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
8122#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
8123#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
8124#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
8125
8126/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
8127#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
8128
8129/* Bit definition for Ethernet DMA Receive Poll Demand Register */
8130#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
8131
8132/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
8133#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
8134
8135/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
8136#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
8137
8138/* Bit definition for Ethernet DMA Status Register */
8139#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
8140#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
8141#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
8142#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
8143/* combination with EBS[2:0] for GetFlagStatus function */
8144#define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
8145#define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
8146#define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
8147#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
8148#define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
8149#define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
8150#define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
8151#define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
8152#define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
8153#define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
8154#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
8155#define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
8156#define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
8157#define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
8158#define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
8159#define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
8160#define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
8161#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
8162#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
8163#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
8164#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
8165#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
8166#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
8167#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
8168#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
8169#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
8170#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
8171#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
8172#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
8173#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
8174#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
8175#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
8176
8177/* Bit definition for Ethernet DMA Operation Mode Register */
8178#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
8179#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
8180#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
8181#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
8182#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
8183#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
8184#define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
8185#define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
8186#define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
8187#define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
8188#define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
8189#define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
8190#define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
8191#define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
8192#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
8193#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
8194#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
8195#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
8196#define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
8197#define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
8198#define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
8199#define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
8200#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
8201#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
8202
8203/* Bit definition for Ethernet DMA Interrupt Enable Register */
8204#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
8205#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
8206#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
8207#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
8208#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
8209#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
8210#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
8211#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
8212#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
8213#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
8214#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
8215#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
8216#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
8217#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
8218#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
8219
8220/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
8221#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
8222#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
8223#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
8224#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
8225
8226/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
8227#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
8228
8229/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
8230#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
8231
8232/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
8233#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
8234
8235/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
8236#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
8237
8238/******************************************************************************/
8239/* */
8240/* USB_OTG */
8241/* */
8242/******************************************************************************/
8243/******************** Bit definition for USB_OTG_GOTGCTL register ********************/
8244#define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
8245#define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
8246#define USB_OTG_GOTGCTL_VBVALOEN ((uint32_t)0x00000004) /*!< VBUS valid override enable */
8247#define USB_OTG_GOTGCTL_VBVALOVAL ((uint32_t)0x00000008) /*!< VBUS valid override value */
8248#define USB_OTG_GOTGCTL_AVALOEN ((uint32_t)0x00000010) /*!< A-peripheral session valid override enable */
8249#define USB_OTG_GOTGCTL_AVALOVAL ((uint32_t)0x00000020) /*!< A-peripheral session valid override value */
8250#define USB_OTG_GOTGCTL_BVALOEN ((uint32_t)0x00000040) /*!< B-peripheral session valid override enable */
8251#define USB_OTG_GOTGCTL_BVALOVAL ((uint32_t)0x00000080) /*!< B-peripheral session valid override value */
8252#define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host set HNP enable */
8253#define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
8254#define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
8255#define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
8256#define USB_OTG_GOTGCTL_EHEN ((uint32_t)0x00001000) /*!< Embedded host enable */
8257#define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
8258#define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
8259#define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
8260#define USB_OTG_GOTGCTL_BSESVLD ((uint32_t)0x00080000) /*!< B-session valid */
8261#define USB_OTG_GOTGCTL_OTGVER ((uint32_t)0x00100000) /*!< OTG version */
8262
8263/******************** Bit definition for USB_OTG_HCFG register ********************/
8264#define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
8265#define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
8266#define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
8267#define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
8268
8269/******************** Bit definition for USB_OTG_DCFG register ********************/
8270#define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
8271#define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
8272#define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
8273#define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
8274
8275#define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
8276#define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
8277#define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
8278#define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
8279#define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
8280#define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
8281#define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
8282#define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
8283
8284#define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
8285#define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
8286#define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
8287
8288#define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
8289#define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
8290#define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
8291
8292/******************** Bit definition for USB_OTG_PCGCR register ********************/
8293#define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
8294#define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
8295#define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
8296
8297/******************** Bit definition for USB_OTG_GOTGINT register ********************/
8298#define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
8299#define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
8300#define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
8301#define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
8302#define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
8303#define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
8304#define USB_OTG_GOTGINT_IDCHNG ((uint32_t)0x00100000) /*!< Change in ID pin input value */
8305
8306/******************** Bit definition for USB_OTG_DCTL register ********************/
8307#define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
8308#define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
8309#define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
8310#define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
8311
8312#define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
8313#define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
8314#define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
8315#define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
8316#define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
8317#define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
8318#define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
8319#define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
8320#define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
8321
8322/******************** Bit definition for USB_OTG_HFIR register ********************/
8323#define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
8324
8325/******************** Bit definition for USB_OTG_HFNUM register ********************/
8326#define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
8327#define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
8328
8329/******************** Bit definition for USB_OTG_DSTS register ********************/
8330#define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
8331
8332#define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
8333#define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
8334#define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
8335#define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
8336#define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
8337
8338/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
8339#define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
8340#define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
8341#define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
8342#define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
8343#define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
8344#define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
8345#define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
8346#define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
8347#define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
8348
8349/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
8350#define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
8351#define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
8352#define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
8353#define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
8354#define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
8355#define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
8356#define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
8357#define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
8358#define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
8359#define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
8360#define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
8361#define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
8362#define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
8363#define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
8364#define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
8365#define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
8366#define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
8367#define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
8368#define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
8369#define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
8370#define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
8371#define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
8372#define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
8373#define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
8374#define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
8375
8376/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
8377#define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
8378#define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
8379#define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
8380#define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
8381#define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
8382#define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
8383#define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
8384#define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
8385#define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
8386#define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
8387#define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
8388#define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
8389#define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
8390
8391/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
8392#define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
8393#define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
8394#define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
8395#define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
8396#define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
8397#define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
8398#define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
8399#define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
8400
8401/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
8402#define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
8403#define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
8404#define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
8405#define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
8406#define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
8407#define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
8408#define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
8409#define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
8410#define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
8411#define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
8412
8413#define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
8414#define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
8415#define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
8416#define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
8417#define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
8418#define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
8419#define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
8420#define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
8421#define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
8422
8423/******************** Bit definition for USB_OTG_HAINT register ********************/
8424#define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
8425
8426/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
8427#define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
8428#define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
8429#define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
8430#define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
8431#define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
8432#define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
8433#define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
8434
8435/******************** Bit definition for USB_OTG_GINTSTS register ********************/
8436#define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
8437#define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
8438#define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
8439#define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
8440#define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
8441#define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
8442#define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
8443#define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
8444#define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
8445#define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
8446#define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
8447#define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
8448#define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
8449#define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
8450#define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
8451#define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
8452#define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
8453#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
8454#define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
8455#define USB_OTG_GINTSTS_RSTDET ((uint32_t)0x00800000) /*!< Reset detected interrupt */
8456#define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
8457#define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
8458#define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
8459#define USB_OTG_GINTSTS_LPMINT ((uint32_t)0x08000000) /*!< LPM interrupt */
8460#define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
8461#define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
8462#define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
8463#define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
8464
8465/******************** Bit definition for USB_OTG_GINTMSK register ********************/
8466#define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
8467#define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
8468#define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
8469#define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
8470#define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
8471#define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
8472#define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
8473#define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
8474#define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
8475#define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
8476#define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
8477#define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
8478#define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
8479#define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
8480#define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
8481#define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
8482#define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
8483#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
8484#define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
8485#define USB_OTG_GINTMSK_RSTDEM ((uint32_t)0x00800000) /*!< Reset detected interrupt mask */
8486#define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
8487#define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
8488#define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
8489#define USB_OTG_GINTMSK_LPMINTM ((uint32_t)0x08000000) /*!< LPM interrupt Mask */
8490#define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
8491#define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
8492#define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
8493#define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
8494
8495/******************** Bit definition for USB_OTG_DAINT register ********************/
8496#define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
8497#define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
8498
8499/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
8500#define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
8501
8502/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
8503#define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
8504#define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
8505#define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
8506#define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
8507
8508/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
8509#define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
8510#define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
8511
8512/******************** Bit definition for OTG register ********************/
8513
8514#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
8515#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
8516#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
8517#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
8518#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
8519#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
8520
8521#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
8522#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
8523#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
8524
8525#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
8526#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
8527#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
8528#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
8529#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
8530
8531#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
8532#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
8533#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
8534#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
8535#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
8536
8537#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
8538#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
8539#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
8540#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
8541#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
8542
8543/******************** Bit definition for OTG register ********************/
8544
8545#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
8546#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
8547#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
8548#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
8549#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
8550#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
8551
8552#define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
8553#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
8554#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
8555
8556#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
8557#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
8558#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
8559#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
8560#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
8561
8562#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
8563#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
8564#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
8565#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
8566#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
8567
8568#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
8569#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
8570#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
8571#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
8572#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
8573
8574/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
8575#define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
8576
8577/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
8578#define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
8579
8580/******************** Bit definition for OTG register ********************/
8581#define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
8582#define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
8583#define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
8584#define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
8585
8586/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
8587#define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
8588
8589/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
8590#define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
8591
8592#define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
8593#define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
8594#define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
8595#define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
8596#define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
8597#define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
8598#define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
8599#define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
8600#define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
8601
8602#define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
8603#define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
8604#define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
8605#define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
8606#define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
8607#define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
8608#define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
8609#define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
8610
8611/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
8612#define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
8613#define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
8614
8615#define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
8616#define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
8617#define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
8618#define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
8619#define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
8620#define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
8621#define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
8622#define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
8623#define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
8624#define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
8625#define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
8626
8627#define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
8628#define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
8629#define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
8630#define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
8631#define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
8632#define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
8633#define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
8634#define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
8635#define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
8636#define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
8637#define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
8638
8639/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
8640#define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
8641
8642/******************** Bit definition for USB_OTG_DEACHINT register ********************/
8643#define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
8644#define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
8645
8646/******************** Bit definition for USB_OTG_GCCFG register ********************/
8647#define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
8648#define USB_OTG_GCCFG_VBDEN ((uint32_t)0x00200000) /*!< USB VBUS Detection Enable */
8649
8650/******************** Bit definition for USB_OTG_GPWRDN) register ********************/
8651#define USB_OTG_GPWRDN_ADPMEN ((uint32_t)0x00000001) /*!< ADP module enable */
8652#define USB_OTG_GPWRDN_ADPIF ((uint32_t)0x00800000) /*!< ADP Interrupt flag */
8653
8654/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
8655#define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
8656#define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
8657
8658/******************** Bit definition for USB_OTG_CID register ********************/
8659#define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
8660
8661/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
8662#define USB_OTG_GLPMCFG_LPMEN ((uint32_t)0x00000001) /*!< LPM support enable */
8663#define USB_OTG_GLPMCFG_LPMACK ((uint32_t)0x00000002) /*!< LPM Token acknowledge enable */
8664#define USB_OTG_GLPMCFG_BESL ((uint32_t)0x0000003C) /*!< BESL value received with last ACKed LPM Token */
8665#define USB_OTG_GLPMCFG_REMWAKE ((uint32_t)0x00000040) /*!< bRemoteWake value received with last ACKed LPM Token */
8666#define USB_OTG_GLPMCFG_L1SSEN ((uint32_t)0x00000080) /*!< L1 shallow sleep enable */
8667#define USB_OTG_GLPMCFG_BESLTHRS ((uint32_t)0x00000F00) /*!< BESL threshold */
8668#define USB_OTG_GLPMCFG_L1DSEN ((uint32_t)0x00001000) /*!< L1 deep sleep enable */
8669#define USB_OTG_GLPMCFG_LPMRSP ((uint32_t)0x00006000) /*!< LPM response */
8670#define USB_OTG_GLPMCFG_SLPSTS ((uint32_t)0x00008000) /*!< Port sleep status */
8671#define USB_OTG_GLPMCFG_L1RSMOK ((uint32_t)0x00010000) /*!< Sleep State Resume OK */
8672#define USB_OTG_GLPMCFG_LPMCHIDX ((uint32_t)0x001E0000) /*!< LPM Channel Index */
8673#define USB_OTG_GLPMCFG_LPMRCNT ((uint32_t)0x00E00000) /*!< LPM retry count */
8674#define USB_OTG_GLPMCFG_SNDLPM ((uint32_t)0x01000000) /*!< Send LPM transaction */
8675#define USB_OTG_GLPMCFG_LPMRCNTSTS ((uint32_t)0x0E000000) /*!< LPM retry count status */
8676#define USB_OTG_GLPMCFG_ENBESL ((uint32_t)0x10000000) /*!< Enable best effort service latency */
8677
8678/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
8679#define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
8680#define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
8681#define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
8682#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
8683#define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
8684#define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
8685#define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
8686#define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
8687#define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
8688
8689/******************** Bit definition for USB_OTG_HPRT register ********************/
8690#define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
8691#define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
8692#define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
8693#define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
8694#define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
8695#define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
8696#define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
8697#define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
8698#define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
8699
8700#define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
8701#define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
8702#define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
8703#define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
8704
8705#define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
8706#define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
8707#define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
8708#define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
8709#define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
8710
8711#define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
8712#define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
8713#define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
8714
8715/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
8716#define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
8717#define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
8718#define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
8719#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
8720#define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
8721#define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
8722#define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
8723#define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
8724#define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
8725#define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
8726#define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
8727
8728/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
8729#define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
8730#define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
8731
8732/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
8733#define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
8734#define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
8735#define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
8736#define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
8737
8738#define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
8739#define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
8740#define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
8741#define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
8742
8743#define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
8744#define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
8745#define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
8746#define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
8747#define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
8748#define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
8749#define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
8750#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
8751#define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
8752#define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
8753#define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
8754
8755/******************** Bit definition for USB_OTG_HCCHAR register ********************/
8756#define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
8757
8758#define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
8759#define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
8760#define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
8761#define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
8762#define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
8763#define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
8764#define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
8765
8766#define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
8767#define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
8768#define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
8769
8770#define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
8771#define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
8772#define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
8773
8774#define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
8775#define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
8776#define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
8777#define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
8778#define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
8779#define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
8780#define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
8781#define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
8782#define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
8783#define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
8784#define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
8785
8786/******************** Bit definition for USB_OTG_HCSPLT register ********************/
8787
8788#define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
8789#define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
8790#define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
8791#define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
8792#define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
8793#define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
8794#define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
8795#define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
8796
8797#define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
8798#define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
8799#define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
8800#define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
8801#define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
8802#define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
8803#define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
8804#define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
8805
8806#define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
8807#define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
8808#define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
8809#define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
8810#define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
8811
8812/******************** Bit definition for USB_OTG_HCINT register ********************/
8813#define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
8814#define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
8815#define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
8816#define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
8817#define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
8818#define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
8819#define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
8820#define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
8821#define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
8822#define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
8823#define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
8824
8825/******************** Bit definition for USB_OTG_DIEPINT register ********************/
8826#define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
8827#define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
8828#define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
8829#define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
8830#define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
8831#define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
8832#define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
8833#define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
8834#define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
8835#define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
8836#define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
8837
8838/******************** Bit definition for USB_OTG_HCINTMSK register ********************/
8839#define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
8840#define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
8841#define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
8842#define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
8843#define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
8844#define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
8845#define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
8846#define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
8847#define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
8848#define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
8849#define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
8850
8851/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
8852
8853#define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
8854#define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
8855#define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
8856/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
8857#define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
8858#define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
8859#define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
8860#define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
8861#define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
8862#define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
8863
8864/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
8865#define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
8866
8867/******************** Bit definition for USB_OTG_HCDMA register ********************/
8868#define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
8869
8870/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
8871#define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space available */
8872
8873/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
8874#define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
8875#define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
8876
8877/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
8878#define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
8879#define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
8880#define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
8881#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
8882#define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
8883#define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
8884#define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
8885#define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
8886#define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
8887#define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
8888#define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
8889#define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
8890#define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
8891#define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
8892
8893/******************** Bit definition for USB_OTG_DOEPINT register ********************/
8894#define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
8895#define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
8896#define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
8897#define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
8898#define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
8899#define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
8900
8901/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
8902#define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
8903#define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
8904
8905#define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
8906#define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
8907#define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
8908
8909/******************** Bit definition for PCGCCTL register ********************/
8910#define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
8911#define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
8912#define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
8913
8914/**
8915 * @}
8916 */
8917
8918/**
8919 * @}
8920 */
8921
8922/** @addtogroup Exported_macros
8923 * @{
8924 */
8925
8926/******************************* ADC Instances ********************************/
8927#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
8928 ((__INSTANCE__) == ADC2) || \
8929 ((__INSTANCE__) == ADC3))
8930
8931/******************************* CAN Instances ********************************/
8932#define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
8933 ((__INSTANCE__) == CAN2))
8934
8935/******************************* CRC Instances ********************************/
8936#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
8937
8938/******************************* DAC Instances ********************************/
8939#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
8940
8941/******************************* DCMI Instances *******************************/
8942#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
8943
8944/******************************* DMA2D Instances *******************************/
8945#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
8946
8947/******************************** DMA Instances *******************************/
8948#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
8949 ((__INSTANCE__) == DMA1_Stream1) || \
8950 ((__INSTANCE__) == DMA1_Stream2) || \
8951 ((__INSTANCE__) == DMA1_Stream3) || \
8952 ((__INSTANCE__) == DMA1_Stream4) || \
8953 ((__INSTANCE__) == DMA1_Stream5) || \
8954 ((__INSTANCE__) == DMA1_Stream6) || \
8955 ((__INSTANCE__) == DMA1_Stream7) || \
8956 ((__INSTANCE__) == DMA2_Stream0) || \
8957 ((__INSTANCE__) == DMA2_Stream1) || \
8958 ((__INSTANCE__) == DMA2_Stream2) || \
8959 ((__INSTANCE__) == DMA2_Stream3) || \
8960 ((__INSTANCE__) == DMA2_Stream4) || \
8961 ((__INSTANCE__) == DMA2_Stream5) || \
8962 ((__INSTANCE__) == DMA2_Stream6) || \
8963 ((__INSTANCE__) == DMA2_Stream7))
8964
8965/******************************* GPIO Instances *******************************/
8966#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
8967 ((__INSTANCE__) == GPIOB) || \
8968 ((__INSTANCE__) == GPIOC) || \
8969 ((__INSTANCE__) == GPIOD) || \
8970 ((__INSTANCE__) == GPIOE) || \
8971 ((__INSTANCE__) == GPIOF) || \
8972 ((__INSTANCE__) == GPIOG) || \
8973 ((__INSTANCE__) == GPIOH) || \
8974 ((__INSTANCE__) == GPIOI) || \
8975 ((__INSTANCE__) == GPIOJ) || \
8976 ((__INSTANCE__) == GPIOK))
8977
8978#define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
8979 ((__INSTANCE__) == GPIOB) || \
8980 ((__INSTANCE__) == GPIOC) || \
8981 ((__INSTANCE__) == GPIOD) || \
8982 ((__INSTANCE__) == GPIOE) || \
8983 ((__INSTANCE__) == GPIOF) || \
8984 ((__INSTANCE__) == GPIOG) || \
8985 ((__INSTANCE__) == GPIOH) || \
8986 ((__INSTANCE__) == GPIOI) || \
8987 ((__INSTANCE__) == GPIOJ) || \
8988 ((__INSTANCE__) == GPIOK))
8989
8990/****************************** CEC Instances *********************************/
8991#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
8992
8993/****************************** QSPI Instances *********************************/
8994#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
8995
8996
8997/******************************** I2C Instances *******************************/
8998#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
8999 ((__INSTANCE__) == I2C2) || \
9000 ((__INSTANCE__) == I2C3) || \
9001 ((__INSTANCE__) == I2C4))
9002
9003/******************************** I2S Instances *******************************/
9004#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
9005 ((__INSTANCE__) == SPI2) || \
9006 ((__INSTANCE__) == SPI3))
9007
9008/******************************* LPTIM Instances ********************************/
9009#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
9010
9011/****************************** LTDC Instances ********************************/
9012#define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
9013
9014/******************************* RNG Instances ********************************/
9015#define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
9016
9017/****************************** RTC Instances *********************************/
9018#define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
9019
9020/******************************* SAI Instances ********************************/
9021#define IS_SAI_BLOCK_PERIPH(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
9022 ((__PERIPH__) == SAI1_Block_B) || \
9023 ((__PERIPH__) == SAI2_Block_A) || \
9024 ((__PERIPH__) == SAI2_Block_B))
9025
9026
9027/******************************** SDMMC Instances *******************************/
9028#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
9029
9030
9031/****************************** SPDIFRX Instances *********************************/
9032#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
9033
9034/******************************** SPI Instances *******************************/
9035#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
9036 ((__INSTANCE__) == SPI2) || \
9037 ((__INSTANCE__) == SPI3) || \
9038 ((__INSTANCE__) == SPI4) || \
9039 ((__INSTANCE__) == SPI5) || \
9040 ((__INSTANCE__) == SPI6))
9041
9042/****************** TIM Instances : All supported instances *******************/
9043#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9044 ((__INSTANCE__) == TIM2) || \
9045 ((__INSTANCE__) == TIM3) || \
9046 ((__INSTANCE__) == TIM4) || \
9047 ((__INSTANCE__) == TIM5) || \
9048 ((__INSTANCE__) == TIM6) || \
9049 ((__INSTANCE__) == TIM7) || \
9050 ((__INSTANCE__) == TIM8) || \
9051 ((__INSTANCE__) == TIM9) || \
9052 ((__INSTANCE__) == TIM10) || \
9053 ((__INSTANCE__) == TIM11) || \
9054 ((__INSTANCE__) == TIM12) || \
9055 ((__INSTANCE__) == TIM13) || \
9056 ((__INSTANCE__) == TIM14))
9057
9058/************* TIM Instances : at least 1 capture/compare channel *************/
9059#define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9060 ((__INSTANCE__) == TIM2) || \
9061 ((__INSTANCE__) == TIM3) || \
9062 ((__INSTANCE__) == TIM4) || \
9063 ((__INSTANCE__) == TIM5) || \
9064 ((__INSTANCE__) == TIM8) || \
9065 ((__INSTANCE__) == TIM9) || \
9066 ((__INSTANCE__) == TIM10) || \
9067 ((__INSTANCE__) == TIM11) || \
9068 ((__INSTANCE__) == TIM12) || \
9069 ((__INSTANCE__) == TIM13) || \
9070 ((__INSTANCE__) == TIM14))
9071
9072/************ TIM Instances : at least 2 capture/compare channels *************/
9073#define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9074 ((__INSTANCE__) == TIM2) || \
9075 ((__INSTANCE__) == TIM3) || \
9076 ((__INSTANCE__) == TIM4) || \
9077 ((__INSTANCE__) == TIM5) || \
9078 ((__INSTANCE__) == TIM8) || \
9079 ((__INSTANCE__) == TIM9) || \
9080 ((__INSTANCE__) == TIM12))
9081
9082/************ TIM Instances : at least 3 capture/compare channels *************/
9083#define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9084 ((__INSTANCE__) == TIM2) || \
9085 ((__INSTANCE__) == TIM3) || \
9086 ((__INSTANCE__) == TIM4) || \
9087 ((__INSTANCE__) == TIM5) || \
9088 ((__INSTANCE__) == TIM8))
9089
9090/************ TIM Instances : at least 4 capture/compare channels *************/
9091#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9092 ((__INSTANCE__) == TIM2) || \
9093 ((__INSTANCE__) == TIM3) || \
9094 ((__INSTANCE__) == TIM4) || \
9095 ((__INSTANCE__) == TIM5) || \
9096 ((__INSTANCE__) == TIM8))
9097
9098/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
9099#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
9100 (((__INSTANCE__) == TIM1) || \
9101 ((__INSTANCE__) == TIM8))
9102
9103/****************** TIM Instances : supporting OCxREF clear *******************/
9104#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
9105 (((__INSTANCE__) == TIM1) || \
9106 ((__INSTANCE__) == TIM2) || \
9107 ((__INSTANCE__) == TIM3) || \
9108 ((__INSTANCE__) == TIM4) || \
9109 ((__INSTANCE__) == TIM8))
9110
9111/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
9112#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
9113 (((__INSTANCE__) == TIM1) || \
9114 ((__INSTANCE__) == TIM2) || \
9115 ((__INSTANCE__) == TIM3) || \
9116 ((__INSTANCE__) == TIM4) || \
9117 ((__INSTANCE__) == TIM5) || \
9118 ((__INSTANCE__) == TIM8))
9119
9120/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
9121#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
9122 (((__INSTANCE__) == TIM1) || \
9123 ((__INSTANCE__) == TIM2) || \
9124 ((__INSTANCE__) == TIM3) || \
9125 ((__INSTANCE__) == TIM4) || \
9126 ((__INSTANCE__) == TIM5) || \
9127 ((__INSTANCE__) == TIM8))
9128/****************** TIM Instances : at least 5 capture/compare channels *******/
9129#define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
9130 (((__INSTANCE__) == TIM1) || \
9131 ((__INSTANCE__) == TIM8) )
9132
9133/****************** TIM Instances : at least 6 capture/compare channels *******/
9134#define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
9135 (((__INSTANCE__) == TIM1) || \
9136 ((__INSTANCE__) == TIM8))
9137
9138
9139/******************** TIM Instances : Advanced-control timers *****************/
9140#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9141 ((__INSTANCE__) == TIM8))
9142
9143/****************** TIM Instances : supporting 2 break inputs *****************/
9144#define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
9145 (((__INSTANCE__) == TIM1) || \
9146 ((__INSTANCE__) == TIM8))
9147
9148/******************* TIM Instances : Timer input XOR function *****************/
9149#define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9150 ((__INSTANCE__) == TIM2) || \
9151 ((__INSTANCE__) == TIM3) || \
9152 ((__INSTANCE__) == TIM4) || \
9153 ((__INSTANCE__) == TIM5) || \
9154 ((__INSTANCE__) == TIM8))
9155
9156/****************** TIM Instances : DMA requests generation (UDE) *************/
9157#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9158 ((__INSTANCE__) == TIM2) || \
9159 ((__INSTANCE__) == TIM3) || \
9160 ((__INSTANCE__) == TIM4) || \
9161 ((__INSTANCE__) == TIM5) || \
9162 ((__INSTANCE__) == TIM6) || \
9163 ((__INSTANCE__) == TIM7) || \
9164 ((__INSTANCE__) == TIM8))
9165
9166/************ TIM Instances : DMA requests generation (CCxDE) *****************/
9167#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9168 ((__INSTANCE__) == TIM2) || \
9169 ((__INSTANCE__) == TIM3) || \
9170 ((__INSTANCE__) == TIM4) || \
9171 ((__INSTANCE__) == TIM5) || \
9172 ((__INSTANCE__) == TIM8))
9173
9174/************ TIM Instances : DMA requests generation (COMDE) *****************/
9175#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9176 ((__INSTANCE__) == TIM2) || \
9177 ((__INSTANCE__) == TIM3) || \
9178 ((__INSTANCE__) == TIM4) || \
9179 ((__INSTANCE__) == TIM5) || \
9180 ((__INSTANCE__) == TIM8))
9181
9182/******************** TIM Instances : DMA burst feature ***********************/
9183#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9184 ((__INSTANCE__) == TIM2) || \
9185 ((__INSTANCE__) == TIM3) || \
9186 ((__INSTANCE__) == TIM4) || \
9187 ((__INSTANCE__) == TIM5) || \
9188 ((__INSTANCE__) == TIM8))
9189
9190/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
9191#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9192 ((__INSTANCE__) == TIM2) || \
9193 ((__INSTANCE__) == TIM3) || \
9194 ((__INSTANCE__) == TIM4) || \
9195 ((__INSTANCE__) == TIM5) || \
9196 ((__INSTANCE__) == TIM6) || \
9197 ((__INSTANCE__) == TIM7) || \
9198 ((__INSTANCE__) == TIM8) || \
9199 ((__INSTANCE__) == TIM13) || \
9200 ((__INSTANCE__) == TIM14))
9201
9202/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
9203#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9204 ((__INSTANCE__) == TIM2) || \
9205 ((__INSTANCE__) == TIM3) || \
9206 ((__INSTANCE__) == TIM4) || \
9207 ((__INSTANCE__) == TIM5) || \
9208 ((__INSTANCE__) == TIM8) || \
9209 ((__INSTANCE__) == TIM9) || \
9210 ((__INSTANCE__) == TIM12))
9211
9212/********************** TIM Instances : 32 bit Counter ************************/
9213#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \
9214 ((__INSTANCE__) == TIM5))
9215
9216/***************** TIM Instances : external trigger input available ************/
9217#define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
9218 ((__INSTANCE__) == TIM2) || \
9219 ((__INSTANCE__) == TIM3) || \
9220 ((__INSTANCE__) == TIM4) || \
9221 ((__INSTANCE__) == TIM5) || \
9222 ((__INSTANCE__) == TIM8))
9223
9224/****************** TIM Instances : remapping capability **********************/
9225#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
9226 ((__INSTANCE__) == TIM5) || \
9227 ((__INSTANCE__) == TIM11))
9228
9229/******************* TIM Instances : output(s) available **********************/
9230#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
9231 ((((__INSTANCE__) == TIM1) && \
9232 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9233 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9234 ((__CHANNEL__) == TIM_CHANNEL_3) || \
9235 ((__CHANNEL__) == TIM_CHANNEL_4))) \
9236 || \
9237 (((__INSTANCE__) == TIM2) && \
9238 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9239 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9240 ((__CHANNEL__) == TIM_CHANNEL_3) || \
9241 ((__CHANNEL__) == TIM_CHANNEL_4))) \
9242 || \
9243 (((__INSTANCE__) == TIM3) && \
9244 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9245 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9246 ((__CHANNEL__) == TIM_CHANNEL_3) || \
9247 ((__CHANNEL__) == TIM_CHANNEL_4))) \
9248 || \
9249 (((__INSTANCE__) == TIM4) && \
9250 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9251 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9252 ((__CHANNEL__) == TIM_CHANNEL_3) || \
9253 ((__CHANNEL__) == TIM_CHANNEL_4))) \
9254 || \
9255 (((__INSTANCE__) == TIM5) && \
9256 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9257 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9258 ((__CHANNEL__) == TIM_CHANNEL_3) || \
9259 ((__CHANNEL__) == TIM_CHANNEL_4))) \
9260 || \
9261 (((__INSTANCE__) == TIM8) && \
9262 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9263 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9264 ((__CHANNEL__) == TIM_CHANNEL_3) || \
9265 ((__CHANNEL__) == TIM_CHANNEL_4))) \
9266 || \
9267 (((__INSTANCE__) == TIM9) && \
9268 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9269 ((__CHANNEL__) == TIM_CHANNEL_2))) \
9270 || \
9271 (((__INSTANCE__) == TIM10) && \
9272 (((__CHANNEL__) == TIM_CHANNEL_1))) \
9273 || \
9274 (((__INSTANCE__) == TIM11) && \
9275 (((__CHANNEL__) == TIM_CHANNEL_1))) \
9276 || \
9277 (((__INSTANCE__) == TIM12) && \
9278 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9279 ((__CHANNEL__) == TIM_CHANNEL_2))) \
9280 || \
9281 (((__INSTANCE__) == TIM13) && \
9282 (((__CHANNEL__) == TIM_CHANNEL_1))) \
9283 || \
9284 (((__INSTANCE__) == TIM14) && \
9285 (((__CHANNEL__) == TIM_CHANNEL_1))))
9286
9287/************ TIM Instances : complementary output(s) available ***************/
9288#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
9289 ((((__INSTANCE__) == TIM1) && \
9290 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9291 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9292 ((__CHANNEL__) == TIM_CHANNEL_3))) \
9293 || \
9294 (((__INSTANCE__) == TIM8) && \
9295 (((__CHANNEL__) == TIM_CHANNEL_1) || \
9296 ((__CHANNEL__) == TIM_CHANNEL_2) || \
9297 ((__CHANNEL__) == TIM_CHANNEL_3))))
9298
9299/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
9300#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
9301 (((__INSTANCE__) == TIM1) || \
9302 ((__INSTANCE__) == TIM8) )
9303
9304/****************** TIM Instances : supporting synchronization ****************/
9305#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
9306 (((__INSTANCE__) == TIM1) || \
9307 ((__INSTANCE__) == TIM2) || \
9308 ((__INSTANCE__) == TIM3) || \
9309 ((__INSTANCE__) == TIM4) || \
9310 ((__INSTANCE__) == TIM5) || \
9311 ((__INSTANCE__) == TIM6) || \
9312 ((__INSTANCE__) == TIM7) || \
9313 ((__INSTANCE__) == TIM8))
9314
9315/******************** USART Instances : Synchronous mode **********************/
9316#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9317 ((__INSTANCE__) == USART2) || \
9318 ((__INSTANCE__) == USART3) || \
9319 ((__INSTANCE__) == USART6))
9320
9321/******************** UART Instances : Asynchronous mode **********************/
9322#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9323 ((__INSTANCE__) == USART2) || \
9324 ((__INSTANCE__) == USART3) || \
9325 ((__INSTANCE__) == UART4) || \
9326 ((__INSTANCE__) == UART5) || \
9327 ((__INSTANCE__) == USART6) || \
9328 ((__INSTANCE__) == UART7) || \
9329 ((__INSTANCE__) == UART8))
9330
9331/****************** UART Instances : Hardware Flow control ********************/
9332#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9333 ((__INSTANCE__) == USART2) || \
9334 ((__INSTANCE__) == USART3) || \
9335 ((__INSTANCE__) == UART4) || \
9336 ((__INSTANCE__) == UART5) || \
9337 ((__INSTANCE__) == USART6) || \
9338 ((__INSTANCE__) == UART7) || \
9339 ((__INSTANCE__) == UART8))
9340
9341/********************* UART Instances : Smart card mode ***********************/
9342#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9343 ((__INSTANCE__) == USART2) || \
9344 ((__INSTANCE__) == USART3) || \
9345 ((__INSTANCE__) == USART6))
9346
9347/*********************** UART Instances : IRDA mode ***************************/
9348#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
9349 ((__INSTANCE__) == USART2) || \
9350 ((__INSTANCE__) == USART3) || \
9351 ((__INSTANCE__) == UART4) || \
9352 ((__INSTANCE__) == UART5) || \
9353 ((__INSTANCE__) == USART6) || \
9354 ((__INSTANCE__) == UART7) || \
9355 ((__INSTANCE__) == UART8))
9356
9357/****************************** IWDG Instances ********************************/
9358#define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
9359
9360/****************************** WWDG Instances ********************************/
9361#define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
9362
9363
9364/******************************************************************************/
9365/* For a painless codes migration between the STM32F7xx device product */
9366/* lines, the aliases defined below are put in place to overcome the */
9367/* differences in the interrupt handlers and IRQn definitions. */
9368/* No need to update developed interrupt code when moving across */
9369/* product lines within the same STM32F7 Family */
9370/******************************************************************************/
9371
9372/* Aliases for __IRQn */
9373#define HASH_RNG_IRQn RNG_IRQn
9374
9375/* Aliases for __IRQHandler */
9376#define HASH_RNG_IRQHandler RNG_IRQHandler
9377
9378/**
9379 * @}
9380 */
9381
9382/**
9383 * @}
9384 */
9385
9386/**
9387 * @}
9388 */
9389
9390#ifdef __cplusplus
9391}
9392#endif /* __cplusplus */
9393
9394#endif /* __STM32F746xx_H */
9395
9396
9397/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/