| rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2012 Travis Geiselbrecht |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining |
| 5 | * a copy of this software and associated documentation files |
| 6 | * (the "Software"), to deal in the Software without restriction, |
| 7 | * including without limitation the rights to use, copy, modify, merge, |
| 8 | * publish, distribute, sublicense, and/or sell copies of the Software, |
| 9 | * and to permit persons to whom the Software is furnished to do so, |
| 10 | * subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be |
| 13 | * included in all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 16 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 17 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 18 | * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
| 19 | * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 20 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 21 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 22 | */ |
| 23 | #include <debug.h> |
| 24 | #include <compiler.h> |
| 25 | #include <arch/arm/cm.h> |
| 26 | #include <platform/stm32.h> |
| 27 | #include <target/debugconfig.h> |
| 28 | #include <lib/cbuf.h> |
| 29 | |
| 30 | /* un-overridden irq handler */ |
| 31 | void stm32_dummy_irq(void) |
| 32 | { |
| 33 | arm_cm_irq_entry(); |
| 34 | |
| 35 | panic("unhandled irq\n"); |
| 36 | } |
| 37 | |
| 38 | /* a list of default handlers that are simply aliases to the dummy handler */ |
| 39 | #define DEFAULT_HANDLER(x) \ |
| 40 | void stm32_##x(void) __WEAK_ALIAS("stm32_dummy_irq"); |
| 41 | |
| 42 | DEFAULT_HANDLER(WWDG_IRQ); |
| 43 | DEFAULT_HANDLER(PVD_IRQ); |
| 44 | DEFAULT_HANDLER(TAMP_STAMP_IRQ); |
| 45 | DEFAULT_HANDLER(RTC_WKUP_IRQ); |
| 46 | DEFAULT_HANDLER(FLASH_IRQ); |
| 47 | DEFAULT_HANDLER(RCC_IRQ); |
| 48 | DEFAULT_HANDLER(EXTI0_IRQ); |
| 49 | DEFAULT_HANDLER(EXTI1_IRQ); |
| 50 | DEFAULT_HANDLER(EXTI2_IRQ); |
| 51 | DEFAULT_HANDLER(EXTI3_IRQ); |
| 52 | DEFAULT_HANDLER(EXTI4_IRQ); |
| 53 | |
| 54 | DEFAULT_HANDLER(DMA1_Stream0_IRQ); |
| 55 | DEFAULT_HANDLER(DMA1_Stream1_IRQ); |
| 56 | DEFAULT_HANDLER(DMA1_Stream2_IRQ); |
| 57 | DEFAULT_HANDLER(DMA1_Stream3_IRQ); |
| 58 | DEFAULT_HANDLER(DMA1_Stream4_IRQ); |
| 59 | DEFAULT_HANDLER(DMA1_Stream5_IRQ); |
| 60 | DEFAULT_HANDLER(DMA1_Stream6_IRQ); |
| 61 | |
| 62 | DEFAULT_HANDLER(ADC_IRQ); |
| 63 | DEFAULT_HANDLER(CAN1_TX_IRQ); |
| 64 | DEFAULT_HANDLER(CAN1_RX0_IRQ); |
| 65 | DEFAULT_HANDLER(CAN1_RX1_IRQ); |
| 66 | DEFAULT_HANDLER(CAN1_SCE_IRQ); |
| 67 | DEFAULT_HANDLER(EXTI9_5_IRQ); |
| 68 | |
| 69 | DEFAULT_HANDLER(TIM1_BRK_TIM9_IRQ); |
| 70 | DEFAULT_HANDLER(TIM1_UP_TIM10_IRQ); |
| 71 | DEFAULT_HANDLER(TIM1_TRG_COM_TIM11_IRQ); |
| 72 | DEFAULT_HANDLER(TIM1_CC_IRQ); |
| 73 | DEFAULT_HANDLER(TIM2_IRQ); |
| 74 | DEFAULT_HANDLER(TIM3_IRQ); |
| 75 | DEFAULT_HANDLER(TIM4_IRQ); |
| 76 | |
| 77 | DEFAULT_HANDLER(I2C1_EV_IRQ); |
| 78 | DEFAULT_HANDLER(I2C1_ER_IRQ); |
| 79 | DEFAULT_HANDLER(I2C2_EV_IRQ); |
| 80 | DEFAULT_HANDLER(I2C2_ER_IRQ); |
| 81 | |
| 82 | DEFAULT_HANDLER(SPI1_IRQ); |
| 83 | DEFAULT_HANDLER(SPI2_IRQ); |
| 84 | |
| 85 | DEFAULT_HANDLER(USART1_IRQ); |
| 86 | DEFAULT_HANDLER(USART2_IRQ); |
| 87 | DEFAULT_HANDLER(USART3_IRQ); |
| 88 | |
| 89 | DEFAULT_HANDLER(EXTI15_10_IRQ); |
| 90 | DEFAULT_HANDLER(RTC_Alarm_IRQ); |
| 91 | DEFAULT_HANDLER(OTG_FS_WKUP_IRQ); |
| 92 | DEFAULT_HANDLER(TIM8_BRK_TIM12_IRQ); |
| 93 | DEFAULT_HANDLER(TIM8_UP_TIM13_IRQ); |
| 94 | DEFAULT_HANDLER(TIM8_TRG_COM_TIM14_IRQ); |
| 95 | DEFAULT_HANDLER(TIM8_CC_IRQ); |
| 96 | DEFAULT_HANDLER(DMA1_Stream7_IRQ); |
| 97 | DEFAULT_HANDLER(FSMC_IRQ); |
| 98 | DEFAULT_HANDLER(SDIO_IRQ); |
| 99 | DEFAULT_HANDLER(TIM5_IRQ); |
| 100 | DEFAULT_HANDLER(SPI3_IRQ); |
| 101 | DEFAULT_HANDLER(UART4_IRQ); |
| 102 | DEFAULT_HANDLER(UART5_IRQ); |
| 103 | DEFAULT_HANDLER(TIM6_DAC_IRQ); |
| 104 | DEFAULT_HANDLER(TIM7_IRQ); |
| 105 | |
| 106 | DEFAULT_HANDLER(DMA2_Stream0_IRQ); |
| 107 | DEFAULT_HANDLER(DMA2_Stream1_IRQ); |
| 108 | DEFAULT_HANDLER(DMA2_Stream2_IRQ); |
| 109 | DEFAULT_HANDLER(DMA2_Stream3_IRQ); |
| 110 | DEFAULT_HANDLER(DMA2_Stream4_IRQ); |
| 111 | |
| 112 | DEFAULT_HANDLER(ETH_IRQ); |
| 113 | DEFAULT_HANDLER(ETH_WKUP_IRQ); |
| 114 | DEFAULT_HANDLER(CAN2_TX_IRQ); |
| 115 | DEFAULT_HANDLER(CAN2_RX0_IRQ); |
| 116 | DEFAULT_HANDLER(CAN2_RX1_IRQ); |
| 117 | DEFAULT_HANDLER(CAN2_SCE_IRQ); |
| 118 | DEFAULT_HANDLER(OTG_FS_IRQ); |
| 119 | DEFAULT_HANDLER(DMA2_Stream5_IRQ); |
| 120 | DEFAULT_HANDLER(DMA2_Stream6_IRQ); |
| 121 | DEFAULT_HANDLER(DMA2_Stream7_IRQ); |
| 122 | DEFAULT_HANDLER(USART6_IRQ); |
| 123 | DEFAULT_HANDLER(I2C3_EV_IRQ); |
| 124 | DEFAULT_HANDLER(I2C3_ER_IRQ); |
| 125 | DEFAULT_HANDLER(OTG_HS_EP1_OUT_IRQ); |
| 126 | DEFAULT_HANDLER(OTG_HS_EP1_IN_IRQ); |
| 127 | DEFAULT_HANDLER(OTG_HS_WKUP_IRQ); |
| 128 | DEFAULT_HANDLER(OTG_HS_IRQ); |
| 129 | DEFAULT_HANDLER(DCMI_IRQ); |
| 130 | DEFAULT_HANDLER(CRYP_IRQ); |
| 131 | DEFAULT_HANDLER(HASH_RNG_IRQ); |
| 132 | |
| 133 | DEFAULT_HANDLER(FMC_IRQ); |
| 134 | DEFAULT_HANDLER(SDMMC1_IRQ); |
| 135 | DEFAULT_HANDLER(RNG_IRQ); |
| 136 | DEFAULT_HANDLER(FPU_IRQ); |
| 137 | DEFAULT_HANDLER(UART7_IRQ); |
| 138 | DEFAULT_HANDLER(UART8_IRQ); |
| 139 | DEFAULT_HANDLER(SPI4_IRQ); |
| 140 | DEFAULT_HANDLER(SPI5_IRQ); |
| 141 | DEFAULT_HANDLER(SPI6_IRQ); |
| 142 | DEFAULT_HANDLER(SAI1_IRQ); |
| 143 | DEFAULT_HANDLER(LTDC_IRQ); |
| 144 | DEFAULT_HANDLER(LTDC_ER_IRQ); |
| 145 | DEFAULT_HANDLER(DMA2D_IRQ); |
| 146 | DEFAULT_HANDLER(SAI2_IRQ); |
| 147 | DEFAULT_HANDLER(QUADSPI_IRQ); |
| 148 | DEFAULT_HANDLER(LPTIM1_IRQ); |
| 149 | DEFAULT_HANDLER(CEC_IRQ); |
| 150 | DEFAULT_HANDLER(I2C4_EV_IRQ); |
| 151 | DEFAULT_HANDLER(I2C4_ER_IRQ); |
| 152 | DEFAULT_HANDLER(SPDIF_RX_IRQ); |
| 153 | |
| 154 | #define VECTAB_ENTRY(x) [x##n] = stm32_##x |
| 155 | |
| 156 | /* appended to the end of the main vector table */ |
| 157 | const void * const __SECTION(".text.boot.vectab2") vectab2[] = { |
| 158 | VECTAB_ENTRY(WWDG_IRQ), /*!< Window WatchDog Interrupt */ |
| 159 | VECTAB_ENTRY(PVD_IRQ), /*!< PVD through EXTI Line detection Interrupt */ |
| 160 | VECTAB_ENTRY(TAMP_STAMP_IRQ), /*!< Tamper and TimeStamp interrupts through the EXTI line */ |
| 161 | VECTAB_ENTRY(RTC_WKUP_IRQ), /*!< RTC Wakeup interrupt through the EXTI line */ |
| 162 | VECTAB_ENTRY(FLASH_IRQ), /*!< FLASH global Interrupt */ |
| 163 | VECTAB_ENTRY(RCC_IRQ), /*!< RCC global Interrupt */ |
| 164 | VECTAB_ENTRY(EXTI0_IRQ), /*!< EXTI Line0 Interrupt */ |
| 165 | VECTAB_ENTRY(EXTI1_IRQ), /*!< EXTI Line1 Interrupt */ |
| 166 | VECTAB_ENTRY(EXTI2_IRQ), /*!< EXTI Line2 Interrupt */ |
| 167 | VECTAB_ENTRY(EXTI3_IRQ), /*!< EXTI Line3 Interrupt */ |
| 168 | VECTAB_ENTRY(EXTI4_IRQ), /*!< EXTI Line4 Interrupt */ |
| 169 | VECTAB_ENTRY(DMA1_Stream0_IRQ), /*!< DMA1 Stream 0 global Interrupt */ |
| 170 | VECTAB_ENTRY(DMA1_Stream1_IRQ), /*!< DMA1 Stream 1 global Interrupt */ |
| 171 | VECTAB_ENTRY(DMA1_Stream2_IRQ), /*!< DMA1 Stream 2 global Interrupt */ |
| 172 | VECTAB_ENTRY(DMA1_Stream3_IRQ), /*!< DMA1 Stream 3 global Interrupt */ |
| 173 | VECTAB_ENTRY(DMA1_Stream4_IRQ), /*!< DMA1 Stream 4 global Interrupt */ |
| 174 | VECTAB_ENTRY(DMA1_Stream5_IRQ), /*!< DMA1 Stream 5 global Interrupt */ |
| 175 | VECTAB_ENTRY(DMA1_Stream6_IRQ), /*!< DMA1 Stream 6 global Interrupt */ |
| 176 | VECTAB_ENTRY(ADC_IRQ), /*!< ADC1, ADC2 and ADC3 global Interrupts */ |
| 177 | VECTAB_ENTRY(CAN1_TX_IRQ), /*!< CAN1 TX Interrupt */ |
| 178 | VECTAB_ENTRY(CAN1_RX0_IRQ), /*!< CAN1 RX0 Interrupt */ |
| 179 | VECTAB_ENTRY(CAN1_RX1_IRQ), /*!< CAN1 RX1 Interrupt */ |
| 180 | VECTAB_ENTRY(CAN1_SCE_IRQ), /*!< CAN1 SCE Interrupt */ |
| 181 | VECTAB_ENTRY(EXTI9_5_IRQ), /*!< External Line[9:5] Interrupts */ |
| 182 | VECTAB_ENTRY(TIM1_BRK_TIM9_IRQ), /*!< TIM1 Break interrupt and TIM9 global interrupt */ |
| 183 | VECTAB_ENTRY(TIM1_UP_TIM10_IRQ), /*!< TIM1 Update Interrupt and TIM10 global interrupt */ |
| 184 | VECTAB_ENTRY(TIM1_TRG_COM_TIM11_IRQ), /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ |
| 185 | VECTAB_ENTRY(TIM1_CC_IRQ), /*!< TIM1 Capture Compare Interrupt */ |
| 186 | VECTAB_ENTRY(TIM2_IRQ), /*!< TIM2 global Interrupt */ |
| 187 | VECTAB_ENTRY(TIM3_IRQ), /*!< TIM3 global Interrupt */ |
| 188 | VECTAB_ENTRY(TIM4_IRQ), /*!< TIM4 global Interrupt */ |
| 189 | VECTAB_ENTRY(I2C1_EV_IRQ), /*!< I2C1 Event Interrupt */ |
| 190 | VECTAB_ENTRY(I2C1_ER_IRQ), /*!< I2C1 Error Interrupt */ |
| 191 | VECTAB_ENTRY(I2C2_EV_IRQ), /*!< I2C2 Event Interrupt */ |
| 192 | VECTAB_ENTRY(I2C2_ER_IRQ), /*!< I2C2 Error Interrupt */ |
| 193 | VECTAB_ENTRY(SPI1_IRQ), /*!< SPI1 global Interrupt */ |
| 194 | VECTAB_ENTRY(SPI2_IRQ), /*!< SPI2 global Interrupt */ |
| 195 | VECTAB_ENTRY(USART1_IRQ), /*!< USART1 global Interrupt */ |
| 196 | VECTAB_ENTRY(USART2_IRQ), /*!< USART2 global Interrupt */ |
| 197 | VECTAB_ENTRY(USART3_IRQ), /*!< USART3 global Interrupt */ |
| 198 | VECTAB_ENTRY(EXTI15_10_IRQ), /*!< External Line[15:10] Interrupts */ |
| 199 | VECTAB_ENTRY(RTC_Alarm_IRQ), /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ |
| 200 | VECTAB_ENTRY(OTG_FS_WKUP_IRQ), /*!< USB OTG FS Wakeup through EXTI line interrupt */ |
| 201 | VECTAB_ENTRY(TIM8_BRK_TIM12_IRQ), /*!< TIM8 Break Interrupt and TIM12 global interrupt */ |
| 202 | VECTAB_ENTRY(TIM8_UP_TIM13_IRQ), /*!< TIM8 Update Interrupt and TIM13 global interrupt */ |
| 203 | VECTAB_ENTRY(TIM8_TRG_COM_TIM14_IRQ), /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ |
| 204 | VECTAB_ENTRY(TIM8_CC_IRQ), /*!< TIM8 Capture Compare Interrupt */ |
| 205 | VECTAB_ENTRY(DMA1_Stream7_IRQ), /*!< DMA1 Stream7 Interrupt */ |
| 206 | VECTAB_ENTRY(FMC_IRQ), /*!< FMC global Interrupt */ |
| 207 | VECTAB_ENTRY(SDMMC1_IRQ), /*!< SDMMC1 global Interrupt */ |
| 208 | VECTAB_ENTRY(TIM5_IRQ), /*!< TIM5 global Interrupt */ |
| 209 | VECTAB_ENTRY(SPI3_IRQ), /*!< SPI3 global Interrupt */ |
| 210 | VECTAB_ENTRY(UART4_IRQ), /*!< UART4 global Interrupt */ |
| 211 | VECTAB_ENTRY(UART5_IRQ), /*!< UART5 global Interrupt */ |
| 212 | VECTAB_ENTRY(TIM6_DAC_IRQ), /*!< TIM6 global and DAC1&2 underrun error interrupts */ |
| 213 | VECTAB_ENTRY(TIM7_IRQ), /*!< TIM7 global interrupt */ |
| 214 | VECTAB_ENTRY(DMA2_Stream0_IRQ), /*!< DMA2 Stream 0 global Interrupt */ |
| 215 | VECTAB_ENTRY(DMA2_Stream1_IRQ), /*!< DMA2 Stream 1 global Interrupt */ |
| 216 | VECTAB_ENTRY(DMA2_Stream2_IRQ), /*!< DMA2 Stream 2 global Interrupt */ |
| 217 | VECTAB_ENTRY(DMA2_Stream3_IRQ), /*!< DMA2 Stream 3 global Interrupt */ |
| 218 | VECTAB_ENTRY(DMA2_Stream4_IRQ), /*!< DMA2 Stream 4 global Interrupt */ |
| 219 | VECTAB_ENTRY(ETH_IRQ), /*!< Ethernet global Interrupt */ |
| 220 | VECTAB_ENTRY(ETH_WKUP_IRQ), /*!< Ethernet Wakeup through EXTI line Interrupt */ |
| 221 | VECTAB_ENTRY(CAN2_TX_IRQ), /*!< CAN2 TX Interrupt */ |
| 222 | VECTAB_ENTRY(CAN2_RX0_IRQ), /*!< CAN2 RX0 Interrupt */ |
| 223 | VECTAB_ENTRY(CAN2_RX1_IRQ), /*!< CAN2 RX1 Interrupt */ |
| 224 | VECTAB_ENTRY(CAN2_SCE_IRQ), /*!< CAN2 SCE Interrupt */ |
| 225 | VECTAB_ENTRY(OTG_FS_IRQ), /*!< USB OTG FS global Interrupt */ |
| 226 | VECTAB_ENTRY(DMA2_Stream5_IRQ), /*!< DMA2 Stream 5 global interrupt */ |
| 227 | VECTAB_ENTRY(DMA2_Stream6_IRQ), /*!< DMA2 Stream 6 global interrupt */ |
| 228 | VECTAB_ENTRY(DMA2_Stream7_IRQ), /*!< DMA2 Stream 7 global interrupt */ |
| 229 | VECTAB_ENTRY(USART6_IRQ), /*!< USART6 global interrupt */ |
| 230 | VECTAB_ENTRY(I2C3_EV_IRQ), /*!< I2C3 event interrupt */ |
| 231 | VECTAB_ENTRY(I2C3_ER_IRQ), /*!< I2C3 error interrupt */ |
| 232 | VECTAB_ENTRY(OTG_HS_EP1_OUT_IRQ), /*!< USB OTG HS End Point 1 Out global interrupt */ |
| 233 | VECTAB_ENTRY(OTG_HS_EP1_IN_IRQ), /*!< USB OTG HS End Point 1 In global interrupt */ |
| 234 | VECTAB_ENTRY(OTG_HS_WKUP_IRQ), /*!< USB OTG HS Wakeup through EXTI interrupt */ |
| 235 | VECTAB_ENTRY(OTG_HS_IRQ), /*!< USB OTG HS global interrupt */ |
| 236 | VECTAB_ENTRY(DCMI_IRQ), /*!< DCMI global interrupt */ |
| 237 | VECTAB_ENTRY(RNG_IRQ), /*!< RNG global interrupt */ |
| 238 | VECTAB_ENTRY(FPU_IRQ), /*!< FPU global interrupt */ |
| 239 | VECTAB_ENTRY(UART7_IRQ), /*!< UART7 global interrupt */ |
| 240 | VECTAB_ENTRY(UART8_IRQ), /*!< UART8 global interrupt */ |
| 241 | VECTAB_ENTRY(SPI4_IRQ), /*!< SPI4 global Interrupt */ |
| 242 | VECTAB_ENTRY(SPI5_IRQ), /*!< SPI5 global Interrupt */ |
| 243 | VECTAB_ENTRY(SPI6_IRQ), /*!< SPI6 global Interrupt */ |
| 244 | VECTAB_ENTRY(SAI1_IRQ), /*!< SAI1 global Interrupt */ |
| 245 | VECTAB_ENTRY(LTDC_IRQ), /*!< LTDC global Interrupt */ |
| 246 | VECTAB_ENTRY(LTDC_ER_IRQ), /*!< LTDC Error global Interrupt */ |
| 247 | VECTAB_ENTRY(DMA2D_IRQ), /*!< DMA2D global Interrupt */ |
| 248 | VECTAB_ENTRY(SAI2_IRQ), /*!< SAI2 global Interrupt */ |
| 249 | VECTAB_ENTRY(QUADSPI_IRQ), /*!< Quad SPI global interrupt */ |
| 250 | VECTAB_ENTRY(LPTIM1_IRQ), /*!< LP TIM1 interrupt */ |
| 251 | VECTAB_ENTRY(CEC_IRQ), /*!< HDMI-CEC global Interrupt */ |
| 252 | VECTAB_ENTRY(I2C4_EV_IRQ), /*!< I2C4 Event Interrupt */ |
| 253 | VECTAB_ENTRY(I2C4_ER_IRQ), /*!< I2C4 Error Interrupt */ |
| 254 | VECTAB_ENTRY(SPDIF_RX_IRQ) /*!< SPDIF-RX global Interrupt */ |
| 255 | }; |
| 256 | |