| rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2014-2015 Travis Geiselbrecht |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining |
| 5 | * a copy of this software and associated documentation files |
| 6 | * (the "Software"), to deal in the Software without restriction, |
| 7 | * including without limitation the rights to use, copy, modify, merge, |
| 8 | * publish, distribute, sublicense, and/or sell copies of the Software, |
| 9 | * and to permit persons to whom the Software is furnished to do so, |
| 10 | * subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be |
| 13 | * included in all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 16 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 17 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 18 | * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
| 19 | * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 20 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 21 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 22 | */ |
| 23 | #include <asm.h> |
| 24 | #include <platform/zynq.h> |
| 25 | |
| 26 | /* code run at the very beginning of the system, attempting to trap the 2nd cpu */ |
| 27 | FUNCTION(platform_reset) |
| 28 | /* figure out our cpu number */ |
| 29 | mrc p15, 0, r12, c0, c0, 5 /* MPIDR */ |
| 30 | |
| 31 | /* mask off the bottom 8 bits to test cpu number */ |
| 32 | ubfx r12, r12, #0, #8 |
| 33 | |
| 34 | /* if we're the 0th cpu, continue to arm_reset */ |
| 35 | teq r12, #0 |
| 36 | beq arm_reset |
| 37 | |
| 38 | /* bump the cpu counter */ |
| 39 | adr r12, __cpu_trapped |
| 40 | mov r11, #1 |
| 41 | str r11, [r12] |
| 42 | dsb |
| 43 | |
| 44 | #if !WITH_SMP |
| 45 | 0: |
| 46 | /* stay trapped here forever */ |
| 47 | wfe |
| 48 | b 0b |
| 49 | #else |
| 50 | /* pass on through the reset vector, where the arm arch code will trap the cpu */ |
| 51 | b arm_reset |
| 52 | #endif |
| 53 | |
| 54 | DATA(__cpu_trapped) |
| 55 | .word 0 |
| 56 | |
| 57 | #if 0 |
| 58 | /* disabled for now */ |
| 59 | |
| 60 | /* this code attempts to remap sram to 0xfffc0000 - 0xffffffff and |
| 61 | branch the cpu into the equivalent spot. Assumes the cpu is running |
| 62 | at the initial 0 based mapping */ |
| 63 | |
| 64 | /* a spot of the top bank of OCM memory for us to run our code from |
| 65 | needs to be below where the second cpu is running (0xffffe00-0xfffffff0) */ |
| 66 | #define TARGET_SPOT 0xfffff800 |
| 67 | |
| 68 | /* first piece of code run out of the reset vector. use |
| 69 | to relocate sram to the final location at 0xfffc0000 |
| 70 | and switch to there */ |
| 71 | FUNCTION(platform_reset) |
| 72 | /* relocate the below code to TARGET_SPOT */ |
| 73 | ldr r8, =TARGET_SPOT |
| 74 | adr r9, .Lcore_reloc_start |
| 75 | adr r10, .Lcore_reloc_end |
| 76 | |
| 77 | 0: |
| 78 | ldr r12, [r9], #4 |
| 79 | str r12, [r8], #4 |
| 80 | cmp r9, r10 |
| 81 | bne 0b |
| 82 | |
| 83 | /* load constants we will need below */ |
| 84 | ldr r8, =SLCR_BASE |
| 85 | ldr r9, =SCU_CONTROL_BASE |
| 86 | |
| 87 | /* calculate the new return address this code will need to branch to */ |
| 88 | adr r12, .Ldone |
| 89 | add r12, #0xfffc0000 |
| 90 | |
| 91 | ldr r10, =TARGET_SPOT |
| 92 | bx r10 |
| 93 | |
| 94 | .Ldone: |
| 95 | b arm_reset |
| 96 | |
| 97 | .Lcore_reloc_start: |
| 98 | # use SCLR to map the sram blocks to the top of their segment |
| 99 | movw r10, #SLCR_UNLOCK_KEY |
| 100 | str r10, [r8, #SLCR_UNLOCK] |
| 101 | |
| 102 | ldr r10, [r8, #OCM_CFG] |
| 103 | orr r10, #0xf |
| 104 | str r10, [r8, #OCM_CFG] |
| 105 | |
| 106 | movw r10, #SLCR_LOCK_KEY |
| 107 | str r10, [r8, #SLCR_LOCK] |
| 108 | |
| 109 | # tell the SCU to not filter first 1MB |
| 110 | mov r10, #0 |
| 111 | str r10, [r9, #0x40] /* SCU filter start address */ |
| 112 | dmb |
| 113 | |
| 114 | bx r12 |
| 115 | .Lcore_reloc_end: |
| 116 | |
| 117 | .ltorg |
| 118 | #endif |
| 119 | |
| 120 | |