Blame - src/bsp/trustzone/teeloader/mt2712/include/device_apc.h - T103

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/* Copyright Statement:

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*

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* This software/firmware and related documentation ("MediaTek Software") are

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* protected under relevant copyright laws. The information contained herein is

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* confidential and proprietary to MediaTek Inc. and/or its licensors. Without

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* the prior written permission of MediaTek inc. and/or its licensors, any

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* reproduction, modification, use or disclosure of MediaTek Software, and

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* information contained herein, in whole or in part, shall be strictly

* prohibited.

*

*

* BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES

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* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")

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* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER

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* ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL

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* WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED

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* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR

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* NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH

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* RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,

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* INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES

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* TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.

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* RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO

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* OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK

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* SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE

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* RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR

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* STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S

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* ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE

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* RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE

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* MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE

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* CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.

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*

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* The following software/firmware and/or related documentation ("MediaTek

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* Software") have been modified by MediaTek Inc. All revisions are subject to

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* any receiver's applicable license agreements with MediaTek Inc.

*/

#ifndef DEVICE_APC_H

#define DEVICE_APC_H

#include "typedefs.h"

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#define DEVAPC0_AO_BASE (0x1000E000U)

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#define DEVAPC0_PD_BASE (0x10207000U)

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/*******************************************************************************

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* REGISTER ADDRESS DEFINATION

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******************************************************************************/

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#define DEVAPC0_D0_APC_0 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0000))

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#define DEVAPC0_D0_APC_1 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0004))

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#define DEVAPC0_D0_APC_2 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0008))

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#define DEVAPC0_D0_APC_3 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x000C))

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#define DEVAPC0_D0_APC_4 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0010))

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#define DEVAPC0_D0_APC_5 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0014))

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#define DEVAPC0_D0_APC_6 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0018))

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#define DEVAPC0_D0_APC_7 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x001C))

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#define DEVAPC0_D0_APC_8 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0020))

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#define DEVAPC0_D0_APC_9 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0020))

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#define DEVAPC0_D0_APC_10 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0024))

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#define DEVAPC0_D0_APC_11 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0028))

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#define DEVAPC0_D0_APC_12 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0030))

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#define DEVAPC0_D1_APC_0 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0100))

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#define DEVAPC0_D1_APC_1 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0104))

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#define DEVAPC0_D1_APC_2 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0108))

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#define DEVAPC0_D1_APC_3 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x010C))

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#define DEVAPC0_D1_APC_4 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0110))

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#define DEVAPC0_D1_APC_5 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0114))

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#define DEVAPC0_D1_APC_6 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0118))

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#define DEVAPC0_D1_APC_7 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x011C))

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#define DEVAPC0_D1_APC_8 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0120))

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#define DEVAPC0_D1_APC_9 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0120))

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#define DEVAPC0_D1_APC_10 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0124))

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#define DEVAPC0_D1_APC_11 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0128))

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#define DEVAPC0_D1_APC_12 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0130))

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#define DEVAPC0_D2_APC_0 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0200))

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#define DEVAPC0_D2_APC_1 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0204))

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#define DEVAPC0_D2_APC_2 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0208))

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#define DEVAPC0_D2_APC_3 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x020C))

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#define DEVAPC0_D2_APC_4 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0210))

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#define DEVAPC0_D2_APC_5 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0214))

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#define DEVAPC0_D2_APC_6 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0218))

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#define DEVAPC0_D2_APC_7 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x021C))

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#define DEVAPC0_D2_APC_8 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0220))

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#define DEVAPC0_D2_APC_9 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0220))

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#define DEVAPC0_D2_APC_10 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0224))

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#define DEVAPC0_D2_APC_11 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0228))

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#define DEVAPC0_D2_APC_12 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0230))

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#define DEVAPC0_D3_APC_0 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0300))

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#define DEVAPC0_D3_APC_1 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0304))

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#define DEVAPC0_D3_APC_2 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0308))

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#define DEVAPC0_D3_APC_3 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x030C))

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#define DEVAPC0_D3_APC_4 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0310))

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#define DEVAPC0_D3_APC_5 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0314))

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#define DEVAPC0_D3_APC_6 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0318))

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#define DEVAPC0_D3_APC_7 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x031C))

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#define DEVAPC0_D3_APC_8 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0320))

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#define DEVAPC0_D3_APC_9 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0320))

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#define DEVAPC0_D3_APC_10 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0324))

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#define DEVAPC0_D3_APC_11 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0328))

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#define DEVAPC0_D3_APC_12 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0330))

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#define DEVAPC0_MAS_DOM_GROUP_0 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0400))

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#define DEVAPC0_MAS_DOM_GROUP_1 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0404))

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#define DEVAPC0_MAS_DOM_GROUP_2 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0408))

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#define DEVAPC0_MAS_SEC_GROUP_0 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0500))

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#define DEVAPC0_MAS_SEC_GROUP_1 ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0504))

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#define DEVAPC0_APC_CON ((volatile unsigned int*)(DEVAPC0_AO_BASE+0x0F00))

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#define DEVAPC0_PD_APC_CON ((volatile unsigned int*)(DEVAPC0_PD_BASE+0x0F00))

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#define DEVAPC_APC_CON_CTRL (0x1U)

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#define DEVAPC_APC_CON_EN (0x1U)

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#define MASTER_MSDC0 4U

typedef enum {

NON_SECURE_TRAN = 0,

SECURE_TRAN,

} E_TRANSACTION;

///* DOMAIN_SETUP */

#define DOMAIN_0 0U

#define DOMAIN_1 1U

#define DOMAIN_2 2U

#define DOMAIN_3 3U

#define CONN2AP (0xf << 16)//index12 DEVAPC0_MAS_DOM_1

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#define GPU (0xf << 20)//index21 DEVAPC0_MAS_DOM_2

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static inline unsigned int uffs(unsigned int x)

{

unsigned int r = 1;

if (!x)

return 0;

if (!(x & 0xffff)) {

x >>= 16;

r += 16;

}

if (!(x & 0xff)) {

x >>= 8;

r += 8;

}

if (!(x & 0xf)) {

x >>= 4;

r += 4;

}

if (!(x & 3)) {

x >>= 2;

r += 2;

}

if (!(x & 1)) {

x >>= 1;

r += 1;

}

return r;

}

#define reg_read16(reg) __raw_readw(reg)

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#define reg_read32(reg) __raw_readl(reg)

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#define reg_write16(reg,val) __raw_writew(val,reg)

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#define reg_write32(reg,val) __raw_writel(val,reg)

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#define reg_set_bits(reg,bs) ((*(volatile u32*)(reg)) |= (u32)(bs))

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#define reg_clr_bits(reg,bs) ((*(volatile u32*)(reg)) &= ~((u32)(bs)))

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#define reg_set_field(reg,field,val) \

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do { \

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volatile unsigned int tv = reg_read32(reg); \

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tv &= ~(field); \

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tv |= ((val) << (uffs((unsigned int)field) - 1)); \

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reg_write32(reg,tv); \

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} while(0)

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#define reg_get_field(reg,field,val) \

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do { \

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volatile unsigned int tv = reg_read32(reg); \

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val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \

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} while(0)

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#define DAPC_SEC_RW_NSEC_RW 0U /* read and write for both secure and non-secure access */

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#define DAPC_SEC_RW 1U /* read and write for secure access */

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#define DAPC_NSEC_RW 2U /* read and write for non-secure access */

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#define DAPC_SEC_DENY_NSEC_DENY 3U /* Any access is prohibited */

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#define DAPC_NS_TRANSACTION 0U /* Emit non-secure signal sideband */

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#define DAPC_S_TRANSACTION 1U /* Emit secure signal sideband */

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#define MASTER_NFI 0U

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#define MASTER_PWM 2U

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#define MASTER_THERMAL_CTRL 3U

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#define MASTER_MSDC0 4U

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#define MASTER_MSDC1 5U

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#define MASTER_MSDC2 6U

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#define MASTER_MSDC3 7U

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#define MASTER_SPI0 8U

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#define MASTER_SPM 9U

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#define MASTER_DEBUG_SYSTEM 11U

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#define MASTER_AUDIO_AFE 12U

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#define MASTER_APMCU 13U

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#define MASTER_MFG_M0 19U

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#define MASTER_USB30 20U

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#define MASTER_SPI1 22U

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#define MASTER_SPI2 23U

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#define MASTER_SPI3 24U

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#define MASTER_SPI4 25U

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#define MASTER_SPI5 26U

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#define MASTER_SCP 27U

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#define MASTER_USB30_2 28U

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#define MASTER_SFLASH 29U

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#define MASTER_GMAC 30U

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#define MASTER_PCIE0 31U

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#define MASTER_PCIE1 32U

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#define MODULE_TRANSACTION(index, is_secure) (is_secure << (index % 32))

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#define DAPC_SET_MASTER_TRANSACTION(devapc_register, is_secure) reg_write32(devapc_register, is_secure)

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#define MODULE_DOMAIN(index, domain) (domain << (2 * (index % 16)))

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#define DAPC_SET_MASTER_DOMAIN(devapc_register, domain) reg_write32(devapc_register, domain)

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#define MODULE_PERMISSION(index, permission) (permission << (2 * (index % 16)))

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#define DAPC_SET_SLAVE_PERMISSION_DOMAIN_0(devapc_register, permission) reg_write32(devapc_register, permission)

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#define DAPC_SET_SLAVE_PERMISSION_DOMAIN_1(devapc_register, permission) reg_write32(devapc_register, permission)

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#define DAPC_SET_SLAVE_PERMISSION_DOMAIN_2(devapc_register, permission) reg_write32(devapc_register, permission)

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#define DAPC_SET_SLAVE_PERMISSION_DOMAIN_3(devapc_register, permission) reg_write32(devapc_register, permission)

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#define INFRA_AO_TOP_LEVEL_CLOCK_GENERATOR 0U

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#define INFRA_AO_INFRASYS_CONFIG_REGS 1U

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/* #define Reserved 2U */

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#define INFRA_AO_PERISYS_CONFIG_REGS 3U

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/* #define Reserved 4U */

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#define INFRA_AO_GPIO_CONTROLLER 5U

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#define INFRA_AO_TOP_LEVEL_SLP_MANAGER 6U

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#define INFRA_AO_TOP_LEVEL_RESET_GENERATOR 7U

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#define INFRA_AO_GPT 8U

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/* #define Reserved 9U */

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#define INFRA_AO_SEJ 10U

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#define INFRA_AO_APMCU_EINT_CONTROLLER 11U

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#define SYS_TIMER_CONTROL_REG 12U

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#define IRRX_CONTROL_REG 13U

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#define INFRA_AO_DEVICE_APC_AO 14U

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#define UART5_REG 15U

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#define INFRA_AO_KPAD_CONTROL_REG 16U

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#define TOP_RTC_REG 17U

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#define SPI4_REG 18U

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#define SPI1_REG 19U

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#define INFRA_AO_GPT2 20U

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#define DRAMC_CH0_REG 21U

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#define DRAMC_CH1_REG 22U

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#define DRAMC_CH2_REG 23U

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#define DRAMC_CH3_REG 24U

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#define INFRASYS_MCUSYS_CONFIG_REG 25U

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#define INFRASYS_CONTROL_REG 26U

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#define INFRASYS_BOOTROM_SRAM 27U

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#define INFRASYS_EMI_BUS_INTERFACE 28U

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#define INFRASYS_SYSTEM_CIRQ 29U

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#define INFRASYS_M4U_CONFIGURATION 30U

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#define INFRASYS_EFUSEC 31U

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#define INFRASYS_DEVICE_APC_MONITOR 32U

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#define BUS_DEBUG_TRAKER 33U

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#define INFRASYS_AP_MIXED_CONTROL_REG 34U

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#define INFRASYS_M4U_2_CONFIGURATION 35U

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#define ANA_MIPI_DSI3 36U

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/* #define Reserved 37U */

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#define INFRASYS_MBIST_CONTROL_REG 38U

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#define INFRASYS_EMI_MPU_CONTROL_REG 39U

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#define INFRASYS_TRNG 40U

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#define INFRASYS_GCPU 41U

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#define INFRASYS_GCPU_NS 42U

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#define INFRASYS_CQ_DMA 43U

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#define INFRASYS_GCPU_M4U 44U

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#define ANA_MIPI_DSI2 45U

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#define ANA_MIPI_DSI0 46U

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#define ANA_MIPI_DSI1 47U

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#define ANA_MIPI_CSI0 48U

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#define ANA_MIPI_CSI1 49U

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/* #define Reserved 50U */

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#define DEGBUG_CORESIGHT 51U

#define DMA 52U

#define AUXADC 53U

#define UART0 54U

#define UART1 55U

#define UART2 56U

#define UART3 57U

#define PWM 58U

#define I2C0 59U

#define I2C1 60U

#define I2C2 61U

#define SPI0 62U

#define THERM_CTRL 63U

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/* #define Reserved 64U */

#define SPI_NOR 65U

#define NFI 66U

#define NFI_ECC 67U

#define I2C3 68U

#define I2C4 69U

/* #define Reserved 70U */

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#define I2C5 71U

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/* #define Reserved 72U */

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#define SPI2 73U

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#define SPI3 74U

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/* #define Reserved 75U */

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/* #define Reserved 76U */

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#define UART4 77U

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/* #define Reserved 78U */

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#define GMAC 79U

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/* #define Reserved 80U */

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/* #define Reserved 81U */

#define AUDIO 82U

#define MSDC0 83U

#define MSDC1 84U

#define MSDC2 85U

#define MSDC3 86U

#define USB3_0 87U

#define USB3_0SIF 88U

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#define USB3_0SIF2 89U

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#define USB3_0_2 90U

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#define USB3_0SIF_2 91U

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#define USB3_0SIF2_2 92U

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#define SCPSYS_SRAM 93U

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#define PCIe0 94U

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#define PCIe1 95U

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#define G3D_CONFIG 96U

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#define MMSYS_CONFIG 97U

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#define MDP_RDMA0 98U

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#define MDP_RDMA1 99U

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#define MDP_RSZ0 100U

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#define MDP_RSZ1 101U

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#define MDP_RSZ2 102U

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#define MDP_WDMA 103U

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#define MDP_WROT0 104U

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#define MDP_WROT1 105U

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#define MDP_TDSHP0 106U

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#define MDP_TDSHP1 107U

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/* #define Reserved 108U */

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#define DISP_OVL0 109U

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#define DISP_OVL1 110U

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#define DISP_RDMA0 111U

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#define DISP_RDMA1 112U

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#define DISP_RDMA2 113U

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#define DISP_WDMA0 114U

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#define DISP_WDMA1 115U

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#define DISP_COLOR0 116U

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#define DISP_COLOR1 117U

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#define DISP_AAL 118U

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#define DISP_GAMMA 119U

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/* #define Reserved 120U */

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#define DISP_SPLIT0 121U

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/* #define Reserved 122U */

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#define DISP_UFOE 123U

#define DSI0 124U

#define DSI1 125U

#define DPI 126U

#define DISP_PWM0 127U

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#define DISP_PWM1 128U

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#define MM_MUTEX 129U

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#define SMI_LARB0 130U

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#define SMI_COMMON 131U

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#define DISP_OD 132U

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#define DPI1 133U

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/* #define Reserved 134U */

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#define LVDS 135U

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#define SMI_LARB4 136U

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#define MDP_RDMA2 137U

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#define DISP_COLOR2 138U

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#define DISP_AAL1 139U

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#define DISP_OD1 140U

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#define DISP_OVL2 141U

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#define DISP_WDMA2 142U

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#define LVDS1 143U

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#define MDP_TDSHP2 144U

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#define SMI_LARB5 145U

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#define SMI_COMMON1 146U

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#define SMI_LARB7 147U

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#define MDP_RDMA3 148U

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#define MDP_WROT2 149U

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#define DSI2 150U

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#define DSI3 151U

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/* #define Reserved 152U */

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#define DISP_MONITOR0 153U

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#define DISP_MONITOR1 154U

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#define DISP_MONITOR2 155U

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#define DISP_MONITOR3 156U

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#define DISP_PWM2 157U

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#define IMGSYS_CONFIG 158U

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#define SMI_LARB2 159U

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#define SENINF_TOP0 160U

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#define SENINF_TOP1 161U

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#define CAMSV_TOP0 162U

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#define CAMSV_TOP1 163U

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#define CAMSV_TOP2 164U

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#define CAMSV_TOP3 165U

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#define CAMSV_TOP4 166U

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#define CAMSV_TOP5 167U

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/* #define Reserved 168U */

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/* #define Reserved 169U */

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/* #define Reserved 170U */

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/* #define Reserved 171U */

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/* #define Reserved 172U */

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/* #define Reserved 173U */

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#define BDP_DISPSYS_CONFIG 174U

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#define BDP_DISPFMT 175U

#define BDP_VDO 176U

#define BDP_NR 177U

#define BDP_NR2 178U

#define BDP_TVD 179U

#define BDP_WR_CHANNEL_DI 180U

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#define BDP_WR_CHANNEL_VDI 181U

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#define BDP_LARB 182U

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#define BDP_LARB_RT 183U

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#define BDP_DRAM2AXI_BRIDGE 184U

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#define VDECSYS_CONFIGURATION 185U

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#define VDECSYS_SMI_LARB1 186U

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#define VDEC_FULL_TOP 187U

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#define IMGRZ 188U

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#define VDEC_MBIST 189U

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#define JPGDEC_CONFIGURATION 190U

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#define JPDEC 191U

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#define JPDGDEC1 192U

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/* #define Reserved 193U */

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#define VENC_CONFIGURATION 194U

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#define VENC_SMI_LARB3 195U

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#define VENC_SMI_LARB6 196U

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#define SMI_COMMON_2 197U

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#define VENC 198U

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/* #define Reserved 199U */

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#define SFLASH 200U

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extern void device_APC_dom_setup(void);

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extern void tz_dapc_sec_setting(void);

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#endif