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192.168.1.100 / T103 / 1f884588077ad3476b9c91cbb0ee9ee0332bbb68 / . / src / devtools / met-driver / 4.14 / common / sspm / ondiemet_sspm.h
blob: 64dfcbd59e0c6c2f9669763ebbe312ced33e9e59 [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +0800[diff] [blame^]1/*
2 * Copyright (C) 2018 MediaTek Inc.
3 *
4 * This program is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __ONDIEMET_SSPM_H
15#define __ONDIEMET_SSPM_H
16
17#if defined(CONFIG_MTK_TINYSYS_SSPM_SUPPORT) && defined(ONDIEMET_SUPPORT)
18#include "ondiemet.h"
19#include "sspm_ipi.h"
20#include <linux/dma-mapping.h>
21
22/* we may use IPI_ID_PLATFORM for mt6759 to reduce SRAM */
23#ifndef IPI_ID_MET
24/* #define IPI_ID_MET IPI_ID_TST1 */
25#define IPI_ID_MET IPI_ID_PLATFORM
26#endif
27
28/* MET IPI command definition: mbox 0 */
29/* main func ID: bit[31-24]; sub func ID: bit[23-18]; argu 0: bit[17-0] */
30#define MET_MAIN_ID_MASK 0xff000000 /* bit 31 - 24 */
31#define MET_SUB_ID_MASK 0x00fc0000 /* bit 23 - 18 */
32#define MET_ARGU0_MASK 0x0003ffff /* bit 17 - 0 */
33#define FUNC_BIT_SHIFT 18
34#define MID_BIT_SHIFT 9
35#define MET_MAIN_ID 0x06000000
36/* handle argument and attribute */
37#define PROCESS_ARGU 0x01
38#define PROCESS_ATTR 0x02
39#define MODULE_ID_MASK 0x3fe00 /* bit 9 - 17 */
40#define ARGUMENT_MASK 0x01ff /* bit 0 - 8 */
41
42/* the following command is used for AP to MD32 */
43#define MET_OP (1 << FUNC_BIT_SHIFT)
44/* argu 0: start: 0x01; stop: 0x02; extract: 0x03 */
45#define MET_OP_START 0x00000001
46#define MET_OP_STOP 0x00000002
47#define MET_OP_EXTRACT 0x00000003
48#define MET_OP_FLUSH 0x00000004
49#define MET_SR (2 << FUNC_BIT_SHIFT) /* sample rate */
50#define MET_MODULE (3 << FUNC_BIT_SHIFT) /* module enable/disable */
51#define MET_ARGU (4 << FUNC_BIT_SHIFT) /* argument passing */
52#define MET_ATTR (5 << FUNC_BIT_SHIFT) /* attribute passing */
53/* system memory information for on-die-met log data */
54#define MET_BUFFER_INFO (6 << FUNC_BIT_SHIFT)
55#define MET_TIMESTAMP (7 << FUNC_BIT_SHIFT) /* timestamp info */
56#define MET_GPT (8 << FUNC_BIT_SHIFT) /* GPT counter reading */
57#define MET_REQ_AP2MD (9 << FUNC_BIT_SHIFT) /* user defined command */
58#define MET_RESP_AP2MD (10 << FUNC_BIT_SHIFT) /* may no need */
59/* mode: bit 15 - 0: */
60/* Bit 0: MD32 SRAM mode; Bit 1: System DRAM mode */
61/* value: 0: output to next level of storage; 1: loop in its own storage */
62#define MET_DATA_MODE (11 << FUNC_BIT_SHIFT) /* log output mode */
63/* start/stop read data into MD32 SRAM buffer; both DMA and met_printf() */
64#define MET_DATA_OP (12 << FUNC_BIT_SHIFT) /* data read operation */
65/* the following command is used for MD32 to AP */
66#define MET_DUMP_BUFFER (13 << FUNC_BIT_SHIFT)
67#define MET_REQ_MD2AP (14 << FUNC_BIT_SHIFT) /* user defined command */
68#define MET_CLOSE_FILE (15 << FUNC_BIT_SHIFT) /* Inform to close the SD file */
69#define MET_RESP_MD2AP (16 << FUNC_BIT_SHIFT)
70#define MET_RUN_MODE (17 << FUNC_BIT_SHIFT)
71
72/* Note: the module ID and its bit pattern should be fixed as below */
73/* DMA based module first */
74enum {
75 MID_PMQOS = 0,
76 MID_VCORE_DVFS,
77 MID_EMI,
78 MID_THERMAL_CPU,
79 MID_WALL_TIME,
80 MID_CPU_DVFS,
81 MID_GPU_DVFS,
82 MID_PTPOD,
83 MID_SPM,
84 MID_PROFILE,
85 MID_MET_TAG,
86 MID_TS,
87 MID_TS_ISR,
88 MID_TS_LAST,
89 MID_TS_ISR_LAST,
90 MID_SRAM_INFO,
91 MID_MET_STOP,
92 MID_IOP_MON,
93 MID_CPU_INFO_MAPPING,
94 MID_SMI,
95
96 MID_COMMON = 0x1F
97};
98
99#define ID_PMQOS (1 << MID_PMQOS)
100#define ID_SMI (1 << MID_SMI)
101#define ID_EMI (1 << MID_EMI)
102#define ID_THERMAL_CPU (1 << MID_THERMAL_CPU)
103#define ID_WALL_TIME (1 << MID_WALL_TIME)
104#define ID_CPU_DVFS (1 << MID_CPU_DVFS)
105#define ID_GPU_DVFS (1 << MID_GPU_DVFS)
106#define ID_VCORE_DVFS (1 << MID_VCORE_DVFS)
107#define ID_PTPOD (1 << MID_PTPOD)
108#define ID_SPM (1 << MID_SPM)
109#define ID_PROFILE (1 << MID_PROFILE)
110#define ID_COMMON (1 << MID_COMMON)
111#define ID_CPU_INFO_MAPPING (1 << MID_CPU_INFO_MAPPING)
112#define ID_SMI (1 << MID_SMI)
113
114extern void ondiemet_extract(void);
115extern void ondiemet_stop(void);
116extern void ondiemet_start(void);
117
118extern void start_sspm_ipi_recv_thread(void);
119extern void stop_sspm_ipi_recv_thread(void);
120
121extern unsigned int ondiemet_ipi_buf[];
122
123/* extern phys_addr_t ondiemet_sspm_log_phy_addr, ondiemet_sspm_log_virt_addr; */
124extern dma_addr_t ondiemet_sspm_log_phy_addr;
125
126extern void *ondiemet_sspm_log_virt_addr;
127extern uint32_t ondiemet_sspm_log_size;
128
129extern int ondiemet_attr_init(struct device *dev);
130extern int ondiemet_attr_uninit(struct device *dev);
131extern int met_sspm_log_discard;
132
133#define SSPM_LOG_FILE 0
134#define SSPM_LOG_SRAM 1
135#define SSPM_LOG_DRAM 2
136extern int sspm_log_mode;
137#define SSPM_RUN_NORMAL 0
138#define SSPM_RUN_CONTINUOUS 1
139extern int sspm_run_mode;
140
141/* extern void sspm_get_buffer_info(void); */
142extern int sspm_buf_available;
143extern int sspm_buffer_dumping;
144
145void sspm_flush(void);
146
147#endif /* CONFIG_MTK_TINYSYS_SSPM_SUPPORT && ONDIEMET_SUPPORT */
148#endif /* __ONDIEMET_SSPM_H */