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192.168.1.100 / T103 / 1f884588077ad3476b9c91cbb0ee9ee0332bbb68 / . / src / devtools / met-driver / 4.19 / mt2712 / mtk_dramc.h
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rjw1f884582022-01-06 17:20:42 +0800[diff] [blame^]1/* Copyright Statement:
2 *
3 * This software/firmware and related documentation ("MediaTek Software") are
4 * protected under relevant copyright laws. The information contained herein
5 * is confidential and proprietary to MediaTek Inc. and/or its licensors.
6 * Without the prior written permission of MediaTek inc. and/or its licensors,
7 * any reproduction, modification, use or disclosure of MediaTek Software,
8 * and information contained herein, in whole or in part, shall be strictly prohibited.
9 */
10/* MediaTek Inc. (C) 2012. All rights reserved.
11 *
12 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
13 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
14 * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
15 * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
18 * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
19 * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
20 * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
21 * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
22 * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
23 * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
24 * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
25 * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
26 * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
27 * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
28 * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
29 * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
30 *
31 * The following software/firmware and/or related documentation ("MediaTek Software")
32 * have been modified by MediaTek Inc. All revisions are subject to any receiver's
33 * applicable license agreements with MediaTek Inc.
34 */
35
36#ifndef __MT_DRAMC_H__
37#define __MT_DRAMC_H__
38#include <linux/types.h>
39//#include "x_hal_io.h"
40
41/* define BM function base address */
42#define MET_DRAMC0_BASE (0xF0006000)
43#define MET_DRAMC1_BASE (0xF0010000)
44#define MET_DRAMC2_BASE (0xF0011000)
45#define TCM_DRAM_FLAGS_ADDR (0xF00080F8)
46#define DRAM_CLOCK_MASK (0x00000FFF)
47
48#define BASE_DDR_CLK 1000000
49#define TCMGET_DDR_CLK(p) ((p & DRAM_CLOCK_MASK) * BASE_DDR_CLK)
50
51/* define BM function offset */
52#define DRAMC_MON_BM(i) (i + 0x80)
53#define DRAMC_MON_BMCYC(i) (i + 0x8C) /* Bus monitor cycle number, BMCYC */
54#define DRAMC_MON_ROBM0(i) (i + 0x90) /* Bus monitor counter for group 1,BMLENGP1_CNT */
55#define DRAMC_MON_ROBM1(i) (i + 0x94) /* Bus monitor counter for group 2,BMLENGP2_CNT */
56#define DRAMC_MON_ROBM2(i) (i + 0x98) /* Bus monitor counter for group 3,BMLENGP3_CNT */
57#define DRAMC_MON_ROBM3(i) (i + 0x9C) /* bus monitor cycle counter,BM_CYC_CNT */
58#define DRAMC_MON_ROBM4(i) (i + 0xA0) /* Maximum burst length, 16'h0000, MAX_BSTCNT */
59
60/* define BM function shift */
61#define DRAMC_BM_PACNTEN (31) /* Bus monitor function select for number of precharge and active */
62#define DRAMC_BM_REQCNTEN (30) /* Bus monitor function select for number of REQ='1'&ALE='1' */
63#define DRAMC_BM_CHGPRIEN (29) /* On-line change agent priority enabling */
64#define DRAMC_BM_FREEZE_SHIFT (28) /* Bus monitor freeze */
65#define DRAMC_BM_DMBW32B_SHIFT (27) /* 1:External 32Bit data bus, 0:External 16Bit data bus */
66#define DRAMC_BM_WREN_SHIFT (25) /* Bus monitor only monitor write cycle enabling */
67#define DRAMC_BM_RDEN_SHIFT (24) /* Bus monitor only monitor read cycle enabling */
68#define DRAMC_BM_GROUP3_ENABLE_SHIFT (23) /* Bus monitor for Group 3 agents enabling */
69#define DRAMC_BM_GROUP3_AGENT_ID_SHIFT (20) /* Bus monitor for Group 3 agent-ID */
70#define DRAMC_BM_GROUP3_AGENT_ID_LEN (3)
71#define DRAMC_BM_GROUP2_ENABLE_SHIFT (19) /* Bus monitor for Group 2 agents enabling */
72#define DRAMC_BM_GROUP2_AGENT_ID_SHIFT (16) /* Bus monitor for Group 2 agent-ID */
73#define DRAMC_BM_GROUP2_AGENT_ID_LEN (3)
74#define DRAMC_BM_GROUP1_ENABLE_SHIFT (15) /* Bus monitor for Group 1 agents enabling */
75#define DRAMC_BM_GROUP1_AGENT_ID_SHIFT (8) /* Bus monitor for Group 1 agent-ID or */
76#define DRAMC_BM_GROUP1_AGENT_ID_LEN (5)
77#define DRAMC_BM_BSTCNTEN (7) /* Monitor burst length enable */
78#define DRAMC_BM_R_DMBSTCNT_SEL (6) /* Latency mode select */
79#define DRAMC_BM_R_DMLATRECEN (5) /* Agent latency record enable */
80#define DRAMC_BM_BSTCNT (0) /* Agent-ID of the burst length monitored agent */
81#define DRAMC_BM_BSTCNT_LEN (4)
82
83/* define TCM function base address */
84#ifndef IO_VIRT
85#define IO_VIRT (0xF0000000)
86#endif
87
88#define REG_RW_GPRB6 (0x00f8) /* RISC Byte General Purpose Register 6 */
89#define TCM_SRAM_ADDR (IO_VIRT + 0x8000)
90
91#ifdef CONFIG_64BIT
92#define TCM_DRAM_FLAGS (*((volatile unsigned long*)(OFFSET_64BIT + TCM_SRAM_ADDR + REG_RW_GPRB6)))
93#else
94#define TCM_DRAM_FLAGS (*((volatile unsigned long*)(TCM_SRAM_ADDR + REG_RW_GPRB6)))
95#endif
96
97#define CHA_FORCE32_SHIFT (22)
98#define DRAM_CHA_FORCE32 (1U << CHA_FORCE32_SHIFT)
99#define CHB_FORCE32_SHIFT (23)
100#define DRAM_CHB_FORCE32 (1U << CHB_FORCE32_SHIFT)
101#define CHC_FORCE32_SHIFT (31)
102#define DRAM_CHC_FORCE32 (1U << CHC_FORCE32_SHIFT)
103
104
105/* to check dramc is ext 32 bit or not*/
106#define DRMAC_IS_FORCE32(p) ((TCM_DRAM_FLAGS & p) ? 0 : 1)
107
108/* generate random cycle to return fake report */
109/* #define DRAMC_FAKE_REPORT */
110
111/* define dramc spec */
112#define DRAMC_MX_CHANNUM (1)
113#define DRAMC_MX_GRPNUM (3)
114#define DRAMC_MX_NUM_IN_AGRP (32)
115#define DRAMC_MX_AGENT_NAMEBUF (96)
116
117/* define all group id */
118#define DRAMC_ALL_GROUP_AGENT_ID (0x20)
119#define DRAMC_MX_LATENCY (0x21)
120
121/* efuse bit[15:14]
12200:4G
12301:3G
12410:2G
12511:1G */
126#define DRAMC_EFUSE_BIT_ADDRESS (0xF0008664)
127#define DRAMC_EFUSE_BIT_MASK (0x0000C000)
128#define DRAMC_EFUSE_BIT_1G (0x0000C000)
129#define DRAMC_EFUSE_BIT_2G (0x00008000)
130#define DRAMC_EFUSE_BIT_3G (0x00004000)
131#define DRAMC_EFUSE_BIT_4G (0x00000000)
132
133#define DRAM_DDRPHY_CHA_BANK (IO_VIRT + 0x7A000)
134#define DRAM_DDRPHY_CHB_BANK (IO_VIRT + 0x7B000)
135#define DRAM_DDRPHY_CHC_BANK (IO_VIRT + 0x7C000)
136
137#define DRAM_BASE (IO_VIRT + 0x07000)
138#define DRAM_CHB_BASE (IO_VIRT + 0x0F000)
139#define DRAM_CHC_BASE (IO_VIRT + 0x15000)
140
141/* Bandwidth counter for agent0-15 */
142#define DRAMC_MON_AGENT_NUM (16)
143#define DRAMC_MON_AGENT_BASE(i) (i + 0x2C0)
144#define DRAMC_MON_AGENT0(i) (i + 0x2C0)
145#define DRAMC_MON_AGENT1(i) (i + 0x2C4)
146#define DRAMC_MON_AGENT2(i) (i + 0x2C8)
147#define DRAMC_MON_AGENT3(i) (i + 0x2CC)
148#define DRAMC_MON_AGENT4(i) (i + 0x2D0)
149#define DRAMC_MON_AGENT5(i) (i + 0x2D4)
150#define DRAMC_MON_AGENT6(i) (i + 0x2D8)
151#define DRAMC_MON_AGENT7(i) (i + 0x2DC)
152#define DRAMC_MON_AGENT8(i) (i + 0x2E0)
153#define DRAMC_MON_AGENT9(i) (i + 0x2E4)
154#define DRAMC_MON_AGENT10(i) (i + 0x2E8)
155#define DRAMC_MON_AGENT11(i) (i + 0x2EC)
156#define DRAMC_MON_AGENT12(i) (i + 0x2F0)
157#define DRAMC_MON_AGENT13(i) (i + 0x2F4)
158#define DRAMC_MON_AGENT14(i) (i + 0x2F8)
159#define DRAMC_MON_AGENT15(i) (i + 0x2FC)
160
161/* total latency counter for agent0-15 */
162#define DRAMC_MON_LTY_AGENT_NUM (16)
163#define DRAMC_MON_LTY_AGENT_BASE(i) (i + 0x300)
164#define DRAMC_MON_LTY_AGENT0(i) (i + 0x300)
165#define DRAMC_MON_LTY_AGENT1(i) (i + 0x304)
166#define DRAMC_MON_LTY_AGENT2(i) (i + 0x308)
167#define DRAMC_MON_LTY_AGENT3(i) (i + 0x30C)
168#define DRAMC_MON_LTY_AGENT4(i) (i + 0x310)
169#define DRAMC_MON_LTY_AGENT5(i) (i + 0x314)
170#define DRAMC_MON_LTY_AGENT6(i) (i + 0x318)
171#define DRAMC_MON_LTY_AGENT7(i) (i + 0x31C)
172#define DRAMC_MON_LTY_AGENT8(i) (i + 0x320)
173#define DRAMC_MON_LTY_AGENT9(i) (i + 0x324)
174#define DRAMC_MON_LTY_AGENT10(i) (i + 0x328)
175#define DRAMC_MON_LTY_AGENT11(i) (i + 0x32C)
176#define DRAMC_MON_LTY_AGENT12(i) (i + 0x330)
177#define DRAMC_MON_LTY_AGENT13(i) (i + 0x334)
178#define DRAMC_MON_LTY_AGENT14(i) (i + 0x338)
179#define DRAMC_MON_LTY_AGENT15(i) (i + 0x33C)
180
181/* max latency counter for agent0-15 */
182#define DRAMC_MON_MAX_LTY_AGENT_NUM (16)
183#define DRAMC_MON_MAX_LTY_AGENT_BASE(i) (i + 0x340)
184#define DRAMC_MON_MAX_LTY_AGENT0(i) (i + 0x340)
185#define DRAMC_MON_MAX_LTY_AGENT1(i) (i + 0x340)
186#define DRAMC_MON_MAX_LTY_AGENT2(i) (i + 0x344)
187#define DRAMC_MON_MAX_LTY_AGENT3(i) (i + 0x344)
188#define DRAMC_MON_MAX_LTY_AGENT4(i) (i + 0x348)
189#define DRAMC_MON_MAX_LTY_AGENT5(i) (i + 0x348)
190#define DRAMC_MON_MAX_LTY_AGENT6(i) (i + 0x34C)
191#define DRAMC_MON_MAX_LTY_AGENT7(i) (i + 0x34C)
192#define DRAMC_MON_MAX_LTY_AGENT8(i) (i + 0x350)
193#define DRAMC_MON_MAX_LTY_AGENT9(i) (i + 0x350)
194#define DRAMC_MON_MAX_LTY_AGENT10(i) (i + 0x354)
195#define DRAMC_MON_MAX_LTY_AGENT11(i) (i + 0x354)
196#define DRAMC_MON_MAX_LTY_AGENT12(i) (i + 0x358)
197#define DRAMC_MON_MAX_LTY_AGENT13(i) (i + 0x358)
198#define DRAMC_MON_MAX_LTY_AGENT14(i) (i + 0x35C)
199#define DRAMC_MON_MAX_LTY_AGENT15(i) (i + 0x35C)
200
201struct dramc_desc_t {
202 int agent_id;
203 char name[DRAMC_MX_AGENT_NAMEBUF];
204};
205
206#define DRAMC_AGENT_TABLE \
207{ \
208 /* define channel A releationship between group and name */ \
209 { \
210 { \
211 /* GRP 1 */ \
212 {0, "00_audio"}, \
213 {1, "01_demux/gcpu/ddi"}, \
214 {2, "02_vbi/3d/tve"}, \
215 {3, "03_xpscaler_ip/tddc"}, \
216 {4, "04_none"}, \
217 {5, "05_audio_dsp_low1"}, \
218 {6, "06_2d_graph/2dgraph_cmd/irt_dma"}, \
219 {7, "07_ether/ci-spi/rs232"}, \
220 {8, "08_demod_isdbt"}, \
221 {9, "09_usb2"}, \
222 {10, "10_usb3_d"}, \
223 {11, "11_mmu"}, \
224 {12, "12_arm11"}, \
225 {13, "13_msdc/emmc"}, \
226 {14, "14_gdma"}, \
227 {15, "15_test0/audio_dsp0"}, \
228 {-1, ""} \
229 }, \
230 { \
231 /* GRP 2 */ \
232 {16, "16_nfi_dma/sfalsh_dma/lzhs/ci_spi"}, \
233 {17, "17_ufozip"}, \
234 {18, "18_usb3_c"}, \
235 {19, "19_none"}, \
236 {20, "20_none"}, \
237 {21, "21_none"}, \
238 {22, "22_none"}, \
239 {30, "30_none"}, \
240 {-1, ""} \
241 }, \
242 { \
243 /* GRP 3 */ \
244 {23, "23_none"}, \
245 {24, "24_none"}, \
246 {25, "25_none"}, \
247 {26, "26_none"}, \
248 {27, "27_none"}, \
249 {28, "28_none"}, \
250 {29, "29_none"}, \
251 {31, "31_none"}, \
252 {-1, ""} \
253 } \
254 } \
255}
256
257/* some marco and static inline function define */
258static inline int FIND_NEXT_AGENT(u64 mask, int agent)
259{
260 int idx = 0;
261 int mx_cnt = sizeof(u64)*8;
262 int temp_agent = agent + 1;
263
264 for (idx = 0 ; idx < mx_cnt; idx++,temp_agent++) {
265 if (mx_cnt == temp_agent)
266 temp_agent = 0;
267 if ((1ULL<<temp_agent) & mask)
268 break;
269 }
270 if (idx == mx_cnt)
271 return -1;
272 return temp_agent;
273}
274
275#define GROUP_ID(agent) ((agent <= 0xF)?1:((agent<=0x17)?2:3))
276#define GROUP1_MASK (0xFFFF)
277
278
279/* function prototype */
280extern void DRAMC_Init(int chan);
281extern void DRAMC_MaxLtcyMode(int chan, int enable);
282extern void DRAMC_Enable(int chan, int group, int agent);
283extern void DRAMC_Disable(int chan);
284extern void DRAMC_Freeze(int chan);
285extern void DRAMC_ConfigTargetCount(int chan, u32 count);
286extern u32 DRAMC_GetMaxLtcy(int chan);
287extern u32 DRAMC_GetCycleCount(int chan, int group);
288extern u32 DRAMC_GetTotalCycleCount(int chan);
289extern u32 DRAMC_GetDramcFreq(void);
290extern int DRAMC_CheckCntIsOverFlow(u32 count);
291
292extern void DRAMC_WriteMode(int chan, int enable);
293extern void DRAMC_ReadMode(int chan, int enable);
294extern unsigned int DRAMC_GetEfuseValue(void);
295
296extern void DRAMC_GetGroup1AgentCounter(int chan, unsigned int* counter);
297extern void DRAMC_GetGroup1Latency(int chan, unsigned int* latency);
298extern void DRAMC_GetGroup1MaxLatency(int chan, unsigned int* max_ltcy);
299
300#endif