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192.168.1.100 / T103 / 1f884588077ad3476b9c91cbb0ee9ee0332bbb68 / . / src / devtools / met-driver / 4.19 / mt2712 / mtk_emi_bm.h
blob: 921d80d11212c8f0b72a08aadb8a07dbcc370856 [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +0800[diff] [blame^]1#ifndef __MT_MET_EMI_BM_H__
2#define __MT_MET_EMI_BM_H__
3
4
5
6
7#define DEF_BM_RW_TYPE (BM_BOTH_READ_WRITE)
8#define NTS 2
9#define NWSCT 4
10#define NLATENCY 8
11#define NTRANS 8
12#define NALL 3
13#define NTTYPE 5
14#define NIDX_EMI (NTS + NWSCT + NLATENCY + NTRANS + NALL + NTTYPE)
15
16#define NCNT 9
17#define NCH 4
18#define NIDX_DRAMC (NCNT * NCH)
19#define NIDX (NIDX_EMI + NIDX_DRAMC)
20
21#define NCLK 1
22#define NARB 8
23#define NBW 10
24#define NIDX_BL (NCLK + NARB + NBW)
25
26/* 1000 To Khz and 4x freq & 2x data rate for LPDDR4 */
27/* 1000 To Khz and 2x freq & 2x data rate for LPDDR3*/
28/* TBD: calculate emi clock rate from DRAM DATA RATE */
29
30/*dram baseclock/EMI clock : LP4=4 LP3=2 */
31#define DRAM_EMI_BASECLOCK_RATE 4
32/*dram io width : LP4=x16 LP3=x32 or x16 */
33#define DRAM_IO_BUS_WIDTH 16
34/*dram datarate : DDR=double */
35#define DRAM_DATARATE 2
36
37#define ADDR_EMI ((unsigned long) BaseAddrEMI)
38#define ADDR_DRAMC0 ((unsigned long) BaseAddrDRAMC0)
39#define ADDR_DRAMC1 ((unsigned long) BaseAddrDRAMC1)
40#define ADDR_DRAMC2 ((unsigned long) BaseAddrDRAMC2)
41#define ADDR_DRAMC3 ((unsigned long) BaseAddrDRAMC3)
42
43static const char of_emi_desc[] = "mediatek,mt2712-emi";
44static const char of_dramc_desc[] = "mediatek,mt2712-dramc";
45
46typedef enum {
47 DRAMC_DTS_DRAMC0_AO = 0x0,
48 DRAMC_DTS_DRAMC0_NAO = 0x4,
49 DRAMC_DTS_DRAMC1_NAO = 0x5,
50 DRAMC_DTS_DRAMC2_NAO = 0x6,
51 DRAMC_DTS_DRAMC3_NAO = 0x7,
52 DRAMC_DTS_DDRPHY0_AO = 0x8,
53} BM_DRAMC_DTS_INDEX;
54
55#define BM_Master_M0_name "m0_APMCU0"
56#define BM_Master_M1_name "m1_APMCU1"
57#define BM_Master_M2_name "m2_MM1_M1"
58#define BM_Master_M3_name "m3_MM2_M1"
59#define BM_Master_M4_name "m4_MM2_M0"
60#define BM_Master_M5_name "m5_MM1_M0"
61#define BM_Master_M6_name "m6_PERI"
62#define BM_Master_M7_name "m7_GPU"
63
64#define BM_Master_GP_AP (BM_MASTER_M0 | BM_MASTER_M1)
65#define BM_Master_GP_MM (BM_MASTER_M2 | BM_MASTER_M3 | BM_MASTER_M4 | BM_MASTER_M5)
66#define BM_Master_GP_GPU (BM_MASTER_M7)
67#define BM_Master_GP_PERI (BM_MASTER_M6)
68
69
70/*Need no change by project*/
71#define BM_Master_GP_1_Default BM_Master_GP_AP
72#define BM_Master_GP_2_Default BM_Master_GP_MM
73#define BM_Master_GP_3_Default BM_Master_GP_GPU
74
75#define BM_MASTER_M0 (0x01)
76#define BM_MASTER_M1 (0x02)
77#define BM_MASTER_M2 (0x04)
78#define BM_MASTER_M3 (0x08)
79#define BM_MASTER_M4 (0x10)
80#define BM_MASTER_M5 (0x20)
81#define BM_MASTER_M6 (0x40)
82#define BM_MASTER_M7 (0x80)
83#define BM_MASTER_ALL (0xFF)
84
85typedef enum {
86 BM_RK0_PRE_STANDBY = 0x0,
87 BM_RK0_PRE_POWERDOWN,
88 BM_RK0_ACT_STANDBY,
89 BM_RK0_ACT_POWERDOWN,
90 BM_RK1_PRE_STANDBY,
91 BM_RK1_PRE_POWERDOWN,
92 BM_RK1_ACT_STANDBY,
93 BM_RK1_ACT_POWERDOWN,
94 BM_RK2_PRE_STANDBY,
95 BM_RK2_PRE_POWERDOWN,
96 BM_RK2_ACT_STANDBY,
97 BM_RK2_ACT_POWERDOWN,
98 DRAMC_Debug_MAX_CNT
99} DRAMC_Debug_Type;
100
101typedef enum {
102 DRAMC_R2R,
103 DRAMC_R2W,
104 DRAMC_W2R,
105 DRAMC_W2W,
106 DRAMC_ALL
107} DRAMC_Cnt_Type;
108
109typedef enum {
110 BM_BOTH_READ_WRITE,
111 BM_READ_ONLY,
112 BM_WRITE_ONLY
113} BM_RW_Type;
114
115enum {
116 BM_TRANS_TYPE_1BEAT = 0x0,
117 BM_TRANS_TYPE_2BEAT,
118 BM_TRANS_TYPE_3BEAT,
119 BM_TRANS_TYPE_4BEAT,
120 BM_TRANS_TYPE_5BEAT,
121 BM_TRANS_TYPE_6BEAT,
122 BM_TRANS_TYPE_7BEAT,
123 BM_TRANS_TYPE_8BEAT,
124 BM_TRANS_TYPE_9BEAT,
125 BM_TRANS_TYPE_10BEAT,
126 BM_TRANS_TYPE_11BEAT,
127 BM_TRANS_TYPE_12BEAT,
128 BM_TRANS_TYPE_13BEAT,
129 BM_TRANS_TYPE_14BEAT,
130 BM_TRANS_TYPE_15BEAT,
131 BM_TRANS_TYPE_16BEAT,
132 BM_TRANS_TYPE_1Byte = 0 << 4,
133 BM_TRANS_TYPE_2Byte = 1 << 4,
134 BM_TRANS_TYPE_4Byte = 2 << 4,
135 BM_TRANS_TYPE_8Byte = 3 << 4,
136 BM_TRANS_TYPE_16Byte = 4 << 4,
137 BM_TRANS_TYPE_32Byte = 5 << 4,
138 BM_TRANS_TYPE_BURST_WRAP = 0 << 7,
139 BM_TRANS_TYPE_BURST_INCR = 1 << 7
140};
141
142enum {
143 BM_TRANS_RW_DEFAULT = 0x0,
144 BM_TRANS_RW_READONLY,
145 BM_TRANS_RW_WRITEONLY,
146 BM_TRANS_RW_RWBOTH
147};
148
149
150/*coda busid 12bit, but HW support 16 bit*/
151#define EMI_BMID_MASK (0xFFFF)
152#define BM_COUNTER_MAX (21)
153
154/*
155*#define BUS_MON_EN (0x00000001)
156*#define BUS_MON_PAUSE (0x00000002)
157*#define BUS_MON_IDLE (0x00000008)
158*#define BC_OVERRUN (0x00000100)
159*/
160enum {
161 BUS_MON_EN_SHIFT = 0,
162 BUS_MON_PAUSE_SHIFT = 1,
163 BUS_MON_IDLE_SHIFT = 3,
164 BC_OVERRUN_SHIFT = 8,
165};
166
167#define BM_REQ_OK (0)
168#define BM_ERR_WRONG_REQ (-1)
169#define BM_ERR_OVERRUN (-2)
170
171#define BM_WSCT_TSCT_IDSEL_ENABLE (0)
172#define BM_WSCT_TSCT_IDSEL_DISABLE (-1)
173#define BM_TTYPE1_16_ENABLE (0)
174#define BM_TTYPE1_16_DISABLE (-1)
175#define BM_TTYPE17_21_ENABLE (0)
176#define BM_TTYPE17_21_DISABLE (-1)
177#define BM_BW_LIMITER_ENABLE (0)
178#define BM_BW_LIMITER_DISABLE (-1)
179
180#define M0_DOUBLE_HALF_BW_1CH (0x0)
181#define M0_DOUBLE_HALF_BW_2CH (0x1)
182#define M0_DOUBLE_HALF_BW_4CH (0x2)
183
184#ifdef CONFIG_MTK_TINYSYS_SSPM_SUPPORT
185/*ondiemet emi ipi command*/
186typedef enum {
187 SET_BASE_EMI = 0x0,
188 SET_BASE_DRAMC0,
189 SET_BASE_DRAMC1,
190 SET_BASE_DRAMC2,
191 SET_BASE_DRAMC3,
192 SET_BASE_DDRPHY0AO,
193 SET_BASE_DRAMC0_AO,
194 SET_EBM_CONFIGS,
195} BM_EMI_IPI_Type;
196#endif
197
198#define EMI_OFF 0x0000
199#define EMI_CONA (0x000-EMI_OFF)
200#define EMI_CONH (0x038-EMI_OFF)
201#define EMI_CONM (0x060-EMI_OFF)
202#define EMI_CONO (0x070-EMI_OFF)
203
204#define EMI_MDCT (0x078-EMI_OFF)
205#define EMI_MDCT_2ND (0x07C-EMI_OFF)
206
207#define EMI_ARBA (0x100-EMI_OFF)
208#define EMI_ARBB (0x108-EMI_OFF)
209#define EMI_ARBC (0x110-EMI_OFF)
210#define EMI_ARBD (0x118-EMI_OFF)
211#define EMI_ARBE (0x120-EMI_OFF)
212#define EMI_ARBF (0x128-EMI_OFF)
213#define EMI_ARBG (0x130-EMI_OFF)
214#define EMI_ARBG_2ND (0x134-EMI_OFF)
215#define EMI_ARBH (0x138-EMI_OFF)
216
217#define EMI_BMEN (0x400-EMI_OFF)
218#define EMI_BCNT (0x408-EMI_OFF)
219#define EMI_TACT (0x410-EMI_OFF)
220#define EMI_TSCT (0x418-EMI_OFF)
221#define EMI_WACT (0x420-EMI_OFF)
222#define EMI_WSCT (0x428-EMI_OFF)
223#define EMI_BACT (0x430-EMI_OFF)
224#define EMI_BSCT (0x438-EMI_OFF)
225
226#define EMI_MSEL (0x440-EMI_OFF)
227#define EMI_TSCT2 (0x448-EMI_OFF)
228#define EMI_TSCT3 (0x450-EMI_OFF)
229#define EMI_WSCT2 (0x458-EMI_OFF)
230#define EMI_WSCT3 (0x460-EMI_OFF)
231#define EMI_WSCT4 (0x464-EMI_OFF)
232#define EMI_MSEL2 (0x468-EMI_OFF)
233#define EMI_MSEL3 (0x470-EMI_OFF)
234#define EMI_MSEL4 (0x478-EMI_OFF)
235#define EMI_MSEL5 (0x480-EMI_OFF)
236#define EMI_MSEL6 (0x488-EMI_OFF)
237#define EMI_MSEL7 (0x490-EMI_OFF)
238#define EMI_MSEL8 (0x498-EMI_OFF)
239#define EMI_MSEL9 (0x4A0-EMI_OFF)
240#define EMI_MSEL10 (0x4A8-EMI_OFF)
241
242#define EMI_BMID0 (0x4B0-EMI_OFF)
243#define EMI_BMID1 (0x4B4-EMI_OFF)
244#define EMI_BMID2 (0x4B8-EMI_OFF)
245#define EMI_BMID3 (0x4BC-EMI_OFF)
246#define EMI_BMID4 (0x4C0-EMI_OFF)
247#define EMI_BMID5 (0x4C4-EMI_OFF)
248#define EMI_BMID6 (0x4C8-EMI_OFF)
249#define EMI_BMID7 (0x4CC-EMI_OFF)
250#define EMI_BMID8 (0x4D0-EMI_OFF)
251#define EMI_BMID9 (0x4D4-EMI_OFF)
252#define EMI_BMID10 (0x4D8-EMI_OFF)
253
254#define EMI_BMEN1 (0x4E0-EMI_OFF)
255#define EMI_BMEN2 (0x4E8-EMI_OFF)
256#define EMI_BMRW0 (0x4F8-EMI_OFF)
257#define EMI_BMRW1 (0x4FC-EMI_OFF)
258#define EMI_TTYPE1 (0x500-EMI_OFF)
259#define EMI_TTYPE2 (0x508-EMI_OFF)
260#define EMI_TTYPE3 (0x510-EMI_OFF)
261#define EMI_TTYPE4 (0x518-EMI_OFF)
262#define EMI_TTYPE5 (0x520-EMI_OFF)
263#define EMI_TTYPE6 (0x528-EMI_OFF)
264#define EMI_TTYPE7 (0x530-EMI_OFF)
265#define EMI_TTYPE8 (0x538-EMI_OFF)
266#define EMI_TTYPE9 (0x540-EMI_OFF)
267#define EMI_TTYPE10 (0x548-EMI_OFF)
268#define EMI_TTYPE11 (0x550-EMI_OFF)
269#define EMI_TTYPE12 (0x558-EMI_OFF)
270#define EMI_TTYPE13 (0x560-EMI_OFF)
271#define EMI_TTYPE14 (0x568-EMI_OFF)
272#define EMI_TTYPE15 (0x570-EMI_OFF)
273#define EMI_TTYPE16 (0x578-EMI_OFF)
274#define EMI_TTYPE17 (0x580-EMI_OFF)
275#define EMI_TTYPE18 (0x588-EMI_OFF)
276#define EMI_TTYPE19 (0x590-EMI_OFF)
277#define EMI_TTYPE20 (0x598-EMI_OFF)
278#define EMI_TTYPE21 (0x5A0-EMI_OFF)
279
280#define EMI_BWCT0 (0x5B0-EMI_OFF)
281#define EMI_BWCT1 (0x5B4-EMI_OFF)
282#define EMI_BWCT2 (0x5B8-EMI_OFF)
283#define EMI_BWCT3 (0x5BC-EMI_OFF)
284#define EMI_BWCT4 (0x5C0-EMI_OFF)
285#define EMI_BWST0 (0x5C4-EMI_OFF)
286#define EMI_BWST1 (0x5C8-EMI_OFF)
287
288#define EMI_BWCT0_2ND (0x6A0-EMI_OFF)
289#define EMI_BWCT1_2ND (0x6A4-EMI_OFF)
290#define EMI_BWST_2ND (0x6A8-EMI_OFF)
291
292#define DRAMC_DMMONITOR 0x24
293#define DRAMC_MISC_STATUSA 0x80
294#define DRAMC_REFRESH_POP 0x300
295#define DRAMC_FREERUN_26M 0x304
296#define DRAMC_R2R_PAGE_HIT 0x30C
297#define DRAMC_R2R_PAGE_MISS 0x310
298#define DRAMC_R2R_INTERBANK 0x314
299#define DRAMC_R2W_PAGE_HIT 0x318
300#define DRAMC_R2W_PAGE_MISS 0x31C
301#define DRAMC_R2W_INTERBANK 0x320
302#define DRAMC_W2R_PAGE_HIT 0x324
303#define DRAMC_W2R_PAGE_MISS 0x328
304#define DRAMC_W2R_INTERBANK 0x32C
305#define DRAMC_W2W_PAGE_HIT 0x330
306#define DRAMC_W2W_PAGE_MISS 0x334
307#define DRAMC_W2W_INTERBANK 0x338
308#define DRAMC_IDLE_COUNT 0x308
309#define DRAMC_RK0_PRE_STANDBY 0x33c
310#define DRAMC_RK0_PRE_POWERDOWN 0x340
311#define DRAMC_RK0_ACT_STANDBY 0x344
312#define DRAMC_RK0_ACT_POWERDOWN 0x348
313#define DRAMC_RK1_PRE_STANDBY 0x34c
314#define DRAMC_RK1_PRE_POWERDOWN 0x350
315#define DRAMC_RK1_ACT_STANDBY 0x354
316#define DRAMC_RK1_ACT_POWERDOWN 0x358
317#define DRAMC_RK2_PRE_STANDBY 0x35c
318#define DRAMC_RK2_PRE_POWERDOWN 0x360
319#define DRAMC_RK2_ACT_STANDBY 0x364
320#define DRAMC_RK2_ACT_POWERDOWN 0x368
321#define DRAMC_READ_BYTES 0x38c
322#define DRAMC_WRITE_BYTES 0x390
323
324
325extern void emi_dump_reg(void);
326extern int MET_BM_Init(void);
327extern void MET_BM_DeInit(void);
328extern void MET_BM_Enable(const unsigned int enable);
329extern void MET_BM_Pause(void);
330extern void MET_BM_Continue(void);
331extern unsigned int MET_BM_IsOverrun(void);
332extern unsigned int MET_BM_GetReadWriteType(void);
333extern void MET_BM_SetReadWriteType(const unsigned int ReadWriteType);
334extern int MET_BM_GetBusCycCount(void);
335extern unsigned int MET_BM_GetTransAllCount(void);
336extern int MET_BM_GetTransCount(const unsigned int counter_num);
337extern int MET_BM_GetWordAllCount(void);
338extern int MET_BM_GetWordCount(const unsigned int counter_num);
339extern unsigned int MET_BM_GetBandwidthWordCount(void);
340extern unsigned int MET_BM_GetOverheadWordCount(void);
341extern int MET_BM_GetTransTypeCount(const unsigned int counter_num);
342extern int MET_BM_GetMDCT(void);
343extern int MET_BM_GetMDCT_2(void);
344extern int MET_BM_GetMonitorCounter(const unsigned int counter_num,
345 unsigned int *master,
346 unsigned int *trans_type);
347extern int MET_BM_SetMDCT_MDMCU(unsigned int mdmcu_rd_buf);
348extern int MET_BM_SetMonitorCounter(const unsigned int counter_num,
349 const unsigned int master,
350 const unsigned int trans_type);
351extern int MET_BM_SetTtypeCounterRW(unsigned int bmrw0_val, unsigned int bmrw1_val);
352extern int MET_BM_Set_WsctTsct_id_sel(unsigned int counter_num, unsigned int enable);
353extern int MET_BM_SetMaster(const unsigned int counter_num,
354 const unsigned int master);
355extern int MET_BM_SetIDSelect(const unsigned int counter_num,
356 const unsigned int id,
357 const unsigned int enable);
358extern int MET_BM_SetUltraHighFilter(const unsigned int counter_num,
359 const unsigned int enable);
360extern int MET_BM_SetLatencyCounter(unsigned int enable);
361extern int MET_BM_GetLatencyCycle(const unsigned int counter_num);
362extern unsigned int MET_BM_GetEmiDcm(void);
363extern int MET_BM_SetEmiDcm(const unsigned int setting);
364
365/* DRAMC */
366extern unsigned int MET_DRAMC_GetPageHitCount(DRAMC_Cnt_Type CountType, int chann);
367extern unsigned int MET_DRAMC_GetPageMissCount(DRAMC_Cnt_Type CountType, int chann);
368extern unsigned int MET_DRAMC_GetInterbankCount(DRAMC_Cnt_Type CountType, int chann);
369extern unsigned int MET_DRAMC_GetIdleCount(int chann);
370extern unsigned int MET_DRAMC_Misc_Status(int chann);
371extern unsigned int MET_DRAMC_RefPop(int chann);
372extern unsigned int MET_DRAMC_Free26M(int chann);
373extern unsigned int MET_DRAMC_RByte(int chann);
374extern unsigned int MET_DRAMC_WByte(int chann);
375extern int MET_DRAMC_BMEnable(int chann, int set);
376extern int MET_DRAMC_BMPause(int chann, int set);
377extern unsigned int get_dram_data_rate(void);
378
379/* Config */
380unsigned int MET_EMI_GetARBA(void);
381unsigned int MET_EMI_GetARBB(void);
382unsigned int MET_EMI_GetARBC(void);
383unsigned int MET_EMI_GetARBD(void);
384unsigned int MET_EMI_GetARBE(void);
385unsigned int MET_EMI_GetARBF(void);
386unsigned int MET_EMI_GetARBG(void);
387unsigned int MET_EMI_GetARBH(void);
388
389/* Total BW status */
390extern unsigned int MET_EMI_GetBWCT0(void);
391extern unsigned int MET_EMI_GetBWCT1(void);
392extern unsigned int MET_EMI_GetBWCT2(void);
393extern unsigned int MET_EMI_GetBWCT3(void);
394extern unsigned int MET_EMI_GetBWCT4(void);
395extern unsigned int MET_EMI_GetBWST0(void);
396extern unsigned int MET_EMI_GetBWST1(void);
397/* C+G BW */
398extern unsigned int MET_EMI_GetBWCT0_2ND(void);
399extern unsigned int MET_EMI_GetBWCT1_2ND(void);
400extern unsigned int MET_EMI_GetBWST_2ND(void);
401
402unsigned int MET_EMI_GetBMRW0(void);
403unsigned int MET_EMI_GetDramChannNum(void);
404
405/* Debug Counter status */
406void MET_DRAMC_GetDebugCounter(int *value, int chann);
407
408/* ondiemet*/
409void MET_BM_IPI_baseaddr(void);
410void met_emi_phyaddr_debug(void);
411
412
413
414#endif /* !__MT_MET_EMI_BM_H__ */