| rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (C) 2018 MediaTek Inc. |
| 3 | * |
| 4 | * This program is free software: you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | |
| 15 | #ifndef _V8_PMU_NAME_H_ |
| 16 | #define _V8_PMU_NAME_H_ |
| 17 | |
| 18 | /* Cortex-A53 */ |
| 19 | struct pmu_desc a53_pmu_desc[] = { |
| 20 | {0x00, "SW_INCR"}, |
| 21 | {0x01, "L1I_CACHE_REFILL"}, |
| 22 | {0x02, "L1I_TLB_REFILL"}, |
| 23 | {0x03, "L1D_CACHE_REFILL"}, |
| 24 | {0x04, "L1D_CACHE"}, |
| 25 | {0x05, "L1D_TLB_REFILL"}, |
| 26 | {0x06, "LD_RETIRED"}, |
| 27 | {0x07, "ST_RETIRED"}, |
| 28 | {0x08, "INST_RETIRED"}, |
| 29 | {0x09, "EXC_TAKEN"}, |
| 30 | {0x0A, "EXC_RETURN"}, |
| 31 | {0x0B, "CID_WRITE_RETIRED"}, |
| 32 | {0x0C, "PC_WRITE_RETIRED"}, |
| 33 | {0x0D, "BR_IMMED_RETIRED"}, |
| 34 | {0x0E, "BR_RETURN_RETIRED"}, |
| 35 | {0x0F, "UNALIGNED_LDST_RETIRED"}, |
| 36 | {0x10, "BR_MIS_PRED"}, |
| 37 | {0x11, "CPU_CYCLES"}, |
| 38 | {0x12, "BR_PRED"}, |
| 39 | {0x13, "MEM_ACCESS"}, |
| 40 | {0x14, "L1I_CACHE"}, |
| 41 | {0x15, "L1D_CACHE_WB"}, |
| 42 | {0x16, "L2D_CACHE"}, |
| 43 | {0x17, "L2D_CACHE_REFILL"}, |
| 44 | {0x18, "L2D_CACHE_WB"}, |
| 45 | {0x19, "BUS_ACCESS"}, |
| 46 | {0x1A, "MEMORY_ERROR"}, |
| 47 | {0x1D, "BUS_CYCLES"}, |
| 48 | {0x60, "BUS_READ_ACCESS"}, |
| 49 | {0x61, "BUS_WRITE_ACCESS"}, |
| 50 | {0x86, "IRQ_EXC_TAKEN"}, |
| 51 | {0x87, "FIQ_EXC_TAKEN"}, |
| 52 | {0xC0, "EXT_MEM_REQ"}, |
| 53 | {0xC1, "NO_CACHE_EXT_MEM_REQ"}, |
| 54 | {0xC2, "PREFETCH_LINEFILL"}, |
| 55 | {0xC4, "ENT_READ_ALLOC_MODE"}, |
| 56 | {0xC5, "READ_ALLOC_MODE"}, |
| 57 | {0xC6, "PRE_DECODE_ERROR"}, |
| 58 | {0xC7, "WRITE_STALL"}, |
| 59 | {0xC8, "SCU_SNOOP_DATA_FROM_ANOTHER_CPU"}, |
| 60 | {0xC9, "CONDITIONAL_BRANCH_EXE"}, |
| 61 | {0xCA, "INDIRECT_BRANCH_MISPREDICT"}, |
| 62 | {0xCB, "INDIRECT_BRANCH_MISPREDICT_ADDR"},/*"INDIRECT_BRANCH_MISPREDICT_ADDR_MISSCOMPARE" */ |
| 63 | {0xCC, "COND_BRANCH_MISPREDICT"}, |
| 64 | {0xD0, "L1_INST_CACHE_MEM_ERR"}, |
| 65 | {0xE1, "ICACHE_MISS_STALL"}, |
| 66 | {0xE2, "DPU_IQ_EMPTY"}, |
| 67 | {0xE4, "NOT_FPU_NEON_INTERLOCK"}, |
| 68 | {0xE5, "LOAD_STORE_INTERLOCK"}, |
| 69 | {0xE6, "FPU_NEON_INTERLOCK"}, |
| 70 | {0xE7, "LOAD_MISS_STALL"}, |
| 71 | {0xE8, "STORE_STALL"}, |
| 72 | {0xFF, "CPU_CYCLES"} |
| 73 | }; |
| 74 | |
| 75 | #define A53_PMU_DESC_COUNT (sizeof(a53_pmu_desc) / sizeof(struct pmu_desc)) |
| 76 | |
| 77 | #endif /* _V8_PMU_NAME_H_ */ |