| rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame^] | 1 | ================================== |
| 2 | ASoC Digital Audio Interface (DAI) |
| 3 | ================================== |
| 4 | |
| 5 | ASoC currently supports the three main Digital Audio Interfaces (DAI) found on |
| 6 | SoC controllers and portable audio CODECs today, namely AC97, I2S and PCM. |
| 7 | |
| 8 | |
| 9 | AC97 |
| 10 | ==== |
| 11 | |
| 12 | AC97 is a five wire interface commonly found on many PC sound cards. It is |
| 13 | now also popular in many portable devices. This DAI has a reset line and time |
| 14 | multiplexes its data on its SDATA_OUT (playback) and SDATA_IN (capture) lines. |
| 15 | The bit clock (BCLK) is always driven by the CODEC (usually 12.288MHz) and the |
| 16 | frame (FRAME) (usually 48kHz) is always driven by the controller. Each AC97 |
| 17 | frame is 21uS long and is divided into 13 time slots. |
| 18 | |
| 19 | The AC97 specification can be found at : |
| 20 | http://www.intel.com/p/en_US/business/design |
| 21 | |
| 22 | |
| 23 | I2S |
| 24 | === |
| 25 | |
| 26 | I2S is a common 4 wire DAI used in HiFi, STB and portable devices. The Tx and |
| 27 | Rx lines are used for audio transmission, whilst the bit clock (BCLK) and |
| 28 | left/right clock (LRC) synchronise the link. I2S is flexible in that either the |
| 29 | controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock |
| 30 | usually varies depending on the sample rate and the master system clock |
| 31 | (SYSCLK). LRCLK is the same as the sample rate. A few devices support separate |
| 32 | ADC and DAC LRCLKs, this allows for simultaneous capture and playback at |
| 33 | different sample rates. |
| 34 | |
| 35 | I2S has several different operating modes:- |
| 36 | |
| 37 | I2S |
| 38 | MSB is transmitted on the falling edge of the first BCLK after LRC |
| 39 | transition. |
| 40 | |
| 41 | Left Justified |
| 42 | MSB is transmitted on transition of LRC. |
| 43 | |
| 44 | Right Justified |
| 45 | MSB is transmitted sample size BCLKs before LRC transition. |
| 46 | |
| 47 | PCM |
| 48 | === |
| 49 | |
| 50 | PCM is another 4 wire interface, very similar to I2S, which can support a more |
| 51 | flexible protocol. It has bit clock (BCLK) and sync (SYNC) lines that are used |
| 52 | to synchronise the link whilst the Tx and Rx lines are used to transmit and |
| 53 | receive the audio data. Bit clock usually varies depending on sample rate |
| 54 | whilst sync runs at the sample rate. PCM also supports Time Division |
| 55 | Multiplexing (TDM) in that several devices can use the bus simultaneously (this |
| 56 | is sometimes referred to as network mode). |
| 57 | |
| 58 | Common PCM operating modes:- |
| 59 | |
| 60 | Mode A |
| 61 | MSB is transmitted on falling edge of first BCLK after FRAME/SYNC. |
| 62 | |
| 63 | Mode B |
| 64 | MSB is transmitted on rising edge of FRAME/SYNC. |