| rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame^] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | # |
| 3 | # For a description of the syntax of this configuration file, |
| 4 | # see Documentation/kbuild/kconfig-language.txt. |
| 5 | # |
| 6 | |
| 7 | menuconfig ARC_PLAT_EZNPS |
| 8 | bool "\"EZchip\" ARC dev platform" |
| 9 | depends on ISA_ARCOMPACT |
| 10 | select CPU_BIG_ENDIAN |
| 11 | select CLKSRC_NPS if !PHYS_ADDR_T_64BIT |
| 12 | select EZNPS_GIC |
| 13 | select EZCHIP_NPS_MANAGEMENT_ENET if ETHERNET |
| 14 | help |
| 15 | Support for EZchip development platforms, |
| 16 | based on ARC700 cores. |
| 17 | We handle few flavors: |
| 18 | - Hardware Emulator AKA HE which is FPGA based chassis |
| 19 | - Simulator based on MetaWare nSIM |
| 20 | - NPS400 chip based on ASIC |
| 21 | |
| 22 | config EZNPS_MTM_EXT |
| 23 | bool "ARC-EZchip MTM Extensions" |
| 24 | select CPUMASK_OFFSTACK |
| 25 | depends on ARC_PLAT_EZNPS && SMP |
| 26 | default y |
| 27 | help |
| 28 | Here we add new hierarchy for CPUs topology. |
| 29 | We got: |
| 30 | Core |
| 31 | Thread |
| 32 | At the new thread level each CPU represent one HW thread. |
| 33 | At highest hierarchy each core contain 16 threads, |
| 34 | any of them seem like CPU from Linux point of view. |
| 35 | All threads within same core share the execution unit of the |
| 36 | core and HW scheduler round robin between them. |
| 37 | |
| 38 | config EZNPS_MEM_ERROR_ALIGN |
| 39 | bool "ARC-EZchip Memory error as an exception" |
| 40 | depends on EZNPS_MTM_EXT |
| 41 | default n |
| 42 | help |
| 43 | On the real chip of the NPS, user memory errors are handled |
| 44 | as a machine check exception, which is fatal, whereas on |
| 45 | simulator platform for NPS, is handled as a Level 2 interrupt |
| 46 | (just a stock ARC700) which is recoverable. This option makes |
| 47 | simulator behave like hardware. |
| 48 | |
| 49 | config EZNPS_SHARED_AUX_REGS |
| 50 | bool "ARC-EZchip Shared Auxiliary Registers Per Core" |
| 51 | depends on ARC_PLAT_EZNPS |
| 52 | default y |
| 53 | help |
| 54 | On the real chip of the NPS, auxiliary registers are shared between |
| 55 | all the cpus of the core, whereas on simulator platform for NPS, |
| 56 | each cpu has a different set of auxiliary registers. Configuration |
| 57 | should be unset if auxiliary registers are not shared between the cpus |
| 58 | of the core, so there will be a need to initialize them per cpu. |