rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (C) 2009 Sascha Hauer, Pengutronix |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #include <linux/types.h> |
| 16 | #include <linux/init.h> |
| 17 | |
| 18 | #include <linux/platform_device.h> |
| 19 | #include <linux/mtd/physmap.h> |
| 20 | #include <linux/mtd/plat-ram.h> |
| 21 | #include <linux/memory.h> |
| 22 | #include <linux/gpio.h> |
| 23 | #include <linux/smc911x.h> |
| 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/delay.h> |
| 26 | #include <linux/i2c.h> |
| 27 | #include <linux/platform_data/at24.h> |
| 28 | #include <linux/usb/otg.h> |
| 29 | #include <linux/usb/ulpi.h> |
| 30 | |
| 31 | #include <asm/mach-types.h> |
| 32 | #include <asm/mach/arch.h> |
| 33 | #include <asm/mach/time.h> |
| 34 | #include <asm/mach/map.h> |
| 35 | |
| 36 | #include "common.h" |
| 37 | #include "devices-imx35.h" |
| 38 | #include "ehci.h" |
| 39 | #include "hardware.h" |
| 40 | #include "iomux-mx35.h" |
| 41 | #include "ulpi.h" |
| 42 | |
| 43 | static const struct fb_videomode fb_modedb[] = { |
| 44 | { |
| 45 | /* 240x320 @ 60 Hz */ |
| 46 | .name = "Sharp-LQ035Q7", |
| 47 | .refresh = 60, |
| 48 | .xres = 240, |
| 49 | .yres = 320, |
| 50 | .pixclock = 185925, |
| 51 | .left_margin = 9, |
| 52 | .right_margin = 16, |
| 53 | .upper_margin = 7, |
| 54 | .lower_margin = 9, |
| 55 | .hsync_len = 1, |
| 56 | .vsync_len = 1, |
| 57 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN, |
| 58 | .vmode = FB_VMODE_NONINTERLACED, |
| 59 | .flag = 0, |
| 60 | }, { |
| 61 | /* 240x320 @ 60 Hz */ |
| 62 | .name = "TX090", |
| 63 | .refresh = 60, |
| 64 | .xres = 240, |
| 65 | .yres = 320, |
| 66 | .pixclock = 38255, |
| 67 | .left_margin = 144, |
| 68 | .right_margin = 0, |
| 69 | .upper_margin = 7, |
| 70 | .lower_margin = 40, |
| 71 | .hsync_len = 96, |
| 72 | .vsync_len = 1, |
| 73 | .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, |
| 74 | .vmode = FB_VMODE_NONINTERLACED, |
| 75 | .flag = 0, |
| 76 | }, |
| 77 | }; |
| 78 | |
| 79 | static struct mx3fb_platform_data mx3fb_pdata __initdata = { |
| 80 | .name = "Sharp-LQ035Q7", |
| 81 | .mode = fb_modedb, |
| 82 | .num_modes = ARRAY_SIZE(fb_modedb), |
| 83 | }; |
| 84 | |
| 85 | static struct physmap_flash_data pcm043_flash_data = { |
| 86 | .width = 2, |
| 87 | }; |
| 88 | |
| 89 | static struct resource pcm043_flash_resource = { |
| 90 | .start = 0xa0000000, |
| 91 | .end = 0xa1ffffff, |
| 92 | .flags = IORESOURCE_MEM, |
| 93 | }; |
| 94 | |
| 95 | static struct platform_device pcm043_flash = { |
| 96 | .name = "physmap-flash", |
| 97 | .id = 0, |
| 98 | .dev = { |
| 99 | .platform_data = &pcm043_flash_data, |
| 100 | }, |
| 101 | .resource = &pcm043_flash_resource, |
| 102 | .num_resources = 1, |
| 103 | }; |
| 104 | |
| 105 | static const struct imxuart_platform_data uart_pdata __initconst = { |
| 106 | .flags = IMXUART_HAVE_RTSCTS, |
| 107 | }; |
| 108 | |
| 109 | static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = { |
| 110 | .bitrate = 50000, |
| 111 | }; |
| 112 | |
| 113 | static struct at24_platform_data board_eeprom = { |
| 114 | .byte_len = 4096, |
| 115 | .page_size = 32, |
| 116 | .flags = AT24_FLAG_ADDR16, |
| 117 | }; |
| 118 | |
| 119 | static struct i2c_board_info pcm043_i2c_devices[] = { |
| 120 | { |
| 121 | I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ |
| 122 | .platform_data = &board_eeprom, |
| 123 | }, { |
| 124 | I2C_BOARD_INFO("pcf8563", 0x51), |
| 125 | }, |
| 126 | }; |
| 127 | |
| 128 | static struct platform_device *devices[] __initdata = { |
| 129 | &pcm043_flash, |
| 130 | }; |
| 131 | |
| 132 | static const iomux_v3_cfg_t pcm043_pads[] __initconst = { |
| 133 | /* UART1 */ |
| 134 | MX35_PAD_CTS1__UART1_CTS, |
| 135 | MX35_PAD_RTS1__UART1_RTS, |
| 136 | MX35_PAD_TXD1__UART1_TXD_MUX, |
| 137 | MX35_PAD_RXD1__UART1_RXD_MUX, |
| 138 | /* UART2 */ |
| 139 | MX35_PAD_CTS2__UART2_CTS, |
| 140 | MX35_PAD_RTS2__UART2_RTS, |
| 141 | MX35_PAD_TXD2__UART2_TXD_MUX, |
| 142 | MX35_PAD_RXD2__UART2_RXD_MUX, |
| 143 | /* FEC */ |
| 144 | MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, |
| 145 | MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, |
| 146 | MX35_PAD_FEC_RX_DV__FEC_RX_DV, |
| 147 | MX35_PAD_FEC_COL__FEC_COL, |
| 148 | MX35_PAD_FEC_RDATA0__FEC_RDATA_0, |
| 149 | MX35_PAD_FEC_TDATA0__FEC_TDATA_0, |
| 150 | MX35_PAD_FEC_TX_EN__FEC_TX_EN, |
| 151 | MX35_PAD_FEC_MDC__FEC_MDC, |
| 152 | MX35_PAD_FEC_MDIO__FEC_MDIO, |
| 153 | MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, |
| 154 | MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, |
| 155 | MX35_PAD_FEC_CRS__FEC_CRS, |
| 156 | MX35_PAD_FEC_RDATA1__FEC_RDATA_1, |
| 157 | MX35_PAD_FEC_TDATA1__FEC_TDATA_1, |
| 158 | MX35_PAD_FEC_RDATA2__FEC_RDATA_2, |
| 159 | MX35_PAD_FEC_TDATA2__FEC_TDATA_2, |
| 160 | MX35_PAD_FEC_RDATA3__FEC_RDATA_3, |
| 161 | MX35_PAD_FEC_TDATA3__FEC_TDATA_3, |
| 162 | /* I2C1 */ |
| 163 | MX35_PAD_I2C1_CLK__I2C1_SCL, |
| 164 | MX35_PAD_I2C1_DAT__I2C1_SDA, |
| 165 | /* Display */ |
| 166 | MX35_PAD_LD0__IPU_DISPB_DAT_0, |
| 167 | MX35_PAD_LD1__IPU_DISPB_DAT_1, |
| 168 | MX35_PAD_LD2__IPU_DISPB_DAT_2, |
| 169 | MX35_PAD_LD3__IPU_DISPB_DAT_3, |
| 170 | MX35_PAD_LD4__IPU_DISPB_DAT_4, |
| 171 | MX35_PAD_LD5__IPU_DISPB_DAT_5, |
| 172 | MX35_PAD_LD6__IPU_DISPB_DAT_6, |
| 173 | MX35_PAD_LD7__IPU_DISPB_DAT_7, |
| 174 | MX35_PAD_LD8__IPU_DISPB_DAT_8, |
| 175 | MX35_PAD_LD9__IPU_DISPB_DAT_9, |
| 176 | MX35_PAD_LD10__IPU_DISPB_DAT_10, |
| 177 | MX35_PAD_LD11__IPU_DISPB_DAT_11, |
| 178 | MX35_PAD_LD12__IPU_DISPB_DAT_12, |
| 179 | MX35_PAD_LD13__IPU_DISPB_DAT_13, |
| 180 | MX35_PAD_LD14__IPU_DISPB_DAT_14, |
| 181 | MX35_PAD_LD15__IPU_DISPB_DAT_15, |
| 182 | MX35_PAD_LD16__IPU_DISPB_DAT_16, |
| 183 | MX35_PAD_LD17__IPU_DISPB_DAT_17, |
| 184 | MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, |
| 185 | MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, |
| 186 | MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, |
| 187 | MX35_PAD_CONTRAST__IPU_DISPB_CONTR, |
| 188 | MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, |
| 189 | MX35_PAD_D3_REV__IPU_DISPB_D3_REV, |
| 190 | MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS, |
| 191 | /* gpio */ |
| 192 | MX35_PAD_ATA_CS0__GPIO2_6, |
| 193 | /* USB host */ |
| 194 | MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR, |
| 195 | MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC, |
| 196 | /* SSI */ |
| 197 | MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS, |
| 198 | MX35_PAD_STXD4__AUDMUX_AUD4_TXD, |
| 199 | MX35_PAD_SRXD4__AUDMUX_AUD4_RXD, |
| 200 | MX35_PAD_SCK4__AUDMUX_AUD4_TXC, |
| 201 | /* CAN2 */ |
| 202 | MX35_PAD_TX5_RX0__CAN2_TXCAN, |
| 203 | MX35_PAD_TX4_RX1__CAN2_RXCAN, |
| 204 | /* esdhc */ |
| 205 | MX35_PAD_SD1_CMD__ESDHC1_CMD, |
| 206 | MX35_PAD_SD1_CLK__ESDHC1_CLK, |
| 207 | MX35_PAD_SD1_DATA0__ESDHC1_DAT0, |
| 208 | MX35_PAD_SD1_DATA1__ESDHC1_DAT1, |
| 209 | MX35_PAD_SD1_DATA2__ESDHC1_DAT2, |
| 210 | MX35_PAD_SD1_DATA3__ESDHC1_DAT3, |
| 211 | MX35_PAD_ATA_DATA10__GPIO2_23, /* WriteProtect */ |
| 212 | MX35_PAD_ATA_DATA11__GPIO2_24, /* CardDetect */ |
| 213 | }; |
| 214 | |
| 215 | #define AC97_GPIO_TXFS IMX_GPIO_NR(2, 31) |
| 216 | #define AC97_GPIO_TXD IMX_GPIO_NR(2, 28) |
| 217 | #define AC97_GPIO_RESET IMX_GPIO_NR(2, 0) |
| 218 | #define SD1_GPIO_WP IMX_GPIO_NR(2, 23) |
| 219 | #define SD1_GPIO_CD IMX_GPIO_NR(2, 24) |
| 220 | |
| 221 | static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) |
| 222 | { |
| 223 | iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; |
| 224 | iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; |
| 225 | int ret; |
| 226 | |
| 227 | ret = gpio_request(AC97_GPIO_TXFS, "SSI"); |
| 228 | if (ret) { |
| 229 | printk("failed to get GPIO_TXFS: %d\n", ret); |
| 230 | return; |
| 231 | } |
| 232 | |
| 233 | mxc_iomux_v3_setup_pad(txfs_gpio); |
| 234 | |
| 235 | /* warm reset */ |
| 236 | gpio_direction_output(AC97_GPIO_TXFS, 1); |
| 237 | udelay(2); |
| 238 | gpio_set_value(AC97_GPIO_TXFS, 0); |
| 239 | |
| 240 | gpio_free(AC97_GPIO_TXFS); |
| 241 | mxc_iomux_v3_setup_pad(txfs); |
| 242 | } |
| 243 | |
| 244 | static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) |
| 245 | { |
| 246 | iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; |
| 247 | iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; |
| 248 | iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28; |
| 249 | iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD; |
| 250 | iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0; |
| 251 | int ret; |
| 252 | |
| 253 | ret = gpio_request(AC97_GPIO_TXFS, "SSI"); |
| 254 | if (ret) |
| 255 | goto err1; |
| 256 | |
| 257 | ret = gpio_request(AC97_GPIO_TXD, "SSI"); |
| 258 | if (ret) |
| 259 | goto err2; |
| 260 | |
| 261 | ret = gpio_request(AC97_GPIO_RESET, "SSI"); |
| 262 | if (ret) |
| 263 | goto err3; |
| 264 | |
| 265 | mxc_iomux_v3_setup_pad(txfs_gpio); |
| 266 | mxc_iomux_v3_setup_pad(txd_gpio); |
| 267 | mxc_iomux_v3_setup_pad(reset_gpio); |
| 268 | |
| 269 | gpio_direction_output(AC97_GPIO_TXFS, 0); |
| 270 | gpio_direction_output(AC97_GPIO_TXD, 0); |
| 271 | |
| 272 | /* cold reset */ |
| 273 | gpio_direction_output(AC97_GPIO_RESET, 0); |
| 274 | udelay(10); |
| 275 | gpio_direction_output(AC97_GPIO_RESET, 1); |
| 276 | |
| 277 | mxc_iomux_v3_setup_pad(txd); |
| 278 | mxc_iomux_v3_setup_pad(txfs); |
| 279 | |
| 280 | gpio_free(AC97_GPIO_RESET); |
| 281 | err3: |
| 282 | gpio_free(AC97_GPIO_TXD); |
| 283 | err2: |
| 284 | gpio_free(AC97_GPIO_TXFS); |
| 285 | err1: |
| 286 | if (ret) |
| 287 | printk("%s failed with %d\n", __func__, ret); |
| 288 | mdelay(1); |
| 289 | } |
| 290 | |
| 291 | static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = { |
| 292 | .ac97_reset = pcm043_ac97_cold_reset, |
| 293 | .ac97_warm_reset = pcm043_ac97_warm_reset, |
| 294 | .flags = IMX_SSI_USE_AC97, |
| 295 | }; |
| 296 | |
| 297 | static const struct mxc_nand_platform_data |
| 298 | pcm037_nand_board_info __initconst = { |
| 299 | .width = 1, |
| 300 | .hw_ecc = 1, |
| 301 | }; |
| 302 | |
| 303 | static int pcm043_otg_init(struct platform_device *pdev) |
| 304 | { |
| 305 | return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); |
| 306 | } |
| 307 | |
| 308 | static struct mxc_usbh_platform_data otg_pdata __initdata = { |
| 309 | .init = pcm043_otg_init, |
| 310 | .portsc = MXC_EHCI_MODE_UTMI, |
| 311 | }; |
| 312 | |
| 313 | static int pcm043_usbh1_init(struct platform_device *pdev) |
| 314 | { |
| 315 | return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI | |
| 316 | MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN); |
| 317 | } |
| 318 | |
| 319 | static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { |
| 320 | .init = pcm043_usbh1_init, |
| 321 | .portsc = MXC_EHCI_MODE_SERIAL, |
| 322 | }; |
| 323 | |
| 324 | static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { |
| 325 | .operating_mode = FSL_USB2_DR_DEVICE, |
| 326 | .phy_mode = FSL_USB2_PHY_UTMI, |
| 327 | }; |
| 328 | |
| 329 | static bool otg_mode_host __initdata; |
| 330 | |
| 331 | static int __init pcm043_otg_mode(char *options) |
| 332 | { |
| 333 | if (!strcmp(options, "host")) |
| 334 | otg_mode_host = true; |
| 335 | else if (!strcmp(options, "device")) |
| 336 | otg_mode_host = false; |
| 337 | else |
| 338 | pr_info("otg_mode neither \"host\" nor \"device\". " |
| 339 | "Defaulting to device\n"); |
| 340 | return 1; |
| 341 | } |
| 342 | __setup("otg_mode=", pcm043_otg_mode); |
| 343 | |
| 344 | static struct esdhc_platform_data sd1_pdata = { |
| 345 | .wp_gpio = SD1_GPIO_WP, |
| 346 | .cd_gpio = SD1_GPIO_CD, |
| 347 | .wp_type = ESDHC_WP_GPIO, |
| 348 | .cd_type = ESDHC_CD_GPIO, |
| 349 | }; |
| 350 | |
| 351 | /* |
| 352 | * Board specific initialization. |
| 353 | */ |
| 354 | static void __init pcm043_init(void) |
| 355 | { |
| 356 | imx35_soc_init(); |
| 357 | |
| 358 | mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); |
| 359 | |
| 360 | imx35_add_fec(NULL); |
| 361 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 362 | imx35_add_imx2_wdt(); |
| 363 | |
| 364 | imx35_add_imx_uart0(&uart_pdata); |
| 365 | imx35_add_mxc_nand(&pcm037_nand_board_info); |
| 366 | |
| 367 | imx35_add_imx_uart1(&uart_pdata); |
| 368 | |
| 369 | i2c_register_board_info(0, pcm043_i2c_devices, |
| 370 | ARRAY_SIZE(pcm043_i2c_devices)); |
| 371 | |
| 372 | imx35_add_imx_i2c0(&pcm043_i2c0_data); |
| 373 | |
| 374 | imx35_add_ipu_core(); |
| 375 | imx35_add_mx3_sdc_fb(&mx3fb_pdata); |
| 376 | |
| 377 | if (otg_mode_host) { |
| 378 | otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | |
| 379 | ULPI_OTG_DRVVBUS_EXT); |
| 380 | if (otg_pdata.otg) |
| 381 | imx35_add_mxc_ehci_otg(&otg_pdata); |
| 382 | } |
| 383 | imx35_add_mxc_ehci_hs(&usbh1_pdata); |
| 384 | |
| 385 | if (!otg_mode_host) |
| 386 | imx35_add_fsl_usb2_udc(&otg_device_pdata); |
| 387 | |
| 388 | imx35_add_flexcan1(); |
| 389 | } |
| 390 | |
| 391 | static void __init pcm043_late_init(void) |
| 392 | { |
| 393 | imx35_add_imx_ssi(0, &pcm043_ssi_pdata); |
| 394 | |
| 395 | imx35_add_sdhci_esdhc_imx(0, &sd1_pdata); |
| 396 | } |
| 397 | |
| 398 | static void __init pcm043_timer_init(void) |
| 399 | { |
| 400 | mx35_clocks_init(); |
| 401 | } |
| 402 | |
| 403 | MACHINE_START(PCM043, "Phytec Phycore pcm043") |
| 404 | /* Maintainer: Pengutronix */ |
| 405 | .atag_offset = 0x100, |
| 406 | .map_io = mx35_map_io, |
| 407 | .init_early = imx35_init_early, |
| 408 | .init_irq = mx35_init_irq, |
| 409 | .init_time = pcm043_timer_init, |
| 410 | .init_machine = pcm043_init, |
| 411 | .init_late = pcm043_late_init, |
| 412 | .restart = mxc_restart, |
| 413 | MACHINE_END |