| rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * OMAP54xx Clock Management register bits |
| 3 | * |
| 4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com |
| 5 | * |
| 6 | * Paul Walmsley (paul@pwsan.com) |
| 7 | * Rajendra Nayak (rnayak@ti.com) |
| 8 | * Benoit Cousson (b-cousson@ti.com) |
| 9 | * |
| 10 | * This file is automatically generated from the OMAP hardware databases. |
| 11 | * We respectfully ask that any modifications to this file be coordinated |
| 12 | * with the public linux-omap@vger.kernel.org mailing list and the |
| 13 | * authors above to ensure that the autogeneration scripts are kept |
| 14 | * up-to-date with the file contents. |
| 15 | * |
| 16 | * This program is free software; you can redistribute it and/or modify |
| 17 | * it under the terms of the GNU General Public License version 2 as |
| 18 | * published by the Free Software Foundation. |
| 19 | */ |
| 20 | |
| 21 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H |
| 22 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H |
| 23 | |
| 24 | #define OMAP54XX_ABE_STATDEP_SHIFT 3 |
| 25 | #define OMAP54XX_AUTO_DPLL_MODE_MASK (0x7 << 0) |
| 26 | #define OMAP54XX_CLKSEL_SHIFT 24 |
| 27 | #define OMAP54XX_CLKSEL_WIDTH 0x1 |
| 28 | #define OMAP54XX_CLKSEL_0_0_SHIFT 0 |
| 29 | #define OMAP54XX_CLKSEL_0_0_WIDTH 0x1 |
| 30 | #define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT 24 |
| 31 | #define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH 0x1 |
| 32 | #define OMAP54XX_CLKSEL_DIV_SHIFT 25 |
| 33 | #define OMAP54XX_CLKSEL_DIV_WIDTH 0x1 |
| 34 | #define OMAP54XX_CLKSEL_FCLK_SHIFT 24 |
| 35 | #define OMAP54XX_CLKSEL_FCLK_WIDTH 0x1 |
| 36 | #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT 24 |
| 37 | #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH 0x1 |
| 38 | #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT 25 |
| 39 | #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH 0x1 |
| 40 | #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT 26 |
| 41 | #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH 0x2 |
| 42 | #define OMAP54XX_CLKSEL_OPP_SHIFT 0 |
| 43 | #define OMAP54XX_CLKSEL_OPP_WIDTH 0x2 |
| 44 | #define OMAP54XX_CLKSEL_SOURCE_SHIFT 24 |
| 45 | #define OMAP54XX_CLKSEL_SOURCE_WIDTH 0x2 |
| 46 | #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT 24 |
| 47 | #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH 0x1 |
| 48 | #define OMAP54XX_CLKSEL_UTMI_P1_SHIFT 24 |
| 49 | #define OMAP54XX_CLKSEL_UTMI_P1_WIDTH 0x1 |
| 50 | #define OMAP54XX_CLKSEL_UTMI_P2_SHIFT 25 |
| 51 | #define OMAP54XX_CLKSEL_UTMI_P2_WIDTH 0x1 |
| 52 | #define OMAP54XX_DIVHS_MASK (0x3f << 0) |
| 53 | #define OMAP54XX_DIVHS_0_4_MASK (0x1f << 0) |
| 54 | #define OMAP54XX_DIVHS_0_6_MASK (0x7f << 0) |
| 55 | #define OMAP54XX_DPLL_DIV_MASK (0x7f << 0) |
| 56 | #define OMAP54XX_DPLL_EN_MASK (0x7 << 0) |
| 57 | #define OMAP54XX_DPLL_LPMODE_EN_MASK (1 << 10) |
| 58 | #define OMAP54XX_DPLL_MULT_MASK (0x7ff << 8) |
| 59 | #define OMAP54XX_DPLL_REGM4XEN_MASK (1 << 11) |
| 60 | #define OMAP54XX_DPLL_SD_DIV_MASK (0xff << 24) |
| 61 | #define OMAP54XX_DSP_STATDEP_SHIFT 1 |
| 62 | #define OMAP54XX_DSS_STATDEP_SHIFT 8 |
| 63 | #define OMAP54XX_EMIF_STATDEP_SHIFT 4 |
| 64 | #define OMAP54XX_GPU_STATDEP_SHIFT 10 |
| 65 | #define OMAP54XX_IPU_STATDEP_SHIFT 0 |
| 66 | #define OMAP54XX_IVA_STATDEP_SHIFT 2 |
| 67 | #define OMAP54XX_L3INIT_STATDEP_SHIFT 7 |
| 68 | #define OMAP54XX_L3MAIN1_STATDEP_SHIFT 5 |
| 69 | #define OMAP54XX_L3MAIN2_STATDEP_SHIFT 6 |
| 70 | #define OMAP54XX_L4CFG_STATDEP_SHIFT 12 |
| 71 | #define OMAP54XX_L4PER_STATDEP_SHIFT 13 |
| 72 | #define OMAP54XX_L4SEC_STATDEP_SHIFT 14 |
| 73 | #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT 11 |
| 74 | #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT 8 |
| 75 | #define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT 9 |
| 76 | #define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT 8 |
| 77 | #define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT 8 |
| 78 | #define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT 8 |
| 79 | #define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT 8 |
| 80 | #define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 |
| 81 | #define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 |
| 82 | #define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT 7 |
| 83 | #define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 |
| 84 | #define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 |
| 85 | #define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT 6 |
| 86 | #define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT 8 |
| 87 | #define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT 8 |
| 88 | #define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT 11 |
| 89 | #define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT 10 |
| 90 | #define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT 8 |
| 91 | #define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT 9 |
| 92 | #define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 |
| 93 | #define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 |
| 94 | #define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 |
| 95 | #define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 |
| 96 | #define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 |
| 97 | #define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 |
| 98 | #define OMAP54XX_PAD_CLKS_GATE_SHIFT 8 |
| 99 | #define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT 10 |
| 100 | #define OMAP54XX_ST_DPLL_CLK_MASK (1 << 0) |
| 101 | #define OMAP54XX_SYS_CLKSEL_SHIFT 0 |
| 102 | #define OMAP54XX_SYS_CLKSEL_WIDTH 0x3 |
| 103 | #define OMAP54XX_WKUPAON_STATDEP_SHIFT 15 |
| 104 | #endif |