| rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (C) 2016 MediaTek Inc. |
| 3 | * |
| 4 | * This program is free software: you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | #include <linux/linkage.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <asm/assembler.h> |
| 16 | #include <asm/errno.h> |
| 17 | #include <asm/unwind.h> |
| 18 | |
| 19 | #include "proc-macros.S" |
| 20 | |
| 21 | /* |
| 22 | * __xxxx_dcache_user_area(start,size) |
| 23 | * |
| 24 | * Ensure that any D-cache lines for the interval [start, start+size) |
| 25 | * are cleaned or/and invalidated to the PoC. |
| 26 | * |
| 27 | * - start - virtual start address of region (EL0/EL1) |
| 28 | * - size - size in question |
| 29 | */ |
| 30 | |
| 31 | ENTRY(__clean_dcache_user_area) |
| 32 | uaccess_enable r2 |
| 33 | add r1, r1, r0 |
| 34 | dcache_line_size r2, r3 |
| 35 | sub r3, r2, #1 |
| 36 | bic r0, r0, r3 |
| 37 | #ifdef CONFIG_ARM_ERRATA_764369 |
| 38 | ALT_SMP(W(dsb)) |
| 39 | ALT_UP(W(nop)) |
| 40 | #endif |
| 41 | 1: |
| 42 | #if defined(CONFIG_ARM_ERRATA_855873) || defined(CONFIG_ARM_ERRATA_824069) |
| 43 | mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D / U line |
| 44 | #else |
| 45 | mcr p15, 0, r0, c7, c10, 1 @ clean D / U line |
| 46 | #endif |
| 47 | add r0, r0, r2 |
| 48 | cmp r0, r1 |
| 49 | blo 1b |
| 50 | dsb st |
| 51 | uaccess_disable r2 |
| 52 | ret lr |
| 53 | ENDPROC(__clean_dcache_user_area) |
| 54 | |
| 55 | ENTRY(__clean_dcache_area_poc) |
| 56 | add r1, r1, r0 |
| 57 | b v7_dma_clean_range |
| 58 | ENDPROC(__clean_dcache_area_poc) |
| 59 | |
| 60 | ENTRY(__flush_dcache_user_area) |
| 61 | uaccess_enable r2 |
| 62 | add r1, r1, r0 |
| 63 | dcache_line_size r2, r3 |
| 64 | sub r3, r2, #1 |
| 65 | bic r0, r0, r3 |
| 66 | #ifdef CONFIG_ARM_ERRATA_764369 |
| 67 | ALT_SMP(W(dsb)) |
| 68 | ALT_UP(W(nop)) |
| 69 | #endif |
| 70 | 1: |
| 71 | mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line |
| 72 | add r0, r0, r2 |
| 73 | cmp r0, r1 |
| 74 | blo 1b |
| 75 | dsb st |
| 76 | uaccess_disable r2 |
| 77 | ret lr |
| 78 | ENDPROC(__flush_dcache_user_area) |
| 79 | |
| 80 | ENTRY(__flush_dcache_area) |
| 81 | add r1, r1, r0 |
| 82 | b v7_dma_flush_range |
| 83 | ENDPROC(__flush_dcache_area) |
| 84 | |
| 85 | ENTRY(__inval_dcache_user_area) |
| 86 | b __flush_dcache_user_area |
| 87 | ENDPROC(__inval_dcache_user_area) |
| 88 | |
| 89 | ENTRY(__inval_dcache_area) |
| 90 | add r1, r1, r0 |
| 91 | b v7_dma_inv_range |
| 92 | ENDPROC(__inval_dcache_area) |
| 93 | |