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rjw1f884582022-01-06 17:20:42 +08001/*
2 * Based on arch/arm/mm/proc.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Copyright (C) 2012 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <linux/init.h>
22#include <linux/linkage.h>
23#include <asm/assembler.h>
24#include <asm/asm-offsets.h>
25#include <asm/hwcap.h>
26#include <asm/pgtable.h>
27#include <asm/pgtable-hwdef.h>
28#include <asm/cpufeature.h>
29#include <asm/alternative.h>
30
31#ifdef CONFIG_ARM64_64K_PAGES
32#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K
33#elif defined(CONFIG_ARM64_16K_PAGES)
34#define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K
35#else /* CONFIG_ARM64_4K_PAGES */
36#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K
37#endif
38
39#define TCR_SMP_FLAGS TCR_SHARED
40
41/* PTWs cacheable, inner/outer WBWA */
42#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
43
44#define MAIR(attr, mt) ((attr) << ((mt) * 8))
45
46/*
47 * cpu_do_idle()
48 *
49 * Idle the processor (wait for interrupt).
50 */
51ENTRY(cpu_do_idle)
52 dsb sy // WFI may enter a low-power mode
53 wfi
54 ret
55ENDPROC(cpu_do_idle)
56
57#ifdef CONFIG_CPU_PM
58/**
59 * cpu_do_suspend - save CPU registers context
60 *
61 * x0: virtual address of context pointer
62 */
63ENTRY(cpu_do_suspend)
64 mrs x2, tpidr_el0
65 mrs x3, tpidrro_el0
66 mrs x4, contextidr_el1
67 mrs x5, osdlr_el1
68 mrs x6, cpacr_el1
69 mrs x7, tcr_el1
70 mrs x8, vbar_el1
71 mrs x9, mdscr_el1
72 mrs x10, oslsr_el1
73 mrs x11, sctlr_el1
74alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
75 mrs x12, tpidr_el1
76alternative_else
77 mrs x12, tpidr_el2
78alternative_endif
79 mrs x13, sp_el0
80 stp x2, x3, [x0]
81 stp x4, x5, [x0, #16]
82 stp x6, x7, [x0, #32]
83 stp x8, x9, [x0, #48]
84 stp x10, x11, [x0, #64]
85 stp x12, x13, [x0, #80]
86 ret
87ENDPROC(cpu_do_suspend)
88
89/**
90 * cpu_do_resume - restore CPU register context
91 *
92 * x0: Address of context pointer
93 */
94 .pushsection ".idmap.text", "awx"
95ENTRY(cpu_do_resume)
96 ldp x2, x3, [x0]
97 ldp x4, x5, [x0, #16]
98 ldp x6, x8, [x0, #32]
99 ldp x9, x10, [x0, #48]
100 ldp x11, x12, [x0, #64]
101 ldp x13, x14, [x0, #80]
102 msr tpidr_el0, x2
103 msr tpidrro_el0, x3
104 msr contextidr_el1, x4
105 msr cpacr_el1, x6
106
107 /* Don't change t0sz here, mask those bits when restoring */
108 mrs x7, tcr_el1
109 bfi x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
110
111 msr tcr_el1, x8
112 msr vbar_el1, x9
113
114 /*
115 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
116 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
117 * exception. Mask them until local_dbg_restore() in cpu_suspend()
118 * resets them.
119 */
120 disable_dbg
121 msr mdscr_el1, x10
122
123 msr sctlr_el1, x12
124alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
125 msr tpidr_el1, x13
126alternative_else
127 msr tpidr_el2, x13
128alternative_endif
129 msr sp_el0, x14
130 /*
131 * Restore oslsr_el1 by writing oslar_el1
132 */
133 msr osdlr_el1, x5
134 ubfx x11, x11, #1, #1
135 msr oslar_el1, x11
136 reset_pmuserenr_el0 x0 // Disable PMU access from EL0
137 isb
138 ret
139ENDPROC(cpu_do_resume)
140 .popsection
141#endif
142
143/*
144 * cpu_do_switch_mm(pgd_phys, tsk)
145 *
146 * Set the translation table base pointer to be pgd_phys.
147 *
148 * - pgd_phys - physical address of new TTB
149 */
150ENTRY(cpu_do_switch_mm)
151 mrs x2, ttbr1_el1
152 mmid x1, x1 // get mm->context.id
153#ifdef CONFIG_ARM64_SW_TTBR0_PAN
154 bfi x0, x1, #48, #16 // set the ASID field in TTBR0
155#endif
156 bfi x2, x1, #48, #16 // set the ASID
157 msr ttbr1_el1, x2 // in TTBR1 (since TCR.A1 is set)
158 isb
159 msr ttbr0_el1, x0 // now update TTBR0
160 isb
161 b post_ttbr_update_workaround // Back to C code...
162ENDPROC(cpu_do_switch_mm)
163
164 .pushsection ".idmap.text", "awx"
165
166.macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
167 adrp \tmp1, empty_zero_page
168 msr ttbr1_el1, \tmp1
169 isb
170 tlbi vmalle1
171 dsb nsh
172 isb
173.endm
174
175/*
176 * void idmap_cpu_replace_ttbr1(phys_addr_t new_pgd)
177 *
178 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
179 * called by anything else. It can only be executed from a TTBR0 mapping.
180 */
181ENTRY(idmap_cpu_replace_ttbr1)
182 mrs x2, daif
183 msr daifset, #0xf
184
185 __idmap_cpu_set_reserved_ttbr1 x1, x3
186
187 msr ttbr1_el1, x0
188 isb
189
190 msr daif, x2
191
192 ret
193ENDPROC(idmap_cpu_replace_ttbr1)
194 .popsection
195
196#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
197 .pushsection ".idmap.text", "awx"
198
199 .macro __idmap_kpti_get_pgtable_ent, type
200 dc cvac, cur_\()\type\()p // Ensure any existing dirty
201 dmb sy // lines are written back before
202 ldr \type, [cur_\()\type\()p] // loading the entry
203 tbz \type, #0, skip_\()\type // Skip invalid and
204 tbnz \type, #11, skip_\()\type // non-global entries
205 .endm
206
207 .macro __idmap_kpti_put_pgtable_ent_ng, type
208 orr \type, \type, #PTE_NG // Same bit for blocks and pages
209 str \type, [cur_\()\type\()p] // Update the entry and ensure
210 dmb sy // that it is visible to all
211 dc civac, cur_\()\type\()p // CPUs.
212 .endm
213
214/*
215 * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
216 *
217 * Called exactly once from stop_machine context by each CPU found during boot.
218 */
219__idmap_kpti_flag:
220 .long 1
221ENTRY(idmap_kpti_install_ng_mappings)
222 cpu .req w0
223 num_cpus .req w1
224 swapper_pa .req x2
225 swapper_ttb .req x3
226 flag_ptr .req x4
227 cur_pgdp .req x5
228 end_pgdp .req x6
229 pgd .req x7
230 cur_pudp .req x8
231 end_pudp .req x9
232 pud .req x10
233 cur_pmdp .req x11
234 end_pmdp .req x12
235 pmd .req x13
236 cur_ptep .req x14
237 end_ptep .req x15
238 pte .req x16
239
240 mrs swapper_ttb, ttbr1_el1
241 adr flag_ptr, __idmap_kpti_flag
242
243 cbnz cpu, __idmap_kpti_secondary
244
245 /* We're the boot CPU. Wait for the others to catch up */
246 sevl
2471: wfe
248 ldaxr w18, [flag_ptr]
249 eor w18, w18, num_cpus
250 cbnz w18, 1b
251
252 /* We need to walk swapper, so turn off the MMU. */
253 mrs x18, sctlr_el1
254 bic x18, x18, #SCTLR_ELx_M
255 msr sctlr_el1, x18
256 isb
257
258 /* Everybody is enjoying the idmap, so we can rewrite swapper. */
259 /* PGD */
260 mov cur_pgdp, swapper_pa
261 add end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
262do_pgd: __idmap_kpti_get_pgtable_ent pgd
263 tbnz pgd, #1, walk_puds
264next_pgd:
265 __idmap_kpti_put_pgtable_ent_ng pgd
266skip_pgd:
267 add cur_pgdp, cur_pgdp, #8
268 cmp cur_pgdp, end_pgdp
269 b.ne do_pgd
270
271 /* Publish the updated tables and nuke all the TLBs */
272 dsb sy
273 tlbi vmalle1is
274 dsb ish
275 isb
276
277 /* We're done: fire up the MMU again */
278 mrs x18, sctlr_el1
279 orr x18, x18, #SCTLR_ELx_M
280 msr sctlr_el1, x18
281 isb
282
283 /*
284 * Invalidate the local I-cache so that any instructions fetched
285 * speculatively from the PoC are discarded, since they may have
286 * been dynamically patched at the PoU.
287 */
288 ic iallu
289 dsb nsh
290 isb
291
292 /* Set the flag to zero to indicate that we're all done */
293 str wzr, [flag_ptr]
294 ret
295
296 /* PUD */
297walk_puds:
298 .if CONFIG_PGTABLE_LEVELS > 3
299 pte_to_phys cur_pudp, pgd
300 add end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
301do_pud: __idmap_kpti_get_pgtable_ent pud
302 tbnz pud, #1, walk_pmds
303next_pud:
304 __idmap_kpti_put_pgtable_ent_ng pud
305skip_pud:
306 add cur_pudp, cur_pudp, 8
307 cmp cur_pudp, end_pudp
308 b.ne do_pud
309 b next_pgd
310 .else /* CONFIG_PGTABLE_LEVELS <= 3 */
311 mov pud, pgd
312 b walk_pmds
313next_pud:
314 b next_pgd
315 .endif
316
317 /* PMD */
318walk_pmds:
319 .if CONFIG_PGTABLE_LEVELS > 2
320 pte_to_phys cur_pmdp, pud
321 add end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
322do_pmd: __idmap_kpti_get_pgtable_ent pmd
323 tbnz pmd, #1, walk_ptes
324next_pmd:
325 __idmap_kpti_put_pgtable_ent_ng pmd
326skip_pmd:
327 add cur_pmdp, cur_pmdp, #8
328 cmp cur_pmdp, end_pmdp
329 b.ne do_pmd
330 b next_pud
331 .else /* CONFIG_PGTABLE_LEVELS <= 2 */
332 mov pmd, pud
333 b walk_ptes
334next_pmd:
335 b next_pud
336 .endif
337
338 /* PTE */
339walk_ptes:
340 pte_to_phys cur_ptep, pmd
341 add end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
342do_pte: __idmap_kpti_get_pgtable_ent pte
343 __idmap_kpti_put_pgtable_ent_ng pte
344skip_pte:
345 add cur_ptep, cur_ptep, #8
346 cmp cur_ptep, end_ptep
347 b.ne do_pte
348 b next_pmd
349
350 /* Secondary CPUs end up here */
351__idmap_kpti_secondary:
352 /* Uninstall swapper before surgery begins */
353 __idmap_cpu_set_reserved_ttbr1 x18, x17
354
355 /* Increment the flag to let the boot CPU we're ready */
3561: ldxr w18, [flag_ptr]
357 add w18, w18, #1
358 stxr w17, w18, [flag_ptr]
359 cbnz w17, 1b
360
361 /* Wait for the boot CPU to finish messing around with swapper */
362 sevl
3631: wfe
364 ldxr w18, [flag_ptr]
365 cbnz w18, 1b
366
367 /* All done, act like nothing happened */
368 msr ttbr1_el1, swapper_ttb
369 isb
370 ret
371
372 .unreq cpu
373 .unreq num_cpus
374 .unreq swapper_pa
375 .unreq swapper_ttb
376 .unreq flag_ptr
377 .unreq cur_pgdp
378 .unreq end_pgdp
379 .unreq pgd
380 .unreq cur_pudp
381 .unreq end_pudp
382 .unreq pud
383 .unreq cur_pmdp
384 .unreq end_pmdp
385 .unreq pmd
386 .unreq cur_ptep
387 .unreq end_ptep
388 .unreq pte
389ENDPROC(idmap_kpti_install_ng_mappings)
390 .popsection
391#endif
392
393/*
394 * __cpu_setup
395 *
396 * Initialise the processor for turning the MMU on. Return in x0 the
397 * value of the SCTLR_EL1 register.
398 */
399 .pushsection ".idmap.text", "awx"
400ENTRY(__cpu_setup)
401 tlbi vmalle1 // Invalidate local TLB
402 dsb nsh
403
404 mov x0, #3 << 20
405 msr cpacr_el1, x0 // Enable FP/ASIMD
406 mov x0, #1 << 12 // Reset mdscr_el1 and disable
407 msr mdscr_el1, x0 // access to the DCC from EL0
408 isb // Unmask debug exceptions now,
409 enable_dbg // since this is per-cpu
410 reset_pmuserenr_el0 x0 // Disable PMU access from EL0
411 /*
412 * Memory region attributes for LPAE:
413 *
414 * n = AttrIndx[2:0]
415 * n MAIR
416 * DEVICE_nGnRnE 000 00000000
417 * DEVICE_nGnRE 001 00000100
418 * DEVICE_GRE 010 00001100
419 * NORMAL_NC 011 01000100
420 * NORMAL 100 11111111
421 * NORMAL_WT 101 10111011
422 */
423 ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
424 MAIR(0x04, MT_DEVICE_nGnRE) | \
425 MAIR(0x0c, MT_DEVICE_GRE) | \
426 MAIR(0x44, MT_NORMAL_NC) | \
427 MAIR(0xff, MT_NORMAL) | \
428 MAIR(0xbb, MT_NORMAL_WT)
429 msr mair_el1, x5
430 /*
431 * Prepare SCTLR
432 */
433 mov_q x0, SCTLR_EL1_SET
434 /*
435 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
436 * both user and kernel.
437 */
438 ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
439 TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 | TCR_A1
440 tcr_set_idmap_t0sz x10, x9
441
442 /*
443 * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in
444 * TCR_EL1.
445 */
446 mrs x9, ID_AA64MMFR0_EL1
447 bfi x10, x9, #32, #3
448#ifdef CONFIG_ARM64_HW_AFDBM
449 /*
450 * Hardware update of the Access and Dirty bits.
451 */
452 mrs x9, ID_AA64MMFR1_EL1
453 and x9, x9, #0xf
454 cbz x9, 2f
455 cmp x9, #2
456 b.lt 1f
457#ifdef CONFIG_ARM64_ERRATUM_1024718
458 /* Disable hardware DBM on Cortex-A55 r0p0, r0p1 & r1p0 */
459 cpu_midr_match MIDR_CORTEX_A55, MIDR_CPU_VAR_REV(0, 0), MIDR_CPU_VAR_REV(1, 0), x1, x2, x3, x4
460 cbnz x1, 1f
461#endif
462 orr x10, x10, #TCR_HD // hardware Dirty flag update
4631: orr x10, x10, #TCR_HA // hardware Access flag update
4642:
465#endif /* CONFIG_ARM64_HW_AFDBM */
466 msr tcr_el1, x10
467 ret // return to head.S
468ENDPROC(__cpu_setup)