| rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame^] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | menu "Processor features" |
| 3 | |
| 4 | choice |
| 5 | prompt "Endianness selection" |
| 6 | default CPU_LITTLE_ENDIAN |
| 7 | help |
| 8 | Some SuperH machines can be configured for either little or big |
| 9 | endian byte order. These modes require different kernels. |
| 10 | |
| 11 | config CPU_LITTLE_ENDIAN |
| 12 | bool "Little Endian" |
| 13 | |
| 14 | config CPU_BIG_ENDIAN |
| 15 | bool "Big Endian" |
| 16 | depends on !CPU_SH5 |
| 17 | |
| 18 | endchoice |
| 19 | |
| 20 | config SH_FPU |
| 21 | def_bool y |
| 22 | prompt "FPU support" |
| 23 | depends on CPU_HAS_FPU |
| 24 | help |
| 25 | Selecting this option will enable support for SH processors that |
| 26 | have FPU units (ie, SH77xx). |
| 27 | |
| 28 | This option must be set in order to enable the FPU. |
| 29 | |
| 30 | config SH64_FPU_DENORM_FLUSH |
| 31 | bool "Flush floating point denorms to zero" |
| 32 | depends on SH_FPU && SUPERH64 |
| 33 | |
| 34 | config SH_FPU_EMU |
| 35 | def_bool n |
| 36 | prompt "FPU emulation support" |
| 37 | depends on !SH_FPU |
| 38 | help |
| 39 | Selecting this option will enable support for software FPU emulation. |
| 40 | Most SH-3 users will want to say Y here, whereas most SH-4 users will |
| 41 | want to say N. |
| 42 | |
| 43 | config SH_DSP |
| 44 | def_bool y |
| 45 | prompt "DSP support" |
| 46 | depends on CPU_HAS_DSP |
| 47 | help |
| 48 | Selecting this option will enable support for SH processors that |
| 49 | have DSP units (ie, SH2-DSP, SH3-DSP, and SH4AL-DSP). |
| 50 | |
| 51 | This option must be set in order to enable the DSP. |
| 52 | |
| 53 | config SH_ADC |
| 54 | def_bool y |
| 55 | prompt "ADC support" |
| 56 | depends on CPU_SH3 |
| 57 | help |
| 58 | Selecting this option will allow the Linux kernel to use SH3 on-chip |
| 59 | ADC module. |
| 60 | |
| 61 | If unsure, say N. |
| 62 | |
| 63 | config SH_STORE_QUEUES |
| 64 | bool "Support for Store Queues" |
| 65 | depends on CPU_SH4 |
| 66 | help |
| 67 | Selecting this option will enable an in-kernel API for manipulating |
| 68 | the store queues integrated in the SH-4 processors. |
| 69 | |
| 70 | config SPECULATIVE_EXECUTION |
| 71 | bool "Speculative subroutine return" |
| 72 | depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 || CPU_SUBTYPE_SH7786 |
| 73 | help |
| 74 | This enables support for a speculative instruction fetch for |
| 75 | subroutine return. There are various pitfalls associated with |
| 76 | this, as outlined in the SH7780 hardware manual. |
| 77 | |
| 78 | If unsure, say N. |
| 79 | |
| 80 | config SH64_ID2815_WORKAROUND |
| 81 | bool "Include workaround for SH5-101 cut2 silicon defect ID2815" |
| 82 | depends on CPU_SUBTYPE_SH5_101 |
| 83 | |
| 84 | config CPU_HAS_INTEVT |
| 85 | bool |
| 86 | |
| 87 | config CPU_HAS_IPR_IRQ |
| 88 | bool |
| 89 | |
| 90 | config CPU_HAS_SR_RB |
| 91 | bool |
| 92 | help |
| 93 | This will enable the use of SR.RB register bank usage. Processors |
| 94 | that are lacking this bit must have another method in place for |
| 95 | accomplishing what is taken care of by the banked registers. |
| 96 | |
| 97 | See <file:Documentation/sh/register-banks.txt> for further |
| 98 | information on SR.RB and register banking in the kernel in general. |
| 99 | |
| 100 | config CPU_HAS_PTEAEX |
| 101 | bool |
| 102 | |
| 103 | config CPU_HAS_DSP |
| 104 | bool |
| 105 | |
| 106 | config CPU_HAS_FPU |
| 107 | bool |
| 108 | |
| 109 | endmenu |