blob: d7186a503e3584282a7001e8e40a65d7765ff02d [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +08001/*
2 * Generic PXA PATA driver
3 *
4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; see the file COPYING. If not, write to
18 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/blkdev.h>
24#include <linux/ata.h>
25#include <linux/libata.h>
26#include <linux/platform_device.h>
27#include <linux/dmaengine.h>
28#include <linux/dma/pxa-dma.h>
29#include <linux/gpio.h>
30#include <linux/slab.h>
31#include <linux/completion.h>
32
33#include <scsi/scsi_host.h>
34
35#include <linux/platform_data/ata-pxa.h>
36
37#define DRV_NAME "pata_pxa"
38#define DRV_VERSION "0.1"
39
40struct pata_pxa_data {
41 struct dma_chan *dma_chan;
42 dma_cookie_t dma_cookie;
43 struct completion dma_done;
44};
45
46/*
47 * DMA interrupt handler.
48 */
49static void pxa_ata_dma_irq(void *d)
50{
51 struct pata_pxa_data *pd = d;
52 enum dma_status status;
53
54 status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, NULL);
55 if (status == DMA_ERROR || status == DMA_COMPLETE)
56 complete(&pd->dma_done);
57}
58
59/*
60 * Prepare taskfile for submission.
61 */
62static enum ata_completion_errors pxa_qc_prep(struct ata_queued_cmd *qc)
63{
64 struct pata_pxa_data *pd = qc->ap->private_data;
65 struct dma_async_tx_descriptor *tx;
66 enum dma_transfer_direction dir;
67
68 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
69 return AC_ERR_OK;
70
71 dir = (qc->dma_dir == DMA_TO_DEVICE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM);
72 tx = dmaengine_prep_slave_sg(pd->dma_chan, qc->sg, qc->n_elem, dir,
73 DMA_PREP_INTERRUPT);
74 if (!tx) {
75 ata_dev_err(qc->dev, "prep_slave_sg() failed\n");
76 return AC_ERR_OK;
77 }
78 tx->callback = pxa_ata_dma_irq;
79 tx->callback_param = pd;
80 pd->dma_cookie = dmaengine_submit(tx);
81
82 return AC_ERR_OK;
83}
84
85/*
86 * Configure the DMA controller, load the DMA descriptors, but don't start the
87 * DMA controller yet. Only issue the ATA command.
88 */
89static void pxa_bmdma_setup(struct ata_queued_cmd *qc)
90{
91 qc->ap->ops->sff_exec_command(qc->ap, &qc->tf);
92}
93
94/*
95 * Execute the DMA transfer.
96 */
97static void pxa_bmdma_start(struct ata_queued_cmd *qc)
98{
99 struct pata_pxa_data *pd = qc->ap->private_data;
100 init_completion(&pd->dma_done);
101 dma_async_issue_pending(pd->dma_chan);
102}
103
104/*
105 * Wait until the DMA transfer completes, then stop the DMA controller.
106 */
107static void pxa_bmdma_stop(struct ata_queued_cmd *qc)
108{
109 struct pata_pxa_data *pd = qc->ap->private_data;
110 enum dma_status status;
111
112 status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, NULL);
113 if (status != DMA_ERROR && status != DMA_COMPLETE &&
114 wait_for_completion_timeout(&pd->dma_done, HZ))
115 ata_dev_err(qc->dev, "Timeout waiting for DMA completion!");
116
117 dmaengine_terminate_all(pd->dma_chan);
118}
119
120/*
121 * Read DMA status. The bmdma_stop() will take care of properly finishing the
122 * DMA transfer so we always have DMA-complete interrupt here.
123 */
124static unsigned char pxa_bmdma_status(struct ata_port *ap)
125{
126 struct pata_pxa_data *pd = ap->private_data;
127 unsigned char ret = ATA_DMA_INTR;
128 struct dma_tx_state state;
129 enum dma_status status;
130
131 status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, &state);
132 if (status != DMA_COMPLETE)
133 ret |= ATA_DMA_ERR;
134
135 return ret;
136}
137
138/*
139 * No IRQ register present so we do nothing.
140 */
141static void pxa_irq_clear(struct ata_port *ap)
142{
143}
144
145/*
146 * Check for ATAPI DMA. ATAPI DMA is unsupported by this driver. It's still
147 * unclear why ATAPI has DMA issues.
148 */
149static int pxa_check_atapi_dma(struct ata_queued_cmd *qc)
150{
151 return -EOPNOTSUPP;
152}
153
154static struct scsi_host_template pxa_ata_sht = {
155 ATA_BMDMA_SHT(DRV_NAME),
156};
157
158static struct ata_port_operations pxa_ata_port_ops = {
159 .inherits = &ata_bmdma_port_ops,
160 .cable_detect = ata_cable_40wire,
161
162 .bmdma_setup = pxa_bmdma_setup,
163 .bmdma_start = pxa_bmdma_start,
164 .bmdma_stop = pxa_bmdma_stop,
165 .bmdma_status = pxa_bmdma_status,
166
167 .check_atapi_dma = pxa_check_atapi_dma,
168
169 .sff_irq_clear = pxa_irq_clear,
170
171 .qc_prep = pxa_qc_prep,
172};
173
174static int pxa_ata_probe(struct platform_device *pdev)
175{
176 struct ata_host *host;
177 struct ata_port *ap;
178 struct pata_pxa_data *data;
179 struct resource *cmd_res;
180 struct resource *ctl_res;
181 struct resource *dma_res;
182 struct resource *irq_res;
183 struct pata_pxa_pdata *pdata = dev_get_platdata(&pdev->dev);
184 struct dma_slave_config config;
185 dma_cap_mask_t mask;
186 struct pxad_param param;
187 int ret = 0;
188
189 /*
190 * Resource validation, three resources are needed:
191 * - CMD port base address
192 * - CTL port base address
193 * - DMA port base address
194 * - IRQ pin
195 */
196 if (pdev->num_resources != 4) {
197 dev_err(&pdev->dev, "invalid number of resources\n");
198 return -EINVAL;
199 }
200
201 /*
202 * CMD port base address
203 */
204 cmd_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
205 if (unlikely(cmd_res == NULL))
206 return -EINVAL;
207
208 /*
209 * CTL port base address
210 */
211 ctl_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
212 if (unlikely(ctl_res == NULL))
213 return -EINVAL;
214
215 /*
216 * DMA port base address
217 */
218 dma_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
219 if (unlikely(dma_res == NULL))
220 return -EINVAL;
221
222 /*
223 * IRQ pin
224 */
225 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
226 if (unlikely(irq_res == NULL))
227 return -EINVAL;
228
229 /*
230 * Allocate the host
231 */
232 host = ata_host_alloc(&pdev->dev, 1);
233 if (!host)
234 return -ENOMEM;
235
236 ap = host->ports[0];
237 ap->ops = &pxa_ata_port_ops;
238 ap->pio_mask = ATA_PIO4;
239 ap->mwdma_mask = ATA_MWDMA2;
240
241 ap->ioaddr.cmd_addr = devm_ioremap(&pdev->dev, cmd_res->start,
242 resource_size(cmd_res));
243 ap->ioaddr.ctl_addr = devm_ioremap(&pdev->dev, ctl_res->start,
244 resource_size(ctl_res));
245 ap->ioaddr.bmdma_addr = devm_ioremap(&pdev->dev, dma_res->start,
246 resource_size(dma_res));
247
248 /*
249 * Adjust register offsets
250 */
251 ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
252 ap->ioaddr.data_addr = ap->ioaddr.cmd_addr +
253 (ATA_REG_DATA << pdata->reg_shift);
254 ap->ioaddr.error_addr = ap->ioaddr.cmd_addr +
255 (ATA_REG_ERR << pdata->reg_shift);
256 ap->ioaddr.feature_addr = ap->ioaddr.cmd_addr +
257 (ATA_REG_FEATURE << pdata->reg_shift);
258 ap->ioaddr.nsect_addr = ap->ioaddr.cmd_addr +
259 (ATA_REG_NSECT << pdata->reg_shift);
260 ap->ioaddr.lbal_addr = ap->ioaddr.cmd_addr +
261 (ATA_REG_LBAL << pdata->reg_shift);
262 ap->ioaddr.lbam_addr = ap->ioaddr.cmd_addr +
263 (ATA_REG_LBAM << pdata->reg_shift);
264 ap->ioaddr.lbah_addr = ap->ioaddr.cmd_addr +
265 (ATA_REG_LBAH << pdata->reg_shift);
266 ap->ioaddr.device_addr = ap->ioaddr.cmd_addr +
267 (ATA_REG_DEVICE << pdata->reg_shift);
268 ap->ioaddr.status_addr = ap->ioaddr.cmd_addr +
269 (ATA_REG_STATUS << pdata->reg_shift);
270 ap->ioaddr.command_addr = ap->ioaddr.cmd_addr +
271 (ATA_REG_CMD << pdata->reg_shift);
272
273 /*
274 * Allocate and load driver's internal data structure
275 */
276 data = devm_kzalloc(&pdev->dev, sizeof(struct pata_pxa_data),
277 GFP_KERNEL);
278 if (!data)
279 return -ENOMEM;
280
281 ap->private_data = data;
282
283 dma_cap_zero(mask);
284 dma_cap_set(DMA_SLAVE, mask);
285 param.prio = PXAD_PRIO_LOWEST;
286 param.drcmr = pdata->dma_dreq;
287 memset(&config, 0, sizeof(config));
288 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
289 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
290 config.src_addr = dma_res->start;
291 config.dst_addr = dma_res->start;
292 config.src_maxburst = 32;
293 config.dst_maxburst = 32;
294
295 /*
296 * Request the DMA channel
297 */
298 data->dma_chan =
299 dma_request_slave_channel_compat(mask, pxad_filter_fn,
300 &param, &pdev->dev, "data");
301 if (!data->dma_chan)
302 return -EBUSY;
303 ret = dmaengine_slave_config(data->dma_chan, &config);
304 if (ret < 0) {
305 dev_err(&pdev->dev, "dma configuration failed: %d\n", ret);
306 return ret;
307 }
308
309 /*
310 * Activate the ATA host
311 */
312 ret = ata_host_activate(host, irq_res->start, ata_sff_interrupt,
313 pdata->irq_flags, &pxa_ata_sht);
314 if (ret)
315 dma_release_channel(data->dma_chan);
316
317 return ret;
318}
319
320static int pxa_ata_remove(struct platform_device *pdev)
321{
322 struct ata_host *host = platform_get_drvdata(pdev);
323 struct pata_pxa_data *data = host->ports[0]->private_data;
324
325 dma_release_channel(data->dma_chan);
326
327 ata_host_detach(host);
328
329 return 0;
330}
331
332static struct platform_driver pxa_ata_driver = {
333 .probe = pxa_ata_probe,
334 .remove = pxa_ata_remove,
335 .driver = {
336 .name = DRV_NAME,
337 },
338};
339
340module_platform_driver(pxa_ata_driver);
341
342MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
343MODULE_DESCRIPTION("DMA-capable driver for PATA on PXA CPU");
344MODULE_LICENSE("GPL");
345MODULE_VERSION(DRV_VERSION);
346MODULE_ALIAS("platform:" DRV_NAME);