src/kernel/linux/v4.14/drivers/clk/mediatek/clk-mt2731.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2019 MediaTek Inc.
 * Author: Yong Wu <yong.wu@mediatek.com>
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include "clk-mtk.h"
#include "clk-mux.h"
#include "clk-gate.h"

#include <dt-bindings/clock/mt2731-clk.h>

#define CLK_CFG_UPDATE 0x004

static DEFINE_SPINLOCK(mt2731_clk_lock);

static const struct mtk_fixed_clk top_fixed_clks[] = {
	/* FIXED_CLK(CLK_TOP_CLK26M, "clk26m", NULL, 26000000), */
	FIXED_CLK(CLK_TOP_USB20_192M, "usb20_192m_ck", "univpll", 192000000),
};

static const struct mtk_fixed_factor top_divs[] = {
	FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
	FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
	FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
	FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
	FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
	FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
	FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
	FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
	FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
	FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
	FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
	FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
	FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
	FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
	FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
	FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
	/* FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", "None", 1, 1), */
	FACTOR(CLK_TOP_USB20_192M_D2, "usb20_192m_d2", "usb20_192m_ck", 1, 2),
	FACTOR(CLK_TOP_USB20_192M_D4, "usb20_192m_d4", "usb20_192m_ck", 1, 4),
	FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
	FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
	FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
	FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
	FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
	FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2),
	FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),
	FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8),
	FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll_d3", 1, 16),
	FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
	FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
	FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
	FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
	FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
	FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
	FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
	FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4),
	FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 8),
	FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
	FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2),
	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, 4),
	FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1, 8),
	FACTOR(CLK_TOP_ETHERPLL, "etherpll_ck", "etherpll", 1, 1),
	FACTOR(CLK_TOP_ETHERPLL_D4, "etherpll_d4", "etherpll_ck", 1, 4),
	FACTOR(CLK_TOP_ETHERPLL_D10, "etherpll_d10", "etherpll", 1, 10),
	FACTOR(CLK_TOP_HD_FAXI, "hd_faxi_ck", "axi_sel", 1, 1),
	FACTOR(CLK_TOP_F_FUART, "f_fuart_ck", "uart_sel", 1, 1),
	FACTOR(CLK_TOP_SPI, "spi_ck", "spi_sel", 1, 1),
	FACTOR(CLK_TOP_MSDC50_0, "msdc50_0_ck", "msdc50_0_sel", 1, 1),
	FACTOR(CLK_TOP_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 1, 1),
	FACTOR(CLK_TOP_AUDIO, "audio_ck", "audio_sel", 1, 1),
	FACTOR(CLK_TOP_AUD_1, "aud_1_ck", "aud_1_sel", 1, 1),
	FACTOR(CLK_TOP_AUD_ENGEN1, "aud_engen1_ck", "aud_engen1_sel", 1, 1),
	FACTOR(CLK_TOP_AUD_ENGEN2, "aud_engen2_ck", "aud_engen2_sel", 1, 1),
	FACTOR(CLK_TOP_HSM_CRYPTO, "hsm_crypto_ck", "hsm_crypto_sel", 1, 1),
	FACTOR(CLK_TOP_I2C, "i2c_ck", "i2c_sel", 1, 1),
	FACTOR(CLK_TOP_MSDC50_2_HCLK,
	       "msdc5_2hclk_ck", "msdc5_2hclk_sel", 1, 1),
	FACTOR(CLK_TOP_MSDC30_2, "msdc30_2_ck", "msdc30_2_sel", 1, 1),
	FACTOR(CLK_TOP_NFI1X_BCLK, "nfi1x_bclk_ck", "nfi1x_bclk_sel", 1, 1),
	FACTOR(CLK_TOP_PCIE_MAC, "pcie_mac_ck", "pcie_mac_sel", 1, 1),
	FACTOR(CLK_TOP_F_FSSUSB_TOP, "f_fssusb_top_ck", "ssusb_top_sel", 1, 1),
	FACTOR(CLK_TOP_SPISLV, "spislv_ck", "spislv_sel", 1, 1),
	FACTOR(CLK_TOP_ETHER_125M, "ether_125m_ck", "ether_125m_sel", 1, 1),
	FACTOR(CLK_TOP_PWM, "pwm_ck", "pwm_sel", 1, 1),
	FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL1, "arm_div_pll1", "syspll_ck", 1, 1),
	FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL2, "arm_div_pll2", "univpll_d2", 1, 1),
};

static const char * const axi_parents[] = {
	"clk26m",
	"syspll2_d2",
	"syspll_d7",
	"syspll1_d4",
	"syspll3_d2"
};

static const char * const uart_parents[] = {
	"clk26m",
	"univpll2_d8"
};

static const char * const spi_parents[] = {
	"clk26m",
	"syspll3_d2",
	"syspll4_d2",
	"syspll2_d4"
};

static const char * const msdc5_0hclk_parents[] = {
	"clk26m",
	"syspll1_d2",
	"univpll1_d4",
	"syspll2_d2"
};

static const char * const msdc50_0_parents[] = {
	"clk26m",
	"msdcpll_ck",
	"syspll2_d2",
	"syspll4_d2",
	"univpll1_d2",
	"syspll1_d2",
	"univpll_d5",
	"univpll1_d4"
};

static const char * const msdc30_1_parents[] = {
	"clk26m",
	"msdcpll_d2",
	"univpll2_d2",
	"syspll2_d2",
	"syspll1_d4",
	"univpll1_d4",
	"usb20_192m_d4",
	"syspll2_d4"
};

static const char * const audio_parents[] = {
	"clk26m",
	"syspll3_d4",
	"syspll4_d4",
	"syspll1_d16"
};

static const char * const aud_intbus_parents[] = {
	"clk26m",
	"syspll1_d4",
	"syspll4_d2"
};

static const char * const aud_1_parents[] = {
	"clk26m",
	"apll1_ck"
};

static const char * const aud_2_parents[] = {
	"clk26m",
	"apll2_ck"
};

static const char * const aud_engen1_parents[] = {
	"clk26m",
	"apll1_d2",
	"apll1_d4",
	"apll1_d8"
};

static const char * const aud_engen2_parents[] = {
	"clk26m",
	"apll2_d2",
	"apll2_d4",
	"apll2_d8"
};

static const char * const dxcc_parents[] = {
	"clk26m",
	"syspll1_d2",
	"syspll1_d4",
	"syspll1_d8"
};

static const char * const hsm_crypto_parents[] = {
	"clk26m",
	"syspll2_d2",
	"syspll1_d2",
	"univpll1_d2"
};

static const char * const hsm_arc_parents[] = {
	"clk26m",
	"syspll1_d8",
	"syspll1_d4",
	"syspll2_d2"
};

static const char * const gcpu_parents[] = {
	"clk26m",
	"syspll1_d4",
	"syspll1_d2",
	"syspll_d3"
};

static const char * const ecc_parents[] = {
	"clk26m",
	"univpll2_d2",
	"univpll1_d2",
	"univpll_d3"
};

static const char * const usb_top_parents[] = {
	"clk26m",
	"univpll3_d4",
	"usb20_192m_d2"
};

static const char * const spm_parents[] = {
	"clk26m",
	"syspll1_d8"
};

static const char * const i2c_parents[] = {
	"clk26m",
	"univpll3_d4",
	"univpll3_d2",
	"syspll1_d8",
	"syspll2_d8"
};

static const char * const ulposc_parents[] = {
	"clk26m",
	"univpll2_d16"
};

static const char * const nfi1x_bclk_parents[] = {
	"clk26m",
	"univpll2_d8",
	"univpll1_d8",
	"syspll2_d4",
	"univpll2_d4",
	"syspll1_d4",
	"univpll1_d4",
	"syspll2_d2"
};

static const char * const spinfi_bclk_parents[] = {
	"clk26m",
	"univpll2_d8",
	"syspll1_d8",
	"univpll1_d8",
	"syspll2_d4",
	"univpll2_d4",
	"univpll3_d2",
	"syspll1_d4"
};

static const char * const pcie_mac_parents[] = {
	"clk26m",
	"syspll1_d8",
	"syspll3_d2",
	"syspll1_d4"
};

static const char * const ssusb_top_parents[] = {
	"clk26m",
	"univpll3_d4",
	"univpll3_d2"
};

static const char * const spislv_parents[] = {
	"clk26m",
	"univpll2_d4",
	"univpll3_d2",
	"univpll1_d4",
	"univpll2_d2",
	"univpll_d5",
	"univpll1_d2",
	"univpll_d3"
};

static const char * const ether_125m_parents[] = {
	"clk26m",
	"etherpll_d4"
};

static const char * const ether_50_parents[] = {
	"clk26m",
	"etherpll_d10"
};

static const char * const ether_62p4m_parents[] = {
	"clk26m",
	"univpll3_d4"
};

static const struct mtk_mux top_muxes[] = {
	/* CLK_CFG_0 */
	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
			0x40, 0x44, 0x48, 0, 3, 7, CLK_CFG_UPDATE, 0,
			CLK_IS_CRITICAL),
	MUX_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
			0x40, 0x44, 0x48, 8, 1, 15, CLK_CFG_UPDATE, 1),
	MUX_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
			0x40, 0x44, 0x48, 16, 2, 23, CLK_CFG_UPDATE, 2),
	MUX_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL,
			"msdc5_0hclk", msdc5_0hclk_parents,
			0x40, 0x44, 0x48, 24, 2, 31, CLK_CFG_UPDATE, 3),
	/* CLK_CFG_1 */
	MUX_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL,
			"msdc50_0_sel", msdc50_0_parents,
			0x050, 0x054, 0x58, 0, 3, 7, CLK_CFG_UPDATE, 4),
	MUX_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL,
			"msdc30_1_sel", msdc30_1_parents,
			0x050, 0x054, 0x58, 8, 3, 15, CLK_CFG_UPDATE, 5),
	MUX_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
			0x050, 0x054, 0x58, 16, 2, 23, CLK_CFG_UPDATE, 6),
	MUX_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL,
			"aud_intbus_sel", aud_intbus_parents,
			0x050, 0x054, 0x58, 24, 2, 31, CLK_CFG_UPDATE, 7),
	/* CLK_CFG_2 */
	MUX_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents,
			0x060, 0x064, 0x068, 0, 1, 7, CLK_CFG_UPDATE, 8),
	MUX_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents,
			0x060, 0x064, 0x068, 8, 1, 15, CLK_CFG_UPDATE, 9),
	MUX_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL,
			"aud_engen1_sel", aud_engen1_parents,
			0x060, 0x064, 0x068, 16, 2, 23, CLK_CFG_UPDATE, 10),
	MUX_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL,
			"aud_engen2_sel", aud_engen2_parents,
			0x060, 0x064, 0x068, 24, 2, 31, CLK_CFG_UPDATE, 11),
	/* CLK_CFG_3 */
	MUX_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents,
			0x070, 0x074, 0x078, 0, 2, 7, CLK_CFG_UPDATE, 12),
	/*
	MUX_CLR_SET_UPD(CLK_TOP_HSM_CRYPTO_SEL,
			"hsm_crypto_sel", hsm_crypto_parents,
			0x070, 0x074, 0x078, 8, 2, 15, CLK_CFG_UPDATE, 13),
	MUX_CLR_SET_UPD(CLK_TOP_HSM_ARC_SEL,
			"hsm_arc_sel", hsm_arc_parents,
			0x070, 0x074, 0x078, 16, 2, 23, CLK_CFG_UPDATE, 14),
	*/
	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents,
			0x070, 0x074, 0x078, 24, 2, 31, CLK_CFG_UPDATE, 15,
			CLK_IS_CRITICAL),
	/* CLK_CFG_4 */
	MUX_CLR_SET_UPD(CLK_TOP_ECC_SEL, "ecc_sel", ecc_parents,
			0x080, 0x084, 0x088, 0, 2, 7, CLK_CFG_UPDATE, 16),
	MUX_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL,
			"usb_top_sel", usb_top_parents,
			0x080, 0x084, 0x088, 8, 2, 15, CLK_CFG_UPDATE, 17),
	MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel", spm_parents,
			0x080, 0x084, 0x088, 16, 1, 23, CLK_CFG_UPDATE, 18,
			CLK_IS_CRITICAL),
	MUX_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
			0x080, 0x084, 0x088, 24, 3, 31, CLK_CFG_UPDATE, 19),
	/* CLK_CFG_5 */
	MUX_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC_SEL,
			"ulposc_sel", ulposc_parents,
			0x090, 0x094, 0x098, 0, 1, 7, CLK_CFG_UPDATE, 20),
	MUX_CLR_SET_UPD(CLK_TOP_MSDC50_2_HCLK_SEL,
			"msdc5_2hclk_sel", msdc5_0hclk_parents,
			0x090, 0x094, 0x098, 8, 2, 15, CLK_CFG_UPDATE, 21),
	MUX_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL,
			"msdc30_2_sel", msdc50_0_parents,
			0x090, 0x094, 0x098, 16, 3, 23, CLK_CFG_UPDATE, 22),
	MUX_CLR_SET_UPD(CLK_TOP_NFI1X_BCLK_SEL,
			"nfi1x_bclk_sel", nfi1x_bclk_parents,
			0x090, 0x094, 0x098, 24, 3, 31, CLK_CFG_UPDATE, 23),
	/* CLK_CFG_6 */
	MUX_CLR_SET_UPD(CLK_TOP_SPINFI_BCLK_SEL,
			"spinfi_bclk_sel", spinfi_bclk_parents,
			0x0a0, 0x0a4, 0x0a8, 0, 3, 7, CLK_CFG_UPDATE, 24),
	MUX_CLR_SET_UPD(CLK_TOP_PCIE_MAC_SEL,
			"pcie_mac_sel", pcie_mac_parents,
			0x0a0, 0x0a4, 0x0a8, 8, 2, 15, CLK_CFG_UPDATE, 25),
	MUX_CLR_SET_UPD(CLK_TOP_SSUSB_TOP_SEL,
			"ssusb_top_sel", ssusb_top_parents,
			0x0a0, 0x0a4, 0x0a8, 16, 2, 23, CLK_CFG_UPDATE, 26),
	MUX_CLR_SET_UPD(CLK_TOP_SPISLV_SEL,
			"spislv_sel", spislv_parents,
			0x0a0, 0x0a4, 0x0a8, 24, 3, 31, CLK_CFG_UPDATE, 27),
	/* CLK_CFG_7 */
	MUX_CLR_SET_UPD(CLK_TOP_ETHER_125M_SEL,
			"ether_125m_sel", ether_125m_parents,
			0x0b0, 0x0b4, 0x0b8, 0, 1, 7, CLK_CFG_UPDATE, 28),
	MUX_CLR_SET_UPD(CLK_TOP_ETHER_50M_RMII_SEL,
			"ether_50_sel", ether_50_parents,
			0x0b0, 0x0b4, 0x0b8, 8, 1, 15, CLK_CFG_UPDATE, 29),
	MUX_CLR_SET_UPD(CLK_TOP_ETHER_62P4M_SEL,
			"ether_62p4m_sel", ether_62p4m_parents,
			0x0b0, 0x0b4, 0x0b8, 16, 1, 23, CLK_CFG_UPDATE, 30),
	MUX_CLR_SET_UPD(CLK_TOP_PWM_SEL,
			"pwm_sel", ether_62p4m_parents,
			0x0b0, 0x0b4, 0x0b8, 24, 1, 31, CLK_CFG_UPDATE, 31),
};

static const char * const i2s0_m_ck_parents[] __initconst = {
	"aud_1_sel",
	"aud_2_sel"
};

static const char * const i2s1_m_ck_parents[] __initconst = {
	"aud_1_sel",
	"aud_2_sel"
};

static const char * const i2s2_m_ck_parents[] __initconst = {
	"aud_1_sel",
	"aud_2_sel"
};

static const char * const i2s3_m_ck_parents[] __initconst = {
	"aud_1_sel",
	"aud_2_sel"
};

static const char * const i2s4_m_ck_parents[] __initconst = {
	"aud_1_sel",
	"aud_2_sel"
};

static const struct mtk_composite top_audmuxes[] = {
	MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents,
		0x320, 8, 1),
	MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents,
		0x320, 9, 1),
	MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents,
		0x320, 10, 1),
	MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents,
		0x320, 11, 1),
	MUX(CLK_TOP_I2S4_M_SEL, "i2s4_m_ck_sel", i2s4_m_ck_parents,
		0x320, 12, 1),

	DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "i2s0_m_ck_sel",
		0x320, 2, 0x324, 8, 0),
	DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "i2s1_m_ck_sel",
		0x320, 3, 0x324, 8, 8),
	DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "i2s2_m_ck_sel",
		0x320, 4, 0x324, 8, 16),
	DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "i2s3_m_ck_sel",
		0x320, 5, 0x324, 8, 24),
	DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "i2s4_m_ck_sel",
		0x320, 6, 0x328, 8, 0),
	DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4",
		0x320, 7, 0x328, 8, 8),
};

static const struct mtk_gate_regs top0_cg_regs = {
	.set_ofs = 0x104,
	.clr_ofs = 0x104,
	.sta_ofs = 0x104,
};

#define GATE_TOP0(_id, _name, _parent, _shift) {	\
		.id = _id,				\
		.name = _name,				\
		.parent_name = _parent,			\
		.regs = &top0_cg_regs,			\
		.shift = _shift,			\
		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\
	}

static const struct mtk_gate top_clks[] = {
	/* TOP0 */
	GATE_TOP0(CLK_TOP_ARMPLL_DIVIDER_PLL1_EN,
		  "arm_div_pll1_en", "arm_div_pll1", 4),
	GATE_TOP0(CLK_TOP_ARMPLL_DIVIDER_PLL2_EN,
		  "arm_div_pll2_en", "arm_div_pll2", 5),
	/* TOP1 */
	/*
	 *GATE_TOP1(CLK_TOP_APLL12_DIV0, "apll12_div0", "aud_1_ck", 2),
	 *GATE_TOP1(CLK_TOP_APLL12_DIV1, "apll12_div1", "aud_1_ck", 3),
	 *GATE_TOP1(CLK_TOP_APLL12_DIV2, "apll12_div2", "aud_1_ck", 4),
	 *GATE_TOP1(CLK_TOP_APLL12_DIV3, "apll12_div3", "aud_1_ck", 5),
	 *GATE_TOP1(CLK_TOP_APLL12_DIV4, "apll12_div4", "aud_1_ck", 6),
	 *GATE_TOP1(CLK_TOP_APLL12_DIVB, "apll12_divb", "aud_1_ck", 7),
	 */
};

static const struct mtk_gate_regs ifr0_cg_regs = {
	.set_ofs = 0x80,
	.clr_ofs = 0x84,
	.sta_ofs = 0x90,
};

static const struct mtk_gate_regs ifr1_cg_regs = {
	.set_ofs = 0x88,
	.clr_ofs = 0x8c,
	.sta_ofs = 0x94,
};

static const struct mtk_gate_regs ifr2_cg_regs = {
	.set_ofs = 0xa4,
	.clr_ofs = 0xa8,
	.sta_ofs = 0xac,
};

static const struct mtk_gate_regs ifr3_cg_regs = {
	.set_ofs = 0xc0,
	.clr_ofs = 0xc4,
	.sta_ofs = 0xc8,
};

#define GATE_IFR0(_id, _name, _parent, _shift) {	\
		.id = _id,				\
		.name = _name,				\
		.parent_name = _parent,			\
		.regs = &ifr0_cg_regs,			\
		.shift = _shift,			\
		.ops = &mtk_clk_gate_ops_setclr,	\
	}

#define GATE_IFR1(_id, _name, _parent, _shift) {	\
		.id = _id,				\
		.name = _name,				\
		.parent_name = _parent,			\
		.regs = &ifr1_cg_regs,			\
		.shift = _shift,			\
		.ops = &mtk_clk_gate_ops_setclr,	\
	}

#define GATE_IFR1_I(_id, _name, _parent, _shift) {	\
		.id = _id,				\
		.name = _name,				\
		.parent_name = _parent,			\
		.regs = &ifr1_cg_regs,			\
		.shift = _shift,			\
		.ops = &mtk_clk_gate_ops_setclr_inv,	\
	}

#define GATE_IFR2(_id, _name, _parent, _shift) {	\
		.id = _id,				\
		.name = _name,				\
		.parent_name = _parent,			\
		.regs = &ifr2_cg_regs,			\
		.shift = _shift,			\
		.ops = &mtk_clk_gate_ops_setclr,	\
	}

#define GATE_IFR3(_id, _name, _parent, _shift) {	\
		.id = _id,				\
		.name = _name,				\
		.parent_name = _parent,			\
		.regs = &ifr3_cg_regs,			\
		.shift = _shift,			\
		.ops = &mtk_clk_gate_ops_setclr,	\
	}

static const struct mtk_gate ifr_clks[] = {
	/* IFR0 */
	GATE_IFR0(CLK_IFR_APXGPT, "ifr_apxgpt", "hd_faxi_ck", 6),
	GATE_IFR0(CLK_IFR_ICUSB, "ifr_icusb", "hd_faxi_ck", 8),
	GATE_IFR0(CLK_IFR_GCE, "ifr_gce", "hd_faxi_ck", 9),
	GATE_IFR0(CLK_IFR_THERM, "ifr_therm", "hd_faxi_ck", 10),
	GATE_IFR0(CLK_IFR_I2C_AP, "ifr_i2c_ap", "i2c_ck", 11),
	GATE_IFR0(CLK_IFR_I2C_CCU, "ifr_i2c_ccu", "i2c_ck", 12),
	GATE_IFR0(CLK_IFR_I2C_SSPM, "ifr_i2c_sspm", "i2c_ck", 13),
	GATE_IFR0(CLK_IFR_I2C_RSV, "ifr_i2c_rsv", "i2c_ck", 14),
	GATE_IFR0(CLK_IFR_PWM_HCLK, "ifr_pwm_hclk", "hd_faxi_ck", 15),
	GATE_IFR0(CLK_IFR_PWM1, "ifr_pwm1", "pwm_ck", 16),
	GATE_IFR0(CLK_IFR_PWM2, "ifr_pwm2", "pwm_ck", 17),
	GATE_IFR0(CLK_IFR_PWM3, "ifr_pwm3", "pwm_ck", 18),
	GATE_IFR0(CLK_IFR_PWM4, "ifr_pwm4", "pwm_ck", 19),
	GATE_IFR0(CLK_IFR_PWM5, "ifr_pwm5", "pwm_ck", 20),
	GATE_IFR0(CLK_IFR_PWM, "ifr_pwm", "pwm_ck", 21),
	GATE_IFR0(CLK_IFR_UART0, "ifr_uart0", "f_fuart_ck", 22),
	GATE_IFR0(CLK_IFR_UART1, "ifr_uart1", "f_fuart_ck", 23),
	GATE_IFR0(CLK_IFR_UART2, "ifr_uart2", "f_fuart_ck", 24),
	GATE_IFR0(CLK_IFR_UART3, "ifr_uart3", "f_fuart_ck", 25),
	GATE_IFR0(CLK_IFR_GCE_26M, "ifr_gce_26m", "clk26m", 27),
	GATE_IFR0(CLK_IFR_CQ_DMA_FPC, "ifr_dma", "hd_faxi_ck", 28),
	/* IFR1 */
	GATE_IFR1(CLK_IFR_SPI0, "ifr_spi0", "spi_ck", 1),
	GATE_IFR1(CLK_IFR_MSDC0, "ifr_msdc0", "msdc5_0hclk", 2),
	GATE_IFR1(CLK_IFR_MSDC1, "ifr_msdc1", "hd_faxi_ck", 4),
	GATE_IFR1(CLK_IFR_MSDC2, "ifr_msdc2_clk", "msdc5_2hclk_ck", 5),
	GATE_IFR1_I(CLK_IFR_TRNG, "ifr_trng", "hd_faxi_ck", 9),
	GATE_IFR1(CLK_IFR_CCIF1_AP, "ifr_ccif1_ap", "hd_faxi_ck", 12),
	GATE_IFR1(CLK_IFR_CCIF1_MD, "ifr_ccif1_md", "hd_faxi_ck", 13),
	GATE_IFR1(CLK_IFR_PCIE, "ifr_pcie", "pcie_mac_ck", 16),
	GATE_IFR1(CLK_IFR_NFI, "ifr_nfi", "nfi1x_bclk_ck", 17),
	GATE_IFR1(CLK_IFR_AP_DMA, "ifr_ap_dma", "hd_faxi_ck", 18),
	GATE_IFR1(CLK_IFR_DEVICE_APC, "ifr_dapc", "hd_faxi_ck", 20),
	GATE_IFR1(CLK_IFR_CCIF_AP, "ifr_ccif_ap", "hd_faxi_ck", 23),
	/* GATE_IFR1(CLK_IFR_DEBUGSYS, "ifr_debugsys", "hd_faxi_ck", 24), */
	GATE_IFR1(CLK_IFR_CCIF_MD, "ifr_ccif_md", "hd_faxi_ck", 26),
	/* GATE_IFR1(CLK_IFR_HSM, "ifr_hsm", "hsm_crypto_ck", 27),
	 * GATE_IFR1(CLK_IFR_HSM_AO, "ifr_hsm_ao", "hsm_crypto_ck", 28),
	 */
	GATE_IFR1(CLK_IFR_ETHER, "ifr_ether", "ether_125m_ck", 29),
	GATE_IFR1(CLK_IFR_SPI_SLAVE, "ifr_spi_slave", "spislv_ck", 30),
	/* IFR2 */
	GATE_IFR2(CLK_IFR_RG_PWM_FBCLK6, "ifr_pwmfb", "clk26m", 0),
	GATE_IFR2(CLK_IFR_SSUSB, "ifr_ssusb", "f_fssusb_top_ck", 1),
	GATE_IFR2(CLK_IFR_CLDMA_BCLK, "ifr_cldmabclk", "hd_faxi_ck", 3),
	GATE_IFR2(CLK_IFR_AUDIO_26M_BCLK, "ifr_audio26m", "clk26m", 4),
	GATE_IFR2(CLK_IFR_SPI1, "ifr_spi1", "spi_ck", 6),
	GATE_IFR2(CLK_IFR_SPI2, "ifr_spi2", "spi_ck", 9),
	GATE_IFR2(CLK_IFR_SPI3, "ifr_spi3", "spi_ck", 10),
	GATE_IFR2(CLK_IFR_SPI4, "ifr_spi4", "spi_ck", 25),
	GATE_IFR2(CLK_IFR_SPI5, "ifr_spi5", "spi_ck", 26),
	GATE_IFR2(CLK_IFR_CQ_DMA, "ifr_cq_dma", "hd_faxi_ck", 27),
	/* IFR3 */
	GATE_IFR3(CLK_IFR_I2C6, "ifr_i2c6", "i2c_ck", 6),
	GATE_IFR3(CLK_IFR_MSDC0_SRC, "ifr_msdc0_clk", "msdc50_0_ck", 9),
	GATE_IFR3(CLK_IFR_MSDC1_SRC, "ifr_msdc1_clk", "msdc30_1_ck", 10),
	GATE_IFR3(CLK_IFR_MSDC2_SRC, "ifr_msdc2", "msdc30_2_ck", 11),
	GATE_IFR3(CLK_IFR_MCU_PM_BCLK, "ifr_mcu_pm_bclk", "hd_faxi_ck", 17),
	GATE_IFR3(CLK_IFR_CCIF2_AP, "ifr_ccif2_ap", "hd_faxi_ck", 18),
	GATE_IFR3(CLK_IFR_CCIF2_MD, "ifr_ccif2_md", "hd_faxi_ck", 19),
	GATE_IFR3(CLK_IFR_UART4, "ifr_uart4", "hd_faxi_ck", 22),
	GATE_IFR3(CLK_IFR_UART5, "ifr_uart5", "hd_faxi_ck", 23),
	GATE_IFR3(CLK_IFR_UART6, "ifr_uart6", "hd_faxi_ck", 24),
};

/* FIXME: modify FMAX/FMIN/RSTBAR */
#define MT2731_PLL_FMAX		(3000UL * MHZ)
#define MT2731_PLL_FMIN		(1500UL * MHZ)
#define CON0_MT2731_RST_BAR	BIT(23)

#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
		_pcwibits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,\
		_tuner_en_bit, _pcw_reg, _pcw_shift, \
		_pcw_chg_reg, _div_table) {\
		.id = _id,						\
		.name = _name,						\
		.reg = _reg,						\
		.pwr_reg = _pwr_reg,					\
		.en_mask = _en_mask,					\
		.flags = _flags,					\
		.rst_bar_mask = CON0_MT2731_RST_BAR,			\
		.fmax = MT2731_PLL_FMAX,				\
		.fmin = MT2731_PLL_FMIN,				\
		.pcwbits = _pcwbits,					\
		.pcwibits = _pcwibits,					\
		.pd_reg = _pd_reg,					\
		.pd_shift = _pd_shift,					\
		.tuner_reg = _tuner_reg,				\
		.tuner_en_reg = _tuner_en_reg,				\
		.tuner_en_bit = _tuner_en_bit,				\
		.pcw_reg = _pcw_reg,					\
		.pcw_shift = _pcw_shift,				\
		.pcw_chg_reg = _pcw_chg_reg,				\
		.div_table = _div_table,				\
	}

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
			_pcwibits, _pd_reg, _pd_shift, _tuner_reg,	\
			_tuner_en_reg, _tuner_en_bit, _pcw_reg,	\
			_pcw_shift, _pcw_chg_reg)	\
		PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags,	\
			_pcwbits, _pcwibits, _pd_reg, _pd_shift,	\
			_tuner_reg, _tuner_en_reg, _tuner_en_bit,	\
			_pcw_reg, _pcw_shift, _pcw_chg_reg, NULL)	\

static const struct mtk_pll_div_table armpll_div_table[] = {
	{ .div = 0, .freq = MT2731_PLL_FMAX },
	{ .div = 1, .freq = 1500 * MHZ },
	{ .div = 2, .freq = 750 * MHZ },
	{ .div = 3, .freq = 375 * MHZ },
	{ .div = 4, .freq = 187500000 },
	{ } /* sentinel */
};

/* The frequency of mainpll and univpll are NOT recommended to adjust. */
static const struct mtk_pll_data plls[] = {
	/* _pd_reg: postdiv */
	PLL_B(CLK_APMIXED_ARMPLL, "armpll", 0x0204, 0x0210, BIT(0),
		PLL_AO, 22, 8, 0x0208, 24, 0, 0, 0, 0x0208, 0, 0,
		armpll_div_table),
	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0214, 0x0220, BIT(0),
		HAVE_RST_BAR | PLL_AO, 22, 8, 0x0218, 24, 0, 0, 0, 0x0218, 0,
		0),
	/*
	 * In order to generate u192M, univpll HW always need freq*2(hw will/2).
	 * But some user still need get_rate, we have to return the accurate
	 * rate, thus use 7 for pcwibits. It's ok since the reg keep as-is.
	 */
	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0224, 0x0230, BIT(0),
		HAVE_RST_BAR, 22, 7, 0x0228, 24, 0, 0, 0, 0x0228, 0, 0),
	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0234, 0x0240, BIT(0),
		0, 22, 8, 0x0238, 24, 0, 0, 0, 0x0238, 0, 0),
	PLL(CLK_APMIXED_APLL1, "apll1", 0x0244, 0x0254, BIT(0),
		0, 32, 8, 0x0248, 24, 0x40, 0x0C, 0, 0x024C, 0, 0x248),
	/* No tuner for apll2. */
	PLL(CLK_APMIXED_APLL2, "apll2", 0x0258, 0x0268, BIT(0),
		0, 32, 8, 0x025C, 24, 0, 0, 0, 0x0260, 0, 0x25C),
	PLL(CLK_APMIXED_MPLL, "mpll", 0x026C, 0x0278, BIT(0),
		PLL_AO, 22, 8, 0x0270, 24, 0, 0, 0, 0x0270, 0, 0),
	PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x027C, 0x0288, BIT(0),
		0, 22, 8, 0x0280, 24, 0, 0, 0, 0x0280, 0, 0),
};

static int clk_mt2731_apmixed_probe(struct platform_device *pdev)
{
	struct clk_onecell_data *clk_data;
	int r;
	struct device_node *node = pdev->dev.of_node;
	void __iomem *base;
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	u32 reg;

	clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);

	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);

	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

	if (r)
		pr_notice("%s(): could not register clock provider: %d\n",
			__func__, r);

	/* switch PLL/BUS mux to spm control.*/
	#define PLLON_CON0     0x44
	#define AP_PLL_CON3    0xC
	base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(base)) {
		pr_notice("%s(): ioremap failed\n", __func__);
		return PTR_ERR(base);
	}
	reg = readl_relaxed(base + PLLON_CON0);

	/* reg &= ~(BIT(16) | BIT(20) | BIT(24)); univpll */
	reg &= ~(BIT(17) | BIT(21) | BIT(25)); /* mpll */
	reg &= ~(BIT(18) | BIT(22) | BIT(26)); /* mainpll */
	reg &= ~(BIT(19) | BIT(23) | BIT(27)); /* armpll */
	writel(reg, base + PLLON_CON0);

	reg = readl_relaxed(base + AP_PLL_CON3);
	reg &= ~BIT(1); /* CLKSQ sleep control. */
	reg &= ~BIT(2); /* CLKSQ LPF sleep control. */
	writel(reg, base + AP_PLL_CON3);

	devm_iounmap(&pdev->dev, base);

	return r;
}

static int clk_mt2731_top_probe(struct platform_device *pdev)
{
	int r;
	struct device_node *node = pdev->dev.of_node;
	void __iomem *base;
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct clk_onecell_data *mt2731_top_clk_data;

	base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(base)) {
		pr_notice("%s(): ioremap failed\n", __func__);
		return PTR_ERR(base);
	}

	mt2731_top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);

	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
				    mt2731_top_clk_data);
	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
				 mt2731_top_clk_data);
	/* mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
	 * base, &mt2731_clk_lock, mt2731_top_clk_data);
	 */
	mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes),
		node, &mt2731_clk_lock, mt2731_top_clk_data);
	mtk_clk_register_composites(top_audmuxes, ARRAY_SIZE(top_audmuxes),
		base, &mt2731_clk_lock, mt2731_top_clk_data);
	mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
			       mt2731_top_clk_data);

	r = of_clk_add_provider(node, of_clk_src_onecell_get,
				mt2731_top_clk_data);

	if (r)
		pr_notice("%s(): could not register clock provider: %d\n",
			__func__, r);
	//mtk_clk_enable_critical();
	{ /* switch PLL/BUS mux to spm control.*/
		#define CLK_SCP_CFG_1    0x204
		u32 reg = readl_relaxed(base + CLK_SCP_CFG_1);

		reg |= 0x1;
		writel(reg, base + CLK_SCP_CFG_1);
	}

	return r;
}

static int clk_mt2731_infra_probe(struct platform_device *pdev)
{
	struct clk_onecell_data *clk_data;
	struct device_node *node = pdev->dev.of_node;
	int r;

	clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);

	mtk_clk_register_gates(node, ifr_clks, ARRAY_SIZE(ifr_clks),
		clk_data);

	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

	if (r)
		pr_err("%s(): could not register clock provider: %d\n",
			__func__, r);

	return r;
}

static const struct of_device_id of_match_clk_mt2731[] = {
	{
		.compatible = "mediatek,mt2731-apmixedsys",
		.data = clk_mt2731_apmixed_probe,
	}, {
		.compatible = "mediatek,mt2731-topckgen",
		.data = clk_mt2731_top_probe,
	}, {
		.compatible = "mediatek,mt2731-infracfg",
		.data = clk_mt2731_infra_probe,
	}, {
		/* sentinel */
	}
};

static int clk_mt2731_probe(struct platform_device *pdev)
{
	int (*clk_probe)(struct platform_device *);
	int r;

	clk_probe = of_device_get_match_data(&pdev->dev);
	if (!clk_probe)
		return -EINVAL;

	r = clk_probe(pdev);
	if (r)
		dev_notice(&pdev->dev,
			"could not register clock provider: %s: %d\n",
			pdev->name, r);

	return r;
}

static struct platform_driver clk_mt2731_drv = {
	.probe = clk_mt2731_probe,
	.driver = {
		.name = "clk-mt2731",
		.owner = THIS_MODULE,
		.of_match_table = of_match_clk_mt2731,
	},
};

static int __init clk_mt2731_init(void)
{
	return platform_driver_register(&clk_mt2731_drv);
}

arch_initcall(clk_mt2731_init);