blob: cdb43270cd5873851442e70cbba41b6833b010dd [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +08001/*
2 * Copyright (c) 2018 MediaTek Inc.
3 * Author: Weiyi Lu <weiyi.lu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clk-provider.h>
16#include <linux/platform_device.h>
17
18#include "clk-mtk.h"
19#include "clk-gate.h"
20
21#include <dt-bindings/clock/mt8183-clk.h>
22
23static const struct mtk_gate_regs img_cg_regs = {
24 .set_ofs = 0x4,
25 .clr_ofs = 0x8,
26 .sta_ofs = 0x0,
27};
28
29#define GATE_IMG(_id, _name, _parent, _shift) { \
30 .id = _id, \
31 .name = _name, \
32 .parent_name = _parent, \
33 .regs = &img_cg_regs, \
34 .shift = _shift, \
35 .ops = &mtk_clk_gate_ops_setclr, \
36 }
37
38static const struct mtk_gate img_clks[] = {
39 GATE_IMG(CLK_IMG_LARB5, "img_larb5", "img_sel", 0),
40 GATE_IMG(CLK_IMG_LARB2, "img_larb2", "img_sel", 1),
41 GATE_IMG(CLK_IMG_DIP, "img_dip", "img_sel", 2),
42 GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "img_sel", 3),
43 GATE_IMG(CLK_IMG_DPE, "img_dpe", "img_sel", 4),
44 GATE_IMG(CLK_IMG_RSC, "img_rsc", "img_sel", 5),
45 GATE_IMG(CLK_IMG_MFB, "img_mfb", "img_sel", 6),
46 GATE_IMG(CLK_IMG_WPE_A, "img_wpe_a", "img_sel", 7),
47 GATE_IMG(CLK_IMG_WPE_B, "img_wpe_b", "img_sel", 8),
48 GATE_IMG(CLK_IMG_OWE, "img_owe", "img_sel", 9),
49};
50
51static int clk_mt8183_img_probe(struct platform_device *pdev)
52{
53 struct clk_onecell_data *clk_data;
54 int r;
55 struct device_node *node = pdev->dev.of_node;
56
57 clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
58
59 mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
60 clk_data);
61
62 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
63
64 if (r)
65 pr_err("%s(): could not register clock provider: %d\n",
66 __func__, r);
67
68 return r;
69}
70
71static const struct of_device_id of_match_clk_mt8183_img[] = {
72 { .compatible = "mediatek,mt8183-imgsys", },
73 {}
74};
75
76static struct platform_driver clk_mt8183_img_drv = {
77 .probe = clk_mt8183_img_probe,
78 .driver = {
79 .name = "clk-mt8183-img",
80 .of_match_table = of_match_clk_mt8183_img,
81 },
82};
83
84builtin_platform_driver(clk_mt8183_img_drv);