blob: d92216e0d3c0dd465dd08a441bcafe09948621b1 [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +08001/*
2 * Copyright (c) 2018 MediaTek Inc.
3 * Author: Weiyi Lu <weiyi.lu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clk-provider.h>
16#include <linux/platform_device.h>
17
18#include "clk-mtk.h"
19#include "clk-gate.h"
20
21#include <dt-bindings/clock/mt8183-clk.h>
22
23static const struct mtk_gate_regs mm0_cg_regs = {
24 .set_ofs = 0x104,
25 .clr_ofs = 0x108,
26 .sta_ofs = 0x100,
27};
28
29static const struct mtk_gate_regs mm1_cg_regs = {
30 .set_ofs = 0x114,
31 .clr_ofs = 0x118,
32 .sta_ofs = 0x110,
33};
34
35#define GATE_MM0(_id, _name, _parent, _shift) { \
36 .id = _id, \
37 .name = _name, \
38 .parent_name = _parent, \
39 .regs = &mm0_cg_regs, \
40 .shift = _shift, \
41 .ops = &mtk_clk_gate_ops_setclr, \
42 }
43
44#define GATE_MM1(_id, _name, _parent, _shift) { \
45 .id = _id, \
46 .name = _name, \
47 .parent_name = _parent, \
48 .regs = &mm1_cg_regs, \
49 .shift = _shift, \
50 .ops = &mtk_clk_gate_ops_setclr, \
51 }
52
53static const struct mtk_gate mm_clks[] = {
54 /* MM0 */
55 GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
56 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
57 GATE_MM0(CLK_MM_SMI_LARB1, "mm_smi_larb1", "mm_sel", 2),
58 GATE_MM0(CLK_MM_GALS_COMM0, "mm_gals_comm0", "mm_sel", 3),
59 GATE_MM0(CLK_MM_GALS_COMM1, "mm_gals_comm1", "mm_sel", 4),
60 GATE_MM0(CLK_MM_GALS_CCU2MM, "mm_gals_ccu2mm", "mm_sel", 5),
61 GATE_MM0(CLK_MM_GALS_IPU12MM, "mm_gals_ipu12mm", "mm_sel", 6),
62 GATE_MM0(CLK_MM_GALS_IMG2MM, "mm_gals_img2mm", "mm_sel", 7),
63 GATE_MM0(CLK_MM_GALS_CAM2MM, "mm_gals_cam2mm", "mm_sel", 8),
64 GATE_MM0(CLK_MM_GALS_IPU2MM, "mm_gals_ipu2mm", "mm_sel", 9),
65 GATE_MM0(CLK_MM_MDP_DL_TXCK, "mm_mdp_dl_txck", "mm_sel", 10),
66 GATE_MM0(CLK_MM_IPU_DL_TXCK, "mm_ipu_dl_txck", "mm_sel", 11),
67 GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 12),
68 GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 13),
69 GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 14),
70 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 15),
71 GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 16),
72 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 17),
73 GATE_MM0(CLK_MM_MDP_WDMA0, "mm_mdp_wdma0", "mm_sel", 18),
74 GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 19),
75 GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 20),
76 GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 21),
77 GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 22),
78 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 23),
79 GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 24),
80 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 25),
81 GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 26),
82 GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_sel", 27),
83 GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "mm_sel", 28),
84 GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_sel", 29),
85 GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "mm_sel", 30),
86 GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31),
87 /* MM1 */
88 GATE_MM1(CLK_MM_DSI0_MM, "mm_dsi0_mm", "mm_sel", 0),
89 GATE_MM1(CLK_MM_DSI0_IF, "mm_dsi0_if", "mm_sel", 1),
90 GATE_MM1(CLK_MM_DPI_MM, "mm_dpi_mm", "mm_sel", 2),
91 GATE_MM1(CLK_MM_DPI_IF, "mm_dpi_if", "dpi0_sel", 3),
92 GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 4),
93 GATE_MM1(CLK_MM_MDP_DL_RX, "mm_mdp_dl_rx", "mm_sel", 5),
94 GATE_MM1(CLK_MM_IPU_DL_RX, "mm_ipu_dl_rx", "mm_sel", 6),
95 GATE_MM1(CLK_MM_26M, "mm_26m", "f_f26m_ck", 7),
96 GATE_MM1(CLK_MM_MMSYS_R2Y, "mm_mmsys_r2y", "mm_sel", 8),
97 GATE_MM1(CLK_MM_DISP_RSZ, "mm_disp_rsz", "mm_sel", 9),
98 GATE_MM1(CLK_MM_MDP_AAL, "mm_mdp_aal", "mm_sel", 10),
99 GATE_MM1(CLK_MM_MDP_CCORR, "mm_mdp_ccorr", "mm_sel", 11),
100 GATE_MM1(CLK_MM_DBI_MM, "mm_dbi_mm", "mm_sel", 12),
101 GATE_MM1(CLK_MM_DBI_IF, "mm_dbi_if", "dpi0_sel", 13),
102};
103
104static int clk_mt8183_mm_probe(struct platform_device *pdev)
105{
106 struct clk_onecell_data *clk_data;
107 int r;
108 struct device_node *node = pdev->dev.of_node;
109
110 clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
111
112 mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
113 clk_data);
114
115 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
116
117 if (r)
118 pr_err("%s(): could not register clock provider: %d\n",
119 __func__, r);
120
121 return r;
122}
123
124static const struct of_device_id of_match_clk_mt8183_mm[] = {
125 { .compatible = "mediatek,mt8183-mmsys", },
126 {}
127};
128
129static struct platform_driver clk_mt8183_mm_drv = {
130 .probe = clk_mt8183_mm_probe,
131 .driver = {
132 .name = "clk-mt8183-mm",
133 .of_match_table = of_match_clk_mt8183_mm,
134 },
135};
136
137builtin_platform_driver(clk_mt8183_mm_drv);