rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (c) 2018 MediaTek Inc. |
| 4 | * Author: Yong Wu <yong.wu@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | #include <linux/module.h> |
| 8 | #include "clkchk.h" |
| 9 | |
| 10 | static const char * const off_pll_names[] = { |
| 11 | "armpll", |
| 12 | "mainpll", |
| 13 | "univpll", |
| 14 | "msdcpll", |
| 15 | "apll1", |
| 16 | "apll2", |
| 17 | "mpll", |
| 18 | "etherpll", |
| 19 | NULL |
| 20 | }; |
| 21 | |
| 22 | static const char * const all_clk_names[] = { |
| 23 | "armpll", |
| 24 | "mainpll", |
| 25 | "univpll", |
| 26 | "msdcpll", |
| 27 | "apll1", |
| 28 | "apll2", |
| 29 | "mpll", |
| 30 | "etherpll", |
| 31 | "syspll_ck", |
| 32 | "syspll_d2", |
| 33 | "syspll1_d2", |
| 34 | "syspll1_d4", |
| 35 | "syspll1_d8", |
| 36 | "syspll1_d16", |
| 37 | "syspll_d3", |
| 38 | "syspll2_d2", |
| 39 | "syspll2_d4", |
| 40 | "syspll2_d8", |
| 41 | "syspll_d5", |
| 42 | "syspll3_d2", |
| 43 | "syspll3_d4", |
| 44 | "syspll_d7", |
| 45 | "syspll4_d2", |
| 46 | "syspll4_d4", |
| 47 | "usb20_192m_ck", |
| 48 | "usb20_192m_d2", |
| 49 | "usb20_192m_d4", |
| 50 | "univpll_d2", |
| 51 | "univpll1_d2", |
| 52 | "univpll1_d4", |
| 53 | "univpll1_d8", |
| 54 | "univpll_d3", |
| 55 | "univpll2_d2", |
| 56 | "univpll2_d4", |
| 57 | "univpll2_d8", |
| 58 | "univpll2_d16", |
| 59 | "univpll_d5", |
| 60 | "univpll3_d2", |
| 61 | "univpll3_d4", |
| 62 | "msdcpll_ck", |
| 63 | "msdcpll_d2", |
| 64 | "apll1_ck", |
| 65 | "apll1_d2", |
| 66 | "apll1_d4", |
| 67 | "apll1_d8", |
| 68 | "apll2_ck", |
| 69 | "apll2_d2", |
| 70 | "apll2_d4", |
| 71 | "apll2_d8", |
| 72 | "etherpll_ck", |
| 73 | "etherpll_d4", |
| 74 | "etherpll_d10", |
| 75 | "hd_faxi_ck", |
| 76 | "f_fuart_ck", |
| 77 | "spi_ck", |
| 78 | "msdc50_0_ck", |
| 79 | "msdc30_1_ck", |
| 80 | "audio_ck", |
| 81 | "aud_1_ck", |
| 82 | "aud_engen1_ck", |
| 83 | "aud_engen2_ck", |
| 84 | "hsm_crypto_ck", |
| 85 | "i2c_ck", |
| 86 | "msdc5_2hclk_ck", |
| 87 | "msdc30_2_ck", |
| 88 | "nfi1x_bclk_ck", |
| 89 | "pcie_mac_ck", |
| 90 | "f_fssusb_top_ck", |
| 91 | "spislv_ck", |
| 92 | "ether_125m_ck", |
| 93 | "pwm_ck", |
| 94 | "arm_div_pll1", |
| 95 | "arm_div_pll2", |
| 96 | |
| 97 | /* CLK_CFG_0 */ |
| 98 | "axi_sel", |
| 99 | "uart_sel", |
| 100 | "spi_sel", |
| 101 | "msdc5_0hclk", |
| 102 | |
| 103 | /* CLK_CFG_1 */ |
| 104 | "msdc50_0_sel", |
| 105 | "msdc30_1_sel", |
| 106 | "audio_sel", |
| 107 | "aud_intbus_sel", |
| 108 | "aud_1_sel", |
| 109 | "aud_2_sel", |
| 110 | "aud_engen1_sel", |
| 111 | "aud_engen2_sel", |
| 112 | |
| 113 | /* CLK_CFG_3 */ |
| 114 | "dxcc_sel", |
| 115 | "hsm_crypto_sel", |
| 116 | "hsm_arc_sel", |
| 117 | "gcpu_sel", |
| 118 | |
| 119 | /* CLK_CFG_4 */ |
| 120 | "ecc_sel", |
| 121 | "usb_top_sel", |
| 122 | "spm_sel", |
| 123 | "i2c_sel", |
| 124 | |
| 125 | /* CLK_CFG_5 */ |
| 126 | "ulposc_sel", |
| 127 | "msdc5_2hclk_sel", |
| 128 | "msdc30_2_sel", |
| 129 | "nfi1x_bclk_sel", |
| 130 | |
| 131 | /* CLK_CFG_6 */ |
| 132 | "spinfi_bclk_sel", |
| 133 | "pcie_mac_sel", |
| 134 | "ssusb_top_sel", |
| 135 | "spislv_sel", |
| 136 | |
| 137 | /* CLK_CFG_7 */ |
| 138 | "ether_125m_sel", |
| 139 | "ether_50_sel", |
| 140 | "ether_62p4m_sel", |
| 141 | "pwm_sel", |
| 142 | |
| 143 | "i2s0_m_ck_sel", |
| 144 | "i2s1_m_ck_sel", |
| 145 | "i2s2_m_ck_sel", |
| 146 | "i2s3_m_ck_sel", |
| 147 | "i2s4_m_ck_sel", |
| 148 | |
| 149 | "apll12_div0", |
| 150 | "apll12_div1", |
| 151 | "apll12_div2", |
| 152 | "apll12_div3", |
| 153 | "apll12_div4", |
| 154 | "apll12_divb", |
| 155 | |
| 156 | "arm_div_pll1_en", |
| 157 | "arm_div_pll2_en", |
| 158 | |
| 159 | /* IFR0 */ |
| 160 | "ifr_apxgpt", |
| 161 | "ifr_icusb", |
| 162 | "ifr_gce", |
| 163 | "ifr_therm", |
| 164 | "ifr_i2c_ap", |
| 165 | "ifr_i2c_ccu", |
| 166 | "ifr_i2c_sspm", |
| 167 | "ifr_i2c_rsv", |
| 168 | "ifr_pwm_hclk", |
| 169 | "ifr_pwm1", |
| 170 | "ifr_pwm2", |
| 171 | "ifr_pwm3", |
| 172 | "ifr_pwm4", |
| 173 | "ifr_pwm5", |
| 174 | "ifr_pwm", |
| 175 | "ifr_uart0", |
| 176 | "ifr_uart1", |
| 177 | "ifr_uart2", |
| 178 | "ifr_uart3", |
| 179 | "ifr_gce_26m", |
| 180 | "ifr_dma", |
| 181 | /* IFR1 */ |
| 182 | "ifr_spi0", |
| 183 | "ifr_msdc0", |
| 184 | "ifr_msdc1", |
| 185 | "ifr_msdc2", |
| 186 | "ifr_trng", |
| 187 | "ifr_ccif1_ap", |
| 188 | "ifr_ccif1_md", |
| 189 | "ifr_pcie", |
| 190 | "ifr_nfi", |
| 191 | "ifr_ap_dma", |
| 192 | "ifr_dapc", |
| 193 | "ifr_ccif_ap", |
| 194 | "ifr_debugsys", |
| 195 | "ifr_ccif_md", |
| 196 | "ifr_hsm", |
| 197 | "ifr_hsm_ao", |
| 198 | "ifr_ether", |
| 199 | "ifr_spi_slave", |
| 200 | /* IFR2 */ |
| 201 | "ifr_pwmfb", |
| 202 | "ifr_ssusb", |
| 203 | "ifr_cldmabclk", |
| 204 | "ifr_audio26m", |
| 205 | "ifr_spi1", |
| 206 | "ifr_spi2", |
| 207 | "ifr_spi3", |
| 208 | "ifr_spi4", |
| 209 | "ifr_spi5", |
| 210 | "ifr_cq_dma", |
| 211 | /* IFR3 */ |
| 212 | "ifr_i2c6", |
| 213 | "ifr_msdc0_clk", |
| 214 | "ifr_msdc1_clk", |
| 215 | "ifr_msdc2_clk", |
| 216 | "ifr_mcu_pm_bclk", |
| 217 | "ifr_ccif2_ap", |
| 218 | "ifr_ccif2_md", |
| 219 | "ifr_uart4", |
| 220 | "ifr_uart5", |
| 221 | "ifr_uart6", |
| 222 | /* end */ |
| 223 | NULL |
| 224 | }; |
| 225 | |
| 226 | static const char * const compatible[] = {"mediatek,mt2731", NULL}; |
| 227 | |
| 228 | static struct clkchk_cfg_t cfg = { |
| 229 | .aee_excp_on_fail = false, |
| 230 | .warn_on_fail = false, |
| 231 | .compatible = compatible, |
| 232 | .off_pll_names = off_pll_names, |
| 233 | .all_clk_names = all_clk_names, |
| 234 | }; |
| 235 | |
| 236 | static int __init clkchk_platform_init(void) |
| 237 | { |
| 238 | return clkchk_init(&cfg); |
| 239 | } |
| 240 | late_initcall(clkchk_platform_init); |
| 241 | |