| rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2017 BayLibre, SAS |
| 3 | * Author: Neil Armstrong <narmstrong@baylibre.com> |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #ifndef __GXBB_AOCLKC_H |
| 9 | #define __GXBB_AOCLKC_H |
| 10 | |
| 11 | /* AO Configuration Clock registers offsets */ |
| 12 | #define AO_RTI_PWR_CNTL_REG1 0x0c |
| 13 | #define AO_RTI_PWR_CNTL_REG0 0x10 |
| 14 | #define AO_RTI_GEN_CNTL_REG0 0x40 |
| 15 | #define AO_OSCIN_CNTL 0x58 |
| 16 | #define AO_CRT_CLK_CNTL1 0x68 |
| 17 | #define AO_RTC_ALT_CLK_CNTL0 0x94 |
| 18 | #define AO_RTC_ALT_CLK_CNTL1 0x98 |
| 19 | |
| 20 | struct aoclk_gate_regmap { |
| 21 | struct clk_hw hw; |
| 22 | unsigned bit_idx; |
| 23 | struct regmap *regmap; |
| 24 | spinlock_t *lock; |
| 25 | }; |
| 26 | |
| 27 | #define to_aoclk_gate_regmap(_hw) \ |
| 28 | container_of(_hw, struct aoclk_gate_regmap, hw) |
| 29 | |
| 30 | extern const struct clk_ops meson_aoclk_gate_regmap_ops; |
| 31 | |
| 32 | struct aoclk_cec_32k { |
| 33 | struct clk_hw hw; |
| 34 | struct regmap *regmap; |
| 35 | spinlock_t *lock; |
| 36 | }; |
| 37 | |
| 38 | #define to_aoclk_cec_32k(_hw) container_of(_hw, struct aoclk_cec_32k, hw) |
| 39 | |
| 40 | extern const struct clk_ops meson_aoclk_cec_32k_ops; |
| 41 | |
| 42 | #endif /* __GXBB_AOCLKC_H */ |