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192.168.1.100 / T103 / 1f884588077ad3476b9c91cbb0ee9ee0332bbb68 / . / src / kernel / linux / v4.14 / drivers / clk / meson / gxbb.c
blob: f2d27addf485c56c49bdb6e03fba617278ba64d7 [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +0800[diff] [blame^]1/*
2 * AmLogic S905 / GXBB Clock Controller Driver
3 *
4 * Copyright (c) 2016 AmLogic, Inc.
5 * Michael Turquette <mturquette@baylibre.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <linux/clk.h>
21#include <linux/clk-provider.h>
22#include <linux/of_address.h>
23#include <linux/of_device.h>
24#include <linux/platform_device.h>
25#include <linux/init.h>
26
27#include "clkc.h"
28#include "gxbb.h"
29
30static DEFINE_SPINLOCK(clk_lock);
31
32static const struct pll_rate_table sys_pll_rate_table[] = {
33 PLL_RATE(24000000, 56, 1, 2),
34 PLL_RATE(48000000, 64, 1, 2),
35 PLL_RATE(72000000, 72, 1, 2),
36 PLL_RATE(96000000, 64, 1, 2),
37 PLL_RATE(120000000, 80, 1, 2),
38 PLL_RATE(144000000, 96, 1, 2),
39 PLL_RATE(168000000, 56, 1, 1),
40 PLL_RATE(192000000, 64, 1, 1),
41 PLL_RATE(216000000, 72, 1, 1),
42 PLL_RATE(240000000, 80, 1, 1),
43 PLL_RATE(264000000, 88, 1, 1),
44 PLL_RATE(288000000, 96, 1, 1),
45 PLL_RATE(312000000, 52, 1, 2),
46 PLL_RATE(336000000, 56, 1, 2),
47 PLL_RATE(360000000, 60, 1, 2),
48 PLL_RATE(384000000, 64, 1, 2),
49 PLL_RATE(408000000, 68, 1, 2),
50 PLL_RATE(432000000, 72, 1, 2),
51 PLL_RATE(456000000, 76, 1, 2),
52 PLL_RATE(480000000, 80, 1, 2),
53 PLL_RATE(504000000, 84, 1, 2),
54 PLL_RATE(528000000, 88, 1, 2),
55 PLL_RATE(552000000, 92, 1, 2),
56 PLL_RATE(576000000, 96, 1, 2),
57 PLL_RATE(600000000, 50, 1, 1),
58 PLL_RATE(624000000, 52, 1, 1),
59 PLL_RATE(648000000, 54, 1, 1),
60 PLL_RATE(672000000, 56, 1, 1),
61 PLL_RATE(696000000, 58, 1, 1),
62 PLL_RATE(720000000, 60, 1, 1),
63 PLL_RATE(744000000, 62, 1, 1),
64 PLL_RATE(768000000, 64, 1, 1),
65 PLL_RATE(792000000, 66, 1, 1),
66 PLL_RATE(816000000, 68, 1, 1),
67 PLL_RATE(840000000, 70, 1, 1),
68 PLL_RATE(864000000, 72, 1, 1),
69 PLL_RATE(888000000, 74, 1, 1),
70 PLL_RATE(912000000, 76, 1, 1),
71 PLL_RATE(936000000, 78, 1, 1),
72 PLL_RATE(960000000, 80, 1, 1),
73 PLL_RATE(984000000, 82, 1, 1),
74 PLL_RATE(1008000000, 84, 1, 1),
75 PLL_RATE(1032000000, 86, 1, 1),
76 PLL_RATE(1056000000, 88, 1, 1),
77 PLL_RATE(1080000000, 90, 1, 1),
78 PLL_RATE(1104000000, 92, 1, 1),
79 PLL_RATE(1128000000, 94, 1, 1),
80 PLL_RATE(1152000000, 96, 1, 1),
81 PLL_RATE(1176000000, 98, 1, 1),
82 PLL_RATE(1200000000, 50, 1, 0),
83 PLL_RATE(1224000000, 51, 1, 0),
84 PLL_RATE(1248000000, 52, 1, 0),
85 PLL_RATE(1272000000, 53, 1, 0),
86 PLL_RATE(1296000000, 54, 1, 0),
87 PLL_RATE(1320000000, 55, 1, 0),
88 PLL_RATE(1344000000, 56, 1, 0),
89 PLL_RATE(1368000000, 57, 1, 0),
90 PLL_RATE(1392000000, 58, 1, 0),
91 PLL_RATE(1416000000, 59, 1, 0),
92 PLL_RATE(1440000000, 60, 1, 0),
93 PLL_RATE(1464000000, 61, 1, 0),
94 PLL_RATE(1488000000, 62, 1, 0),
95 PLL_RATE(1512000000, 63, 1, 0),
96 PLL_RATE(1536000000, 64, 1, 0),
97 PLL_RATE(1560000000, 65, 1, 0),
98 PLL_RATE(1584000000, 66, 1, 0),
99 PLL_RATE(1608000000, 67, 1, 0),
100 PLL_RATE(1632000000, 68, 1, 0),
101 PLL_RATE(1656000000, 68, 1, 0),
102 PLL_RATE(1680000000, 68, 1, 0),
103 PLL_RATE(1704000000, 68, 1, 0),
104 PLL_RATE(1728000000, 69, 1, 0),
105 PLL_RATE(1752000000, 69, 1, 0),
106 PLL_RATE(1776000000, 69, 1, 0),
107 PLL_RATE(1800000000, 69, 1, 0),
108 PLL_RATE(1824000000, 70, 1, 0),
109 PLL_RATE(1848000000, 70, 1, 0),
110 PLL_RATE(1872000000, 70, 1, 0),
111 PLL_RATE(1896000000, 70, 1, 0),
112 PLL_RATE(1920000000, 71, 1, 0),
113 PLL_RATE(1944000000, 71, 1, 0),
114 PLL_RATE(1968000000, 71, 1, 0),
115 PLL_RATE(1992000000, 71, 1, 0),
116 PLL_RATE(2016000000, 72, 1, 0),
117 PLL_RATE(2040000000, 72, 1, 0),
118 PLL_RATE(2064000000, 72, 1, 0),
119 PLL_RATE(2088000000, 72, 1, 0),
120 PLL_RATE(2112000000, 73, 1, 0),
121 { /* sentinel */ },
122};
123
124static const struct pll_rate_table gxbb_gp0_pll_rate_table[] = {
125 PLL_RATE(96000000, 32, 1, 3),
126 PLL_RATE(99000000, 33, 1, 3),
127 PLL_RATE(102000000, 34, 1, 3),
128 PLL_RATE(105000000, 35, 1, 3),
129 PLL_RATE(108000000, 36, 1, 3),
130 PLL_RATE(111000000, 37, 1, 3),
131 PLL_RATE(114000000, 38, 1, 3),
132 PLL_RATE(117000000, 39, 1, 3),
133 PLL_RATE(120000000, 40, 1, 3),
134 PLL_RATE(123000000, 41, 1, 3),
135 PLL_RATE(126000000, 42, 1, 3),
136 PLL_RATE(129000000, 43, 1, 3),
137 PLL_RATE(132000000, 44, 1, 3),
138 PLL_RATE(135000000, 45, 1, 3),
139 PLL_RATE(138000000, 46, 1, 3),
140 PLL_RATE(141000000, 47, 1, 3),
141 PLL_RATE(144000000, 48, 1, 3),
142 PLL_RATE(147000000, 49, 1, 3),
143 PLL_RATE(150000000, 50, 1, 3),
144 PLL_RATE(153000000, 51, 1, 3),
145 PLL_RATE(156000000, 52, 1, 3),
146 PLL_RATE(159000000, 53, 1, 3),
147 PLL_RATE(162000000, 54, 1, 3),
148 PLL_RATE(165000000, 55, 1, 3),
149 PLL_RATE(168000000, 56, 1, 3),
150 PLL_RATE(171000000, 57, 1, 3),
151 PLL_RATE(174000000, 58, 1, 3),
152 PLL_RATE(177000000, 59, 1, 3),
153 PLL_RATE(180000000, 60, 1, 3),
154 PLL_RATE(183000000, 61, 1, 3),
155 PLL_RATE(186000000, 62, 1, 3),
156 PLL_RATE(192000000, 32, 1, 2),
157 PLL_RATE(198000000, 33, 1, 2),
158 PLL_RATE(204000000, 34, 1, 2),
159 PLL_RATE(210000000, 35, 1, 2),
160 PLL_RATE(216000000, 36, 1, 2),
161 PLL_RATE(222000000, 37, 1, 2),
162 PLL_RATE(228000000, 38, 1, 2),
163 PLL_RATE(234000000, 39, 1, 2),
164 PLL_RATE(240000000, 40, 1, 2),
165 PLL_RATE(246000000, 41, 1, 2),
166 PLL_RATE(252000000, 42, 1, 2),
167 PLL_RATE(258000000, 43, 1, 2),
168 PLL_RATE(264000000, 44, 1, 2),
169 PLL_RATE(270000000, 45, 1, 2),
170 PLL_RATE(276000000, 46, 1, 2),
171 PLL_RATE(282000000, 47, 1, 2),
172 PLL_RATE(288000000, 48, 1, 2),
173 PLL_RATE(294000000, 49, 1, 2),
174 PLL_RATE(300000000, 50, 1, 2),
175 PLL_RATE(306000000, 51, 1, 2),
176 PLL_RATE(312000000, 52, 1, 2),
177 PLL_RATE(318000000, 53, 1, 2),
178 PLL_RATE(324000000, 54, 1, 2),
179 PLL_RATE(330000000, 55, 1, 2),
180 PLL_RATE(336000000, 56, 1, 2),
181 PLL_RATE(342000000, 57, 1, 2),
182 PLL_RATE(348000000, 58, 1, 2),
183 PLL_RATE(354000000, 59, 1, 2),
184 PLL_RATE(360000000, 60, 1, 2),
185 PLL_RATE(366000000, 61, 1, 2),
186 PLL_RATE(372000000, 62, 1, 2),
187 PLL_RATE(384000000, 32, 1, 1),
188 PLL_RATE(396000000, 33, 1, 1),
189 PLL_RATE(408000000, 34, 1, 1),
190 PLL_RATE(420000000, 35, 1, 1),
191 PLL_RATE(432000000, 36, 1, 1),
192 PLL_RATE(444000000, 37, 1, 1),
193 PLL_RATE(456000000, 38, 1, 1),
194 PLL_RATE(468000000, 39, 1, 1),
195 PLL_RATE(480000000, 40, 1, 1),
196 PLL_RATE(492000000, 41, 1, 1),
197 PLL_RATE(504000000, 42, 1, 1),
198 PLL_RATE(516000000, 43, 1, 1),
199 PLL_RATE(528000000, 44, 1, 1),
200 PLL_RATE(540000000, 45, 1, 1),
201 PLL_RATE(552000000, 46, 1, 1),
202 PLL_RATE(564000000, 47, 1, 1),
203 PLL_RATE(576000000, 48, 1, 1),
204 PLL_RATE(588000000, 49, 1, 1),
205 PLL_RATE(600000000, 50, 1, 1),
206 PLL_RATE(612000000, 51, 1, 1),
207 PLL_RATE(624000000, 52, 1, 1),
208 PLL_RATE(636000000, 53, 1, 1),
209 PLL_RATE(648000000, 54, 1, 1),
210 PLL_RATE(660000000, 55, 1, 1),
211 PLL_RATE(672000000, 56, 1, 1),
212 PLL_RATE(684000000, 57, 1, 1),
213 PLL_RATE(696000000, 58, 1, 1),
214 PLL_RATE(708000000, 59, 1, 1),
215 PLL_RATE(720000000, 60, 1, 1),
216 PLL_RATE(732000000, 61, 1, 1),
217 PLL_RATE(744000000, 62, 1, 1),
218 PLL_RATE(768000000, 32, 1, 0),
219 PLL_RATE(792000000, 33, 1, 0),
220 PLL_RATE(816000000, 34, 1, 0),
221 PLL_RATE(840000000, 35, 1, 0),
222 PLL_RATE(864000000, 36, 1, 0),
223 PLL_RATE(888000000, 37, 1, 0),
224 PLL_RATE(912000000, 38, 1, 0),
225 PLL_RATE(936000000, 39, 1, 0),
226 PLL_RATE(960000000, 40, 1, 0),
227 PLL_RATE(984000000, 41, 1, 0),
228 PLL_RATE(1008000000, 42, 1, 0),
229 PLL_RATE(1032000000, 43, 1, 0),
230 PLL_RATE(1056000000, 44, 1, 0),
231 PLL_RATE(1080000000, 45, 1, 0),
232 PLL_RATE(1104000000, 46, 1, 0),
233 PLL_RATE(1128000000, 47, 1, 0),
234 PLL_RATE(1152000000, 48, 1, 0),
235 PLL_RATE(1176000000, 49, 1, 0),
236 PLL_RATE(1200000000, 50, 1, 0),
237 PLL_RATE(1224000000, 51, 1, 0),
238 PLL_RATE(1248000000, 52, 1, 0),
239 PLL_RATE(1272000000, 53, 1, 0),
240 PLL_RATE(1296000000, 54, 1, 0),
241 PLL_RATE(1320000000, 55, 1, 0),
242 PLL_RATE(1344000000, 56, 1, 0),
243 PLL_RATE(1368000000, 57, 1, 0),
244 PLL_RATE(1392000000, 58, 1, 0),
245 PLL_RATE(1416000000, 59, 1, 0),
246 PLL_RATE(1440000000, 60, 1, 0),
247 PLL_RATE(1464000000, 61, 1, 0),
248 PLL_RATE(1488000000, 62, 1, 0),
249 { /* sentinel */ },
250};
251
252static const struct pll_rate_table gxl_gp0_pll_rate_table[] = {
253 PLL_RATE(504000000, 42, 1, 1),
254 PLL_RATE(516000000, 43, 1, 1),
255 PLL_RATE(528000000, 44, 1, 1),
256 PLL_RATE(540000000, 45, 1, 1),
257 PLL_RATE(552000000, 46, 1, 1),
258 PLL_RATE(564000000, 47, 1, 1),
259 PLL_RATE(576000000, 48, 1, 1),
260 PLL_RATE(588000000, 49, 1, 1),
261 PLL_RATE(600000000, 50, 1, 1),
262 PLL_RATE(612000000, 51, 1, 1),
263 PLL_RATE(624000000, 52, 1, 1),
264 PLL_RATE(636000000, 53, 1, 1),
265 PLL_RATE(648000000, 54, 1, 1),
266 PLL_RATE(660000000, 55, 1, 1),
267 PLL_RATE(672000000, 56, 1, 1),
268 PLL_RATE(684000000, 57, 1, 1),
269 PLL_RATE(696000000, 58, 1, 1),
270 PLL_RATE(708000000, 59, 1, 1),
271 PLL_RATE(720000000, 60, 1, 1),
272 PLL_RATE(732000000, 61, 1, 1),
273 PLL_RATE(744000000, 62, 1, 1),
274 PLL_RATE(756000000, 63, 1, 1),
275 PLL_RATE(768000000, 64, 1, 1),
276 PLL_RATE(780000000, 65, 1, 1),
277 PLL_RATE(792000000, 66, 1, 1),
278 { /* sentinel */ },
279};
280
281static struct meson_clk_pll gxbb_fixed_pll = {
282 .m = {
283 .reg_off = HHI_MPLL_CNTL,
284 .shift = 0,
285 .width = 9,
286 },
287 .n = {
288 .reg_off = HHI_MPLL_CNTL,
289 .shift = 9,
290 .width = 5,
291 },
292 .od = {
293 .reg_off = HHI_MPLL_CNTL,
294 .shift = 16,
295 .width = 2,
296 },
297 .lock = &clk_lock,
298 .hw.init = &(struct clk_init_data){
299 .name = "fixed_pll",
300 .ops = &meson_clk_pll_ro_ops,
301 .parent_names = (const char *[]){ "xtal" },
302 .num_parents = 1,
303 .flags = CLK_GET_RATE_NOCACHE,
304 },
305};
306
307static struct meson_clk_pll gxbb_hdmi_pll = {
308 .m = {
309 .reg_off = HHI_HDMI_PLL_CNTL,
310 .shift = 0,
311 .width = 9,
312 },
313 .n = {
314 .reg_off = HHI_HDMI_PLL_CNTL,
315 .shift = 9,
316 .width = 5,
317 },
318 .frac = {
319 .reg_off = HHI_HDMI_PLL_CNTL2,
320 .shift = 0,
321 .width = 12,
322 },
323 .od = {
324 .reg_off = HHI_HDMI_PLL_CNTL2,
325 .shift = 16,
326 .width = 2,
327 },
328 .od2 = {
329 .reg_off = HHI_HDMI_PLL_CNTL2,
330 .shift = 22,
331 .width = 2,
332 },
333 .lock = &clk_lock,
334 .hw.init = &(struct clk_init_data){
335 .name = "hdmi_pll",
336 .ops = &meson_clk_pll_ro_ops,
337 .parent_names = (const char *[]){ "xtal" },
338 .num_parents = 1,
339 .flags = CLK_GET_RATE_NOCACHE,
340 },
341};
342
343static struct meson_clk_pll gxbb_sys_pll = {
344 .m = {
345 .reg_off = HHI_SYS_PLL_CNTL,
346 .shift = 0,
347 .width = 9,
348 },
349 .n = {
350 .reg_off = HHI_SYS_PLL_CNTL,
351 .shift = 9,
352 .width = 5,
353 },
354 .od = {
355 .reg_off = HHI_SYS_PLL_CNTL,
356 .shift = 10,
357 .width = 2,
358 },
359 .rate_table = sys_pll_rate_table,
360 .rate_count = ARRAY_SIZE(sys_pll_rate_table),
361 .lock = &clk_lock,
362 .hw.init = &(struct clk_init_data){
363 .name = "sys_pll",
364 .ops = &meson_clk_pll_ro_ops,
365 .parent_names = (const char *[]){ "xtal" },
366 .num_parents = 1,
367 .flags = CLK_GET_RATE_NOCACHE,
368 },
369};
370
371struct pll_params_table gxbb_gp0_params_table[] = {
372 PLL_PARAM(HHI_GP0_PLL_CNTL, 0x6a000228),
373 PLL_PARAM(HHI_GP0_PLL_CNTL2, 0x69c80000),
374 PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a5590c4),
375 PLL_PARAM(HHI_GP0_PLL_CNTL4, 0x0000500d),
376};
377
378static struct meson_clk_pll gxbb_gp0_pll = {
379 .m = {
380 .reg_off = HHI_GP0_PLL_CNTL,
381 .shift = 0,
382 .width = 9,
383 },
384 .n = {
385 .reg_off = HHI_GP0_PLL_CNTL,
386 .shift = 9,
387 .width = 5,
388 },
389 .od = {
390 .reg_off = HHI_GP0_PLL_CNTL,
391 .shift = 16,
392 .width = 2,
393 },
394 .params = {
395 .params_table = gxbb_gp0_params_table,
396 .params_count = ARRAY_SIZE(gxbb_gp0_params_table),
397 .no_init_reset = true,
398 .clear_reset_for_lock = true,
399 },
400 .rate_table = gxbb_gp0_pll_rate_table,
401 .rate_count = ARRAY_SIZE(gxbb_gp0_pll_rate_table),
402 .lock = &clk_lock,
403 .hw.init = &(struct clk_init_data){
404 .name = "gp0_pll",
405 .ops = &meson_clk_pll_ops,
406 .parent_names = (const char *[]){ "xtal" },
407 .num_parents = 1,
408 .flags = CLK_GET_RATE_NOCACHE,
409 },
410};
411
412struct pll_params_table gxl_gp0_params_table[] = {
413 PLL_PARAM(HHI_GP0_PLL_CNTL, 0x40010250),
414 PLL_PARAM(HHI_GP0_PLL_CNTL1, 0xc084a000),
415 PLL_PARAM(HHI_GP0_PLL_CNTL2, 0xb75020be),
416 PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a59a288),
417 PLL_PARAM(HHI_GP0_PLL_CNTL4, 0xc000004d),
418 PLL_PARAM(HHI_GP0_PLL_CNTL5, 0x00078000),
419};
420
421static struct meson_clk_pll gxl_gp0_pll = {
422 .m = {
423 .reg_off = HHI_GP0_PLL_CNTL,
424 .shift = 0,
425 .width = 9,
426 },
427 .n = {
428 .reg_off = HHI_GP0_PLL_CNTL,
429 .shift = 9,
430 .width = 5,
431 },
432 .od = {
433 .reg_off = HHI_GP0_PLL_CNTL,
434 .shift = 16,
435 .width = 2,
436 },
437 .params = {
438 .params_table = gxl_gp0_params_table,
439 .params_count = ARRAY_SIZE(gxl_gp0_params_table),
440 .no_init_reset = true,
441 .reset_lock_loop = true,
442 },
443 .rate_table = gxl_gp0_pll_rate_table,
444 .rate_count = ARRAY_SIZE(gxl_gp0_pll_rate_table),
445 .lock = &clk_lock,
446 .hw.init = &(struct clk_init_data){
447 .name = "gp0_pll",
448 .ops = &meson_clk_pll_ops,
449 .parent_names = (const char *[]){ "xtal" },
450 .num_parents = 1,
451 .flags = CLK_GET_RATE_NOCACHE,
452 },
453};
454
455static struct clk_fixed_factor gxbb_fclk_div2 = {
456 .mult = 1,
457 .div = 2,
458 .hw.init = &(struct clk_init_data){
459 .name = "fclk_div2",
460 .ops = &clk_fixed_factor_ops,
461 .parent_names = (const char *[]){ "fixed_pll" },
462 .num_parents = 1,
463 },
464};
465
466static struct clk_fixed_factor gxbb_fclk_div3 = {
467 .mult = 1,
468 .div = 3,
469 .hw.init = &(struct clk_init_data){
470 .name = "fclk_div3",
471 .ops = &clk_fixed_factor_ops,
472 .parent_names = (const char *[]){ "fixed_pll" },
473 .num_parents = 1,
474 },
475};
476
477static struct clk_fixed_factor gxbb_fclk_div4 = {
478 .mult = 1,
479 .div = 4,
480 .hw.init = &(struct clk_init_data){
481 .name = "fclk_div4",
482 .ops = &clk_fixed_factor_ops,
483 .parent_names = (const char *[]){ "fixed_pll" },
484 .num_parents = 1,
485 },
486};
487
488static struct clk_fixed_factor gxbb_fclk_div5 = {
489 .mult = 1,
490 .div = 5,
491 .hw.init = &(struct clk_init_data){
492 .name = "fclk_div5",
493 .ops = &clk_fixed_factor_ops,
494 .parent_names = (const char *[]){ "fixed_pll" },
495 .num_parents = 1,
496 },
497};
498
499static struct clk_fixed_factor gxbb_fclk_div7 = {
500 .mult = 1,
501 .div = 7,
502 .hw.init = &(struct clk_init_data){
503 .name = "fclk_div7",
504 .ops = &clk_fixed_factor_ops,
505 .parent_names = (const char *[]){ "fixed_pll" },
506 .num_parents = 1,
507 },
508};
509
510static struct meson_clk_mpll gxbb_mpll0 = {
511 .sdm = {
512 .reg_off = HHI_MPLL_CNTL7,
513 .shift = 0,
514 .width = 14,
515 },
516 .sdm_en = {
517 .reg_off = HHI_MPLL_CNTL7,
518 .shift = 15,
519 .width = 1,
520 },
521 .n2 = {
522 .reg_off = HHI_MPLL_CNTL7,
523 .shift = 16,
524 .width = 9,
525 },
526 .en = {
527 .reg_off = HHI_MPLL_CNTL7,
528 .shift = 14,
529 .width = 1,
530 },
531 .ssen = {
532 .reg_off = HHI_MPLL_CNTL,
533 .shift = 25,
534 .width = 1,
535 },
536 .lock = &clk_lock,
537 .hw.init = &(struct clk_init_data){
538 .name = "mpll0",
539 .ops = &meson_clk_mpll_ops,
540 .parent_names = (const char *[]){ "fixed_pll" },
541 .num_parents = 1,
542 },
543};
544
545static struct meson_clk_mpll gxbb_mpll1 = {
546 .sdm = {
547 .reg_off = HHI_MPLL_CNTL8,
548 .shift = 0,
549 .width = 14,
550 },
551 .sdm_en = {
552 .reg_off = HHI_MPLL_CNTL8,
553 .shift = 15,
554 .width = 1,
555 },
556 .n2 = {
557 .reg_off = HHI_MPLL_CNTL8,
558 .shift = 16,
559 .width = 9,
560 },
561 .en = {
562 .reg_off = HHI_MPLL_CNTL8,
563 .shift = 14,
564 .width = 1,
565 },
566 .lock = &clk_lock,
567 .hw.init = &(struct clk_init_data){
568 .name = "mpll1",
569 .ops = &meson_clk_mpll_ops,
570 .parent_names = (const char *[]){ "fixed_pll" },
571 .num_parents = 1,
572 },
573};
574
575static struct meson_clk_mpll gxbb_mpll2 = {
576 .sdm = {
577 .reg_off = HHI_MPLL_CNTL9,
578 .shift = 0,
579 .width = 14,
580 },
581 .sdm_en = {
582 .reg_off = HHI_MPLL_CNTL9,
583 .shift = 15,
584 .width = 1,
585 },
586 .n2 = {
587 .reg_off = HHI_MPLL_CNTL9,
588 .shift = 16,
589 .width = 9,
590 },
591 .en = {
592 .reg_off = HHI_MPLL_CNTL9,
593 .shift = 14,
594 .width = 1,
595 },
596 .lock = &clk_lock,
597 .hw.init = &(struct clk_init_data){
598 .name = "mpll2",
599 .ops = &meson_clk_mpll_ops,
600 .parent_names = (const char *[]){ "fixed_pll" },
601 .num_parents = 1,
602 },
603};
604
605/*
606 * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers
607 * and should be modeled with their respective PLLs via the forthcoming
608 * coordinated clock rates feature
609 */
610
611static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
612static const char * const clk81_parent_names[] = {
613 "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
614 "fclk_div3", "fclk_div5"
615};
616
617static struct clk_mux gxbb_mpeg_clk_sel = {
618 .reg = (void *)HHI_MPEG_CLK_CNTL,
619 .mask = 0x7,
620 .shift = 12,
621 .flags = CLK_MUX_READ_ONLY,
622 .table = mux_table_clk81,
623 .lock = &clk_lock,
624 .hw.init = &(struct clk_init_data){
625 .name = "mpeg_clk_sel",
626 .ops = &clk_mux_ro_ops,
627 /*
628 * bits 14:12 selects from 8 possible parents:
629 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
630 * fclk_div4, fclk_div3, fclk_div5
631 */
632 .parent_names = clk81_parent_names,
633 .num_parents = ARRAY_SIZE(clk81_parent_names),
634 .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
635 },
636};
637
638static struct clk_divider gxbb_mpeg_clk_div = {
639 .reg = (void *)HHI_MPEG_CLK_CNTL,
640 .shift = 0,
641 .width = 7,
642 .lock = &clk_lock,
643 .hw.init = &(struct clk_init_data){
644 .name = "mpeg_clk_div",
645 .ops = &clk_divider_ops,
646 .parent_names = (const char *[]){ "mpeg_clk_sel" },
647 .num_parents = 1,
648 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
649 },
650};
651
652/* the mother of dragons^W gates */
653static struct clk_gate gxbb_clk81 = {
654 .reg = (void *)HHI_MPEG_CLK_CNTL,
655 .bit_idx = 7,
656 .lock = &clk_lock,
657 .hw.init = &(struct clk_init_data){
658 .name = "clk81",
659 .ops = &clk_gate_ops,
660 .parent_names = (const char *[]){ "mpeg_clk_div" },
661 .num_parents = 1,
662 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
663 },
664};
665
666static struct clk_mux gxbb_sar_adc_clk_sel = {
667 .reg = (void *)HHI_SAR_CLK_CNTL,
668 .mask = 0x3,
669 .shift = 9,
670 .lock = &clk_lock,
671 .hw.init = &(struct clk_init_data){
672 .name = "sar_adc_clk_sel",
673 .ops = &clk_mux_ops,
674 /* NOTE: The datasheet doesn't list the parents for bit 10 */
675 .parent_names = (const char *[]){ "xtal", "clk81", },
676 .num_parents = 2,
677 },
678};
679
680static struct clk_divider gxbb_sar_adc_clk_div = {
681 .reg = (void *)HHI_SAR_CLK_CNTL,
682 .shift = 0,
683 .width = 8,
684 .lock = &clk_lock,
685 .hw.init = &(struct clk_init_data){
686 .name = "sar_adc_clk_div",
687 .ops = &clk_divider_ops,
688 .parent_names = (const char *[]){ "sar_adc_clk_sel" },
689 .num_parents = 1,
690 .flags = CLK_SET_RATE_PARENT,
691 },
692};
693
694static struct clk_gate gxbb_sar_adc_clk = {
695 .reg = (void *)HHI_SAR_CLK_CNTL,
696 .bit_idx = 8,
697 .lock = &clk_lock,
698 .hw.init = &(struct clk_init_data){
699 .name = "sar_adc_clk",
700 .ops = &clk_gate_ops,
701 .parent_names = (const char *[]){ "sar_adc_clk_div" },
702 .num_parents = 1,
703 .flags = CLK_SET_RATE_PARENT,
704 },
705};
706
707/*
708 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
709 * muxed by a glitch-free switch.
710 */
711
712static u32 mux_table_mali_0_1[] = {0, 1, 2, 3, 4, 5, 6, 7};
713static const char * const gxbb_mali_0_1_parent_names[] = {
714 "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
715 "fclk_div4", "fclk_div3", "fclk_div5"
716};
717
718static struct clk_mux gxbb_mali_0_sel = {
719 .reg = (void *)HHI_MALI_CLK_CNTL,
720 .mask = 0x7,
721 .shift = 9,
722 .table = mux_table_mali_0_1,
723 .lock = &clk_lock,
724 .hw.init = &(struct clk_init_data){
725 .name = "mali_0_sel",
726 .ops = &clk_mux_ops,
727 /*
728 * bits 10:9 selects from 8 possible parents:
729 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
730 * fclk_div4, fclk_div3, fclk_div5
731 */
732 .parent_names = gxbb_mali_0_1_parent_names,
733 .num_parents = 8,
734 .flags = CLK_SET_RATE_NO_REPARENT,
735 },
736};
737
738static struct clk_divider gxbb_mali_0_div = {
739 .reg = (void *)HHI_MALI_CLK_CNTL,
740 .shift = 0,
741 .width = 7,
742 .lock = &clk_lock,
743 .hw.init = &(struct clk_init_data){
744 .name = "mali_0_div",
745 .ops = &clk_divider_ops,
746 .parent_names = (const char *[]){ "mali_0_sel" },
747 .num_parents = 1,
748 .flags = CLK_SET_RATE_NO_REPARENT,
749 },
750};
751
752static struct clk_gate gxbb_mali_0 = {
753 .reg = (void *)HHI_MALI_CLK_CNTL,
754 .bit_idx = 8,
755 .lock = &clk_lock,
756 .hw.init = &(struct clk_init_data){
757 .name = "mali_0",
758 .ops = &clk_gate_ops,
759 .parent_names = (const char *[]){ "mali_0_div" },
760 .num_parents = 1,
761 .flags = CLK_SET_RATE_PARENT,
762 },
763};
764
765static struct clk_mux gxbb_mali_1_sel = {
766 .reg = (void *)HHI_MALI_CLK_CNTL,
767 .mask = 0x7,
768 .shift = 25,
769 .table = mux_table_mali_0_1,
770 .lock = &clk_lock,
771 .hw.init = &(struct clk_init_data){
772 .name = "mali_1_sel",
773 .ops = &clk_mux_ops,
774 /*
775 * bits 10:9 selects from 8 possible parents:
776 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
777 * fclk_div4, fclk_div3, fclk_div5
778 */
779 .parent_names = gxbb_mali_0_1_parent_names,
780 .num_parents = 8,
781 .flags = CLK_SET_RATE_NO_REPARENT,
782 },
783};
784
785static struct clk_divider gxbb_mali_1_div = {
786 .reg = (void *)HHI_MALI_CLK_CNTL,
787 .shift = 16,
788 .width = 7,
789 .lock = &clk_lock,
790 .hw.init = &(struct clk_init_data){
791 .name = "mali_1_div",
792 .ops = &clk_divider_ops,
793 .parent_names = (const char *[]){ "mali_1_sel" },
794 .num_parents = 1,
795 .flags = CLK_SET_RATE_NO_REPARENT,
796 },
797};
798
799static struct clk_gate gxbb_mali_1 = {
800 .reg = (void *)HHI_MALI_CLK_CNTL,
801 .bit_idx = 24,
802 .lock = &clk_lock,
803 .hw.init = &(struct clk_init_data){
804 .name = "mali_1",
805 .ops = &clk_gate_ops,
806 .parent_names = (const char *[]){ "mali_1_div" },
807 .num_parents = 1,
808 .flags = CLK_SET_RATE_PARENT,
809 },
810};
811
812static u32 mux_table_mali[] = {0, 1};
813static const char * const gxbb_mali_parent_names[] = {
814 "mali_0", "mali_1"
815};
816
817static struct clk_mux gxbb_mali = {
818 .reg = (void *)HHI_MALI_CLK_CNTL,
819 .mask = 1,
820 .shift = 31,
821 .table = mux_table_mali,
822 .lock = &clk_lock,
823 .hw.init = &(struct clk_init_data){
824 .name = "mali",
825 .ops = &clk_mux_ops,
826 .parent_names = gxbb_mali_parent_names,
827 .num_parents = 2,
828 .flags = CLK_SET_RATE_NO_REPARENT,
829 },
830};
831
832static struct clk_mux gxbb_cts_amclk_sel = {
833 .reg = (void *) HHI_AUD_CLK_CNTL,
834 .mask = 0x3,
835 .shift = 9,
836 /* Default parent unknown (register reset value: 0) */
837 .table = (u32[]){ 1, 2, 3 },
838 .lock = &clk_lock,
839 .hw.init = &(struct clk_init_data){
840 .name = "cts_amclk_sel",
841 .ops = &clk_mux_ops,
842 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
843 .num_parents = 3,
844 .flags = CLK_SET_RATE_PARENT,
845 },
846};
847
848static struct meson_clk_audio_divider gxbb_cts_amclk_div = {
849 .div = {
850 .reg_off = HHI_AUD_CLK_CNTL,
851 .shift = 0,
852 .width = 8,
853 },
854 .flags = CLK_DIVIDER_ROUND_CLOSEST,
855 .lock = &clk_lock,
856 .hw.init = &(struct clk_init_data){
857 .name = "cts_amclk_div",
858 .ops = &meson_clk_audio_divider_ops,
859 .parent_names = (const char *[]){ "cts_amclk_sel" },
860 .num_parents = 1,
861 .flags = CLK_SET_RATE_PARENT,
862 },
863};
864
865static struct clk_gate gxbb_cts_amclk = {
866 .reg = (void *) HHI_AUD_CLK_CNTL,
867 .bit_idx = 8,
868 .lock = &clk_lock,
869 .hw.init = &(struct clk_init_data){
870 .name = "cts_amclk",
871 .ops = &clk_gate_ops,
872 .parent_names = (const char *[]){ "cts_amclk_div" },
873 .num_parents = 1,
874 .flags = CLK_SET_RATE_PARENT,
875 },
876};
877
878static struct clk_mux gxbb_cts_mclk_i958_sel = {
879 .reg = (void *)HHI_AUD_CLK_CNTL2,
880 .mask = 0x3,
881 .shift = 25,
882 /* Default parent unknown (register reset value: 0) */
883 .table = (u32[]){ 1, 2, 3 },
884 .lock = &clk_lock,
885 .hw.init = &(struct clk_init_data) {
886 .name = "cts_mclk_i958_sel",
887 .ops = &clk_mux_ops,
888 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
889 .num_parents = 3,
890 .flags = CLK_SET_RATE_PARENT,
891 },
892};
893
894static struct clk_divider gxbb_cts_mclk_i958_div = {
895 .reg = (void *)HHI_AUD_CLK_CNTL2,
896 .shift = 16,
897 .width = 8,
898 .lock = &clk_lock,
899 .flags = CLK_DIVIDER_ROUND_CLOSEST,
900 .hw.init = &(struct clk_init_data) {
901 .name = "cts_mclk_i958_div",
902 .ops = &clk_divider_ops,
903 .parent_names = (const char *[]){ "cts_mclk_i958_sel" },
904 .num_parents = 1,
905 .flags = CLK_SET_RATE_PARENT,
906 },
907};
908
909static struct clk_gate gxbb_cts_mclk_i958 = {
910 .reg = (void *)HHI_AUD_CLK_CNTL2,
911 .bit_idx = 24,
912 .lock = &clk_lock,
913 .hw.init = &(struct clk_init_data){
914 .name = "cts_mclk_i958",
915 .ops = &clk_gate_ops,
916 .parent_names = (const char *[]){ "cts_mclk_i958_div" },
917 .num_parents = 1,
918 .flags = CLK_SET_RATE_PARENT,
919 },
920};
921
922static struct clk_mux gxbb_cts_i958 = {
923 .reg = (void *)HHI_AUD_CLK_CNTL2,
924 .mask = 0x1,
925 .shift = 27,
926 .lock = &clk_lock,
927 .hw.init = &(struct clk_init_data){
928 .name = "cts_i958",
929 .ops = &clk_mux_ops,
930 .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" },
931 .num_parents = 2,
932 /*
933 *The parent is specific to origin of the audio data. Let the
934 * consumer choose the appropriate parent
935 */
936 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
937 },
938};
939
940static struct clk_divider gxbb_32k_clk_div = {
941 .reg = (void *)HHI_32K_CLK_CNTL,
942 .shift = 0,
943 .width = 14,
944 .lock = &clk_lock,
945 .hw.init = &(struct clk_init_data){
946 .name = "32k_clk_div",
947 .ops = &clk_divider_ops,
948 .parent_names = (const char *[]){ "32k_clk_sel" },
949 .num_parents = 1,
950 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
951 },
952};
953
954static struct clk_gate gxbb_32k_clk = {
955 .reg = (void *)HHI_32K_CLK_CNTL,
956 .bit_idx = 15,
957 .lock = &clk_lock,
958 .hw.init = &(struct clk_init_data){
959 .name = "32k_clk",
960 .ops = &clk_gate_ops,
961 .parent_names = (const char *[]){ "32k_clk_div" },
962 .num_parents = 1,
963 .flags = CLK_SET_RATE_PARENT,
964 },
965};
966
967static const char * const gxbb_32k_clk_parent_names[] = {
968 "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
969};
970
971static struct clk_mux gxbb_32k_clk_sel = {
972 .reg = (void *)HHI_32K_CLK_CNTL,
973 .mask = 0x3,
974 .shift = 16,
975 .lock = &clk_lock,
976 .hw.init = &(struct clk_init_data){
977 .name = "32k_clk_sel",
978 .ops = &clk_mux_ops,
979 .parent_names = gxbb_32k_clk_parent_names,
980 .num_parents = 4,
981 .flags = CLK_SET_RATE_PARENT,
982 },
983};
984
985static const char * const gxbb_sd_emmc_clk0_parent_names[] = {
986 "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
987
988 /*
989 * Following these parent clocks, we should also have had mpll2, mpll3
990 * and gp0_pll but these clocks are too precious to be used here. All
991 * the necessary rates for MMC and NAND operation can be acheived using
992 * xtal or fclk_div clocks
993 */
994};
995
996/* SDIO clock */
997static struct clk_mux gxbb_sd_emmc_a_clk0_sel = {
998 .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
999 .mask = 0x7,
1000 .shift = 9,
1001 .lock = &clk_lock,
1002 .hw.init = &(struct clk_init_data) {
1003 .name = "sd_emmc_a_clk0_sel",
1004 .ops = &clk_mux_ops,
1005 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1006 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1007 .flags = CLK_SET_RATE_PARENT,
1008 },
1009};
1010
1011static struct clk_divider gxbb_sd_emmc_a_clk0_div = {
1012 .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
1013 .shift = 0,
1014 .width = 7,
1015 .lock = &clk_lock,
1016 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1017 .hw.init = &(struct clk_init_data) {
1018 .name = "sd_emmc_a_clk0_div",
1019 .ops = &clk_divider_ops,
1020 .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },
1021 .num_parents = 1,
1022 .flags = CLK_SET_RATE_PARENT,
1023 },
1024};
1025
1026static struct clk_gate gxbb_sd_emmc_a_clk0 = {
1027 .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
1028 .bit_idx = 7,
1029 .lock = &clk_lock,
1030 .hw.init = &(struct clk_init_data){
1031 .name = "sd_emmc_a_clk0",
1032 .ops = &clk_gate_ops,
1033 .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },
1034 .num_parents = 1,
1035
1036 /*
1037 * FIXME:
1038 * We need CLK_IGNORE_UNUSED because mmc DT node point to xtal
1039 * instead of this clock. CCF would gate this on boot, killing
1040 * the mmc controller. Please remove this flag once DT properly
1041 * point to this clock instead of xtal
1042 *
1043 * Same goes for emmc B and C clocks
1044 */
1045 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1046 },
1047};
1048
1049/* SDcard clock */
1050static struct clk_mux gxbb_sd_emmc_b_clk0_sel = {
1051 .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
1052 .mask = 0x7,
1053 .shift = 25,
1054 .lock = &clk_lock,
1055 .hw.init = &(struct clk_init_data) {
1056 .name = "sd_emmc_b_clk0_sel",
1057 .ops = &clk_mux_ops,
1058 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1059 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1060 .flags = CLK_SET_RATE_PARENT,
1061 },
1062};
1063
1064static struct clk_divider gxbb_sd_emmc_b_clk0_div = {
1065 .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
1066 .shift = 16,
1067 .width = 7,
1068 .lock = &clk_lock,
1069 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1070 .hw.init = &(struct clk_init_data) {
1071 .name = "sd_emmc_b_clk0_div",
1072 .ops = &clk_divider_ops,
1073 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
1074 .num_parents = 1,
1075 .flags = CLK_SET_RATE_PARENT,
1076 },
1077};
1078
1079static struct clk_gate gxbb_sd_emmc_b_clk0 = {
1080 .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
1081 .bit_idx = 23,
1082 .lock = &clk_lock,
1083 .hw.init = &(struct clk_init_data){
1084 .name = "sd_emmc_b_clk0",
1085 .ops = &clk_gate_ops,
1086 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
1087 .num_parents = 1,
1088 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1089 },
1090};
1091
1092/* EMMC/NAND clock */
1093static struct clk_mux gxbb_sd_emmc_c_clk0_sel = {
1094 .reg = (void *)HHI_NAND_CLK_CNTL,
1095 .mask = 0x7,
1096 .shift = 9,
1097 .lock = &clk_lock,
1098 .hw.init = &(struct clk_init_data) {
1099 .name = "sd_emmc_c_clk0_sel",
1100 .ops = &clk_mux_ops,
1101 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1102 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1103 .flags = CLK_SET_RATE_PARENT,
1104 },
1105};
1106
1107static struct clk_divider gxbb_sd_emmc_c_clk0_div = {
1108 .reg = (void *)HHI_NAND_CLK_CNTL,
1109 .shift = 0,
1110 .width = 7,
1111 .lock = &clk_lock,
1112 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1113 .hw.init = &(struct clk_init_data) {
1114 .name = "sd_emmc_c_clk0_div",
1115 .ops = &clk_divider_ops,
1116 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
1117 .num_parents = 1,
1118 .flags = CLK_SET_RATE_PARENT,
1119 },
1120};
1121
1122static struct clk_gate gxbb_sd_emmc_c_clk0 = {
1123 .reg = (void *)HHI_NAND_CLK_CNTL,
1124 .bit_idx = 7,
1125 .lock = &clk_lock,
1126 .hw.init = &(struct clk_init_data){
1127 .name = "sd_emmc_c_clk0",
1128 .ops = &clk_gate_ops,
1129 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
1130 .num_parents = 1,
1131 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1132 },
1133};
1134
1135/* Everything Else (EE) domain gates */
1136static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
1137static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
1138static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
1139static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
1140static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
1141static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
1142static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
1143static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);
1144static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
1145static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
1146static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
1147static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
1148static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
1149static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
1150static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
1151static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
1152static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
1153static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
1154static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
1155static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
1156static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
1157static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
1158
1159static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
1160static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
1161static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
1162static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);
1163static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);
1164static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);
1165static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);
1166static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);
1167static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);
1168static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);
1169static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);
1170static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
1171static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
1172static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
1173static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
1174static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
1175static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
1176static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
1177static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
1178static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
1179static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
1180static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
1181static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
1182static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
1183static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
1184
1185static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
1186static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
1187static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
1188static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
1189static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
1190static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
1191static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
1192static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
1193static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
1194static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
1195static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
1196static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
1197static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
1198
1199static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
1200static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
1201static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
1202static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
1203static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
1204static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
1205static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
1206static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
1207static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
1208static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
1209static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
1210static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
1211static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
1212static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
1213static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
1214static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
1215
1216/* Always On (AO) domain gates */
1217
1218static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
1219static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
1220static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
1221static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
1222static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
1223
1224/* Array of all clocks provided by this provider */
1225
1226static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
1227 .hws = {
1228 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
1229 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
1230 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
1231 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
1232 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
1233 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
1234 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
1235 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
1236 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
1237 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
1238 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
1239 [CLKID_CLK81] = &gxbb_clk81.hw,
1240 [CLKID_MPLL0] = &gxbb_mpll0.hw,
1241 [CLKID_MPLL1] = &gxbb_mpll1.hw,
1242 [CLKID_MPLL2] = &gxbb_mpll2.hw,
1243 [CLKID_DDR] = &gxbb_ddr.hw,
1244 [CLKID_DOS] = &gxbb_dos.hw,
1245 [CLKID_ISA] = &gxbb_isa.hw,
1246 [CLKID_PL301] = &gxbb_pl301.hw,
1247 [CLKID_PERIPHS] = &gxbb_periphs.hw,
1248 [CLKID_SPICC] = &gxbb_spicc.hw,
1249 [CLKID_I2C] = &gxbb_i2c.hw,
1250 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
1251 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
1252 [CLKID_RNG0] = &gxbb_rng0.hw,
1253 [CLKID_UART0] = &gxbb_uart0.hw,
1254 [CLKID_SDHC] = &gxbb_sdhc.hw,
1255 [CLKID_STREAM] = &gxbb_stream.hw,
1256 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
1257 [CLKID_SDIO] = &gxbb_sdio.hw,
1258 [CLKID_ABUF] = &gxbb_abuf.hw,
1259 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
1260 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
1261 [CLKID_SPI] = &gxbb_spi.hw,
1262 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
1263 [CLKID_ETH] = &gxbb_eth.hw,
1264 [CLKID_DEMUX] = &gxbb_demux.hw,
1265 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
1266 [CLKID_IEC958] = &gxbb_iec958.hw,
1267 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
1268 [CLKID_AMCLK] = &gxbb_amclk.hw,
1269 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
1270 [CLKID_MIXER] = &gxbb_mixer.hw,
1271 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
1272 [CLKID_ADC] = &gxbb_adc.hw,
1273 [CLKID_BLKMV] = &gxbb_blkmv.hw,
1274 [CLKID_AIU] = &gxbb_aiu.hw,
1275 [CLKID_UART1] = &gxbb_uart1.hw,
1276 [CLKID_G2D] = &gxbb_g2d.hw,
1277 [CLKID_USB0] = &gxbb_usb0.hw,
1278 [CLKID_USB1] = &gxbb_usb1.hw,
1279 [CLKID_RESET] = &gxbb_reset.hw,
1280 [CLKID_NAND] = &gxbb_nand.hw,
1281 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
1282 [CLKID_USB] = &gxbb_usb.hw,
1283 [CLKID_VDIN1] = &gxbb_vdin1.hw,
1284 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
1285 [CLKID_EFUSE] = &gxbb_efuse.hw,
1286 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
1287 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
1288 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
1289 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
1290 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
1291 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
1292 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
1293 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
1294 [CLKID_DVIN] = &gxbb_dvin.hw,
1295 [CLKID_UART2] = &gxbb_uart2.hw,
1296 [CLKID_SANA] = &gxbb_sana.hw,
1297 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
1298 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
1299 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
1300 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
1301 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
1302 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
1303 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
1304 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
1305 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
1306 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
1307 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
1308 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
1309 [CLKID_ENC480P] = &gxbb_enc480p.hw,
1310 [CLKID_RNG1] = &gxbb_rng1.hw,
1311 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
1312 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
1313 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
1314 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
1315 [CLKID_EDP] = &gxbb_edp.hw,
1316 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
1317 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
1318 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
1319 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
1320 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
1321 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
1322 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
1323 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
1324 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
1325 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
1326 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
1327 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
1328 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
1329 [CLKID_MALI_0] = &gxbb_mali_0.hw,
1330 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
1331 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
1332 [CLKID_MALI_1] = &gxbb_mali_1.hw,
1333 [CLKID_MALI] = &gxbb_mali.hw,
1334 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
1335 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
1336 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
1337 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
1338 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
1339 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
1340 [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
1341 [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
1342 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
1343 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
1344 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
1345 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
1346 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
1347 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
1348 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
1349 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
1350 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
1351 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
1352 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
1353 [NR_CLKS] = NULL,
1354 },
1355 .num = NR_CLKS,
1356};
1357
1358static struct clk_hw_onecell_data gxl_hw_onecell_data = {
1359 .hws = {
1360 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
1361 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
1362 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
1363 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
1364 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
1365 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
1366 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
1367 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
1368 [CLKID_GP0_PLL] = &gxl_gp0_pll.hw,
1369 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
1370 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
1371 [CLKID_CLK81] = &gxbb_clk81.hw,
1372 [CLKID_MPLL0] = &gxbb_mpll0.hw,
1373 [CLKID_MPLL1] = &gxbb_mpll1.hw,
1374 [CLKID_MPLL2] = &gxbb_mpll2.hw,
1375 [CLKID_DDR] = &gxbb_ddr.hw,
1376 [CLKID_DOS] = &gxbb_dos.hw,
1377 [CLKID_ISA] = &gxbb_isa.hw,
1378 [CLKID_PL301] = &gxbb_pl301.hw,
1379 [CLKID_PERIPHS] = &gxbb_periphs.hw,
1380 [CLKID_SPICC] = &gxbb_spicc.hw,
1381 [CLKID_I2C] = &gxbb_i2c.hw,
1382 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
1383 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
1384 [CLKID_RNG0] = &gxbb_rng0.hw,
1385 [CLKID_UART0] = &gxbb_uart0.hw,
1386 [CLKID_SDHC] = &gxbb_sdhc.hw,
1387 [CLKID_STREAM] = &gxbb_stream.hw,
1388 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
1389 [CLKID_SDIO] = &gxbb_sdio.hw,
1390 [CLKID_ABUF] = &gxbb_abuf.hw,
1391 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
1392 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
1393 [CLKID_SPI] = &gxbb_spi.hw,
1394 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
1395 [CLKID_ETH] = &gxbb_eth.hw,
1396 [CLKID_DEMUX] = &gxbb_demux.hw,
1397 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
1398 [CLKID_IEC958] = &gxbb_iec958.hw,
1399 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
1400 [CLKID_AMCLK] = &gxbb_amclk.hw,
1401 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
1402 [CLKID_MIXER] = &gxbb_mixer.hw,
1403 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
1404 [CLKID_ADC] = &gxbb_adc.hw,
1405 [CLKID_BLKMV] = &gxbb_blkmv.hw,
1406 [CLKID_AIU] = &gxbb_aiu.hw,
1407 [CLKID_UART1] = &gxbb_uart1.hw,
1408 [CLKID_G2D] = &gxbb_g2d.hw,
1409 [CLKID_USB0] = &gxbb_usb0.hw,
1410 [CLKID_USB1] = &gxbb_usb1.hw,
1411 [CLKID_RESET] = &gxbb_reset.hw,
1412 [CLKID_NAND] = &gxbb_nand.hw,
1413 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
1414 [CLKID_USB] = &gxbb_usb.hw,
1415 [CLKID_VDIN1] = &gxbb_vdin1.hw,
1416 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
1417 [CLKID_EFUSE] = &gxbb_efuse.hw,
1418 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
1419 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
1420 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
1421 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
1422 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
1423 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
1424 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
1425 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
1426 [CLKID_DVIN] = &gxbb_dvin.hw,
1427 [CLKID_UART2] = &gxbb_uart2.hw,
1428 [CLKID_SANA] = &gxbb_sana.hw,
1429 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
1430 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
1431 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
1432 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
1433 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
1434 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
1435 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
1436 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
1437 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
1438 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
1439 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
1440 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
1441 [CLKID_ENC480P] = &gxbb_enc480p.hw,
1442 [CLKID_RNG1] = &gxbb_rng1.hw,
1443 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
1444 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
1445 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
1446 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
1447 [CLKID_EDP] = &gxbb_edp.hw,
1448 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
1449 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
1450 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
1451 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
1452 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
1453 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
1454 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
1455 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
1456 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
1457 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
1458 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
1459 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
1460 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
1461 [CLKID_MALI_0] = &gxbb_mali_0.hw,
1462 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
1463 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
1464 [CLKID_MALI_1] = &gxbb_mali_1.hw,
1465 [CLKID_MALI] = &gxbb_mali.hw,
1466 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
1467 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
1468 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
1469 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
1470 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
1471 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
1472 [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
1473 [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
1474 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
1475 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
1476 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
1477 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
1478 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
1479 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
1480 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
1481 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
1482 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
1483 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
1484 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
1485 [NR_CLKS] = NULL,
1486 },
1487 .num = NR_CLKS,
1488};
1489
1490/* Convenience tables to populate base addresses in .probe */
1491
1492static struct meson_clk_pll *const gxbb_clk_plls[] = {
1493 &gxbb_fixed_pll,
1494 &gxbb_hdmi_pll,
1495 &gxbb_sys_pll,
1496 &gxbb_gp0_pll,
1497};
1498
1499static struct meson_clk_pll *const gxl_clk_plls[] = {
1500 &gxbb_fixed_pll,
1501 &gxbb_hdmi_pll,
1502 &gxbb_sys_pll,
1503 &gxl_gp0_pll,
1504};
1505
1506static struct meson_clk_mpll *const gxbb_clk_mplls[] = {
1507 &gxbb_mpll0,
1508 &gxbb_mpll1,
1509 &gxbb_mpll2,
1510};
1511
1512static struct clk_gate *const gxbb_clk_gates[] = {
1513 &gxbb_clk81,
1514 &gxbb_ddr,
1515 &gxbb_dos,
1516 &gxbb_isa,
1517 &gxbb_pl301,
1518 &gxbb_periphs,
1519 &gxbb_spicc,
1520 &gxbb_i2c,
1521 &gxbb_sar_adc,
1522 &gxbb_smart_card,
1523 &gxbb_rng0,
1524 &gxbb_uart0,
1525 &gxbb_sdhc,
1526 &gxbb_stream,
1527 &gxbb_async_fifo,
1528 &gxbb_sdio,
1529 &gxbb_abuf,
1530 &gxbb_hiu_iface,
1531 &gxbb_assist_misc,
1532 &gxbb_spi,
1533 &gxbb_i2s_spdif,
1534 &gxbb_eth,
1535 &gxbb_demux,
1536 &gxbb_aiu_glue,
1537 &gxbb_iec958,
1538 &gxbb_i2s_out,
1539 &gxbb_amclk,
1540 &gxbb_aififo2,
1541 &gxbb_mixer,
1542 &gxbb_mixer_iface,
1543 &gxbb_adc,
1544 &gxbb_blkmv,
1545 &gxbb_aiu,
1546 &gxbb_uart1,
1547 &gxbb_g2d,
1548 &gxbb_usb0,
1549 &gxbb_usb1,
1550 &gxbb_reset,
1551 &gxbb_nand,
1552 &gxbb_dos_parser,
1553 &gxbb_usb,
1554 &gxbb_vdin1,
1555 &gxbb_ahb_arb0,
1556 &gxbb_efuse,
1557 &gxbb_boot_rom,
1558 &gxbb_ahb_data_bus,
1559 &gxbb_ahb_ctrl_bus,
1560 &gxbb_hdmi_intr_sync,
1561 &gxbb_hdmi_pclk,
1562 &gxbb_usb1_ddr_bridge,
1563 &gxbb_usb0_ddr_bridge,
1564 &gxbb_mmc_pclk,
1565 &gxbb_dvin,
1566 &gxbb_uart2,
1567 &gxbb_sana,
1568 &gxbb_vpu_intr,
1569 &gxbb_sec_ahb_ahb3_bridge,
1570 &gxbb_clk81_a53,
1571 &gxbb_vclk2_venci0,
1572 &gxbb_vclk2_venci1,
1573 &gxbb_vclk2_vencp0,
1574 &gxbb_vclk2_vencp1,
1575 &gxbb_gclk_venci_int0,
1576 &gxbb_gclk_vencp_int,
1577 &gxbb_dac_clk,
1578 &gxbb_aoclk_gate,
1579 &gxbb_iec958_gate,
1580 &gxbb_enc480p,
1581 &gxbb_rng1,
1582 &gxbb_gclk_venci_int1,
1583 &gxbb_vclk2_venclmcc,
1584 &gxbb_vclk2_vencl,
1585 &gxbb_vclk_other,
1586 &gxbb_edp,
1587 &gxbb_ao_media_cpu,
1588 &gxbb_ao_ahb_sram,
1589 &gxbb_ao_ahb_bus,
1590 &gxbb_ao_iface,
1591 &gxbb_ao_i2c,
1592 &gxbb_emmc_a,
1593 &gxbb_emmc_b,
1594 &gxbb_emmc_c,
1595 &gxbb_sar_adc_clk,
1596 &gxbb_mali_0,
1597 &gxbb_mali_1,
1598 &gxbb_cts_amclk,
1599 &gxbb_cts_mclk_i958,
1600 &gxbb_32k_clk,
1601 &gxbb_sd_emmc_a_clk0,
1602 &gxbb_sd_emmc_b_clk0,
1603 &gxbb_sd_emmc_c_clk0,
1604};
1605
1606static struct clk_mux *const gxbb_clk_muxes[] = {
1607 &gxbb_mpeg_clk_sel,
1608 &gxbb_sar_adc_clk_sel,
1609 &gxbb_mali_0_sel,
1610 &gxbb_mali_1_sel,
1611 &gxbb_mali,
1612 &gxbb_cts_amclk_sel,
1613 &gxbb_cts_mclk_i958_sel,
1614 &gxbb_cts_i958,
1615 &gxbb_32k_clk_sel,
1616 &gxbb_sd_emmc_a_clk0_sel,
1617 &gxbb_sd_emmc_b_clk0_sel,
1618 &gxbb_sd_emmc_c_clk0_sel,
1619};
1620
1621static struct clk_divider *const gxbb_clk_dividers[] = {
1622 &gxbb_mpeg_clk_div,
1623 &gxbb_sar_adc_clk_div,
1624 &gxbb_mali_0_div,
1625 &gxbb_mali_1_div,
1626 &gxbb_cts_mclk_i958_div,
1627 &gxbb_32k_clk_div,
1628 &gxbb_sd_emmc_a_clk0_div,
1629 &gxbb_sd_emmc_b_clk0_div,
1630 &gxbb_sd_emmc_c_clk0_div,
1631};
1632
1633static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
1634 &gxbb_cts_amclk_div,
1635};
1636
1637struct clkc_data {
1638 struct clk_gate *const *clk_gates;
1639 unsigned int clk_gates_count;
1640 struct meson_clk_mpll *const *clk_mplls;
1641 unsigned int clk_mplls_count;
1642 struct meson_clk_pll *const *clk_plls;
1643 unsigned int clk_plls_count;
1644 struct clk_mux *const *clk_muxes;
1645 unsigned int clk_muxes_count;
1646 struct clk_divider *const *clk_dividers;
1647 unsigned int clk_dividers_count;
1648 struct meson_clk_audio_divider *const *clk_audio_dividers;
1649 unsigned int clk_audio_dividers_count;
1650 struct clk_hw_onecell_data *hw_onecell_data;
1651};
1652
1653static const struct clkc_data gxbb_clkc_data = {
1654 .clk_gates = gxbb_clk_gates,
1655 .clk_gates_count = ARRAY_SIZE(gxbb_clk_gates),
1656 .clk_mplls = gxbb_clk_mplls,
1657 .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls),
1658 .clk_plls = gxbb_clk_plls,
1659 .clk_plls_count = ARRAY_SIZE(gxbb_clk_plls),
1660 .clk_muxes = gxbb_clk_muxes,
1661 .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes),
1662 .clk_dividers = gxbb_clk_dividers,
1663 .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
1664 .clk_audio_dividers = gxbb_audio_dividers,
1665 .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
1666 .hw_onecell_data = &gxbb_hw_onecell_data,
1667};
1668
1669static const struct clkc_data gxl_clkc_data = {
1670 .clk_gates = gxbb_clk_gates,
1671 .clk_gates_count = ARRAY_SIZE(gxbb_clk_gates),
1672 .clk_mplls = gxbb_clk_mplls,
1673 .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls),
1674 .clk_plls = gxl_clk_plls,
1675 .clk_plls_count = ARRAY_SIZE(gxl_clk_plls),
1676 .clk_muxes = gxbb_clk_muxes,
1677 .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes),
1678 .clk_dividers = gxbb_clk_dividers,
1679 .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
1680 .clk_audio_dividers = gxbb_audio_dividers,
1681 .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
1682 .hw_onecell_data = &gxl_hw_onecell_data,
1683};
1684
1685static const struct of_device_id clkc_match_table[] = {
1686 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
1687 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
1688 {},
1689};
1690
1691static int gxbb_clkc_probe(struct platform_device *pdev)
1692{
1693 const struct clkc_data *clkc_data;
1694 void __iomem *clk_base;
1695 int ret, clkid, i;
1696 struct device *dev = &pdev->dev;
1697
1698 clkc_data = of_device_get_match_data(&pdev->dev);
1699 if (!clkc_data)
1700 return -EINVAL;
1701
1702 /* Generic clocks and PLLs */
1703 clk_base = of_iomap(dev->of_node, 0);
1704 if (!clk_base) {
1705 pr_err("%s: Unable to map clk base\n", __func__);
1706 return -ENXIO;
1707 }
1708
1709 /* Populate base address for PLLs */
1710 for (i = 0; i < clkc_data->clk_plls_count; i++)
1711 clkc_data->clk_plls[i]->base = clk_base;
1712
1713 /* Populate base address for MPLLs */
1714 for (i = 0; i < clkc_data->clk_mplls_count; i++)
1715 clkc_data->clk_mplls[i]->base = clk_base;
1716
1717 /* Populate base address for gates */
1718 for (i = 0; i < clkc_data->clk_gates_count; i++)
1719 clkc_data->clk_gates[i]->reg = clk_base +
1720 (u64)clkc_data->clk_gates[i]->reg;
1721
1722 /* Populate base address for muxes */
1723 for (i = 0; i < clkc_data->clk_muxes_count; i++)
1724 clkc_data->clk_muxes[i]->reg = clk_base +
1725 (u64)clkc_data->clk_muxes[i]->reg;
1726
1727 /* Populate base address for dividers */
1728 for (i = 0; i < clkc_data->clk_dividers_count; i++)
1729 clkc_data->clk_dividers[i]->reg = clk_base +
1730 (u64)clkc_data->clk_dividers[i]->reg;
1731
1732 /* Populate base address for the audio dividers */
1733 for (i = 0; i < clkc_data->clk_audio_dividers_count; i++)
1734 clkc_data->clk_audio_dividers[i]->base = clk_base;
1735
1736 /*
1737 * register all clks
1738 */
1739 for (clkid = 0; clkid < clkc_data->hw_onecell_data->num; clkid++) {
1740 /* array might be sparse */
1741 if (!clkc_data->hw_onecell_data->hws[clkid])
1742 continue;
1743
1744 ret = devm_clk_hw_register(dev,
1745 clkc_data->hw_onecell_data->hws[clkid]);
1746 if (ret)
1747 goto iounmap;
1748 }
1749
1750 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
1751 clkc_data->hw_onecell_data);
1752
1753iounmap:
1754 iounmap(clk_base);
1755 return ret;
1756}
1757
1758static struct platform_driver gxbb_driver = {
1759 .probe = gxbb_clkc_probe,
1760 .driver = {
1761 .name = "gxbb-clkc",
1762 .of_match_table = clkc_match_table,
1763 },
1764};
1765
1766builtin_platform_driver(gxbb_driver);