rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * r8a7795 Clock Pulse Generator / Module Standby and Software Reset |
| 3 | * |
| 4 | * Copyright (C) 2015 Glider bvba |
| 5 | * |
| 6 | * Based on clk-rcar-gen3.c |
| 7 | * |
| 8 | * Copyright (C) 2015 Renesas Electronics Corp. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | */ |
| 14 | |
| 15 | #include <linux/device.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/kernel.h> |
| 18 | #include <linux/soc/renesas/rcar-rst.h> |
| 19 | #include <linux/sys_soc.h> |
| 20 | |
| 21 | #include <dt-bindings/clock/r8a7795-cpg-mssr.h> |
| 22 | |
| 23 | #include "renesas-cpg-mssr.h" |
| 24 | #include "rcar-gen3-cpg.h" |
| 25 | |
| 26 | enum clk_ids { |
| 27 | /* Core Clock Outputs exported to DT */ |
| 28 | LAST_DT_CORE_CLK = R8A7795_CLK_S0D12, |
| 29 | |
| 30 | /* External Input Clocks */ |
| 31 | CLK_EXTAL, |
| 32 | CLK_EXTALR, |
| 33 | |
| 34 | /* Internal Core Clocks */ |
| 35 | CLK_MAIN, |
| 36 | CLK_PLL0, |
| 37 | CLK_PLL1, |
| 38 | CLK_PLL2, |
| 39 | CLK_PLL3, |
| 40 | CLK_PLL4, |
| 41 | CLK_PLL1_DIV2, |
| 42 | CLK_PLL1_DIV4, |
| 43 | CLK_S0, |
| 44 | CLK_S1, |
| 45 | CLK_S2, |
| 46 | CLK_S3, |
| 47 | CLK_SDSRC, |
| 48 | CLK_SSPSRC, |
| 49 | CLK_RINT, |
| 50 | |
| 51 | /* Module Clocks */ |
| 52 | MOD_CLK_BASE |
| 53 | }; |
| 54 | |
| 55 | static struct cpg_core_clk r8a7795_core_clks[] __initdata = { |
| 56 | /* External Clock Inputs */ |
| 57 | DEF_INPUT("extal", CLK_EXTAL), |
| 58 | DEF_INPUT("extalr", CLK_EXTALR), |
| 59 | |
| 60 | /* Internal Core Clocks */ |
| 61 | DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), |
| 62 | DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), |
| 63 | DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), |
| 64 | DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), |
| 65 | DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), |
| 66 | DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN), |
| 67 | |
| 68 | DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), |
| 69 | DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), |
| 70 | DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), |
| 71 | DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), |
| 72 | DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), |
| 73 | DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), |
| 74 | DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), |
| 75 | |
| 76 | /* Core Clock Outputs */ |
| 77 | DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), |
| 78 | DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), |
| 79 | DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), |
| 80 | DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1), |
| 81 | DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1), |
| 82 | DEF_FIXED("s0d2", R8A7795_CLK_S0D2, CLK_S0, 2, 1), |
| 83 | DEF_FIXED("s0d3", R8A7795_CLK_S0D3, CLK_S0, 3, 1), |
| 84 | DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1), |
| 85 | DEF_FIXED("s0d6", R8A7795_CLK_S0D6, CLK_S0, 6, 1), |
| 86 | DEF_FIXED("s0d8", R8A7795_CLK_S0D8, CLK_S0, 8, 1), |
| 87 | DEF_FIXED("s0d12", R8A7795_CLK_S0D12, CLK_S0, 12, 1), |
| 88 | DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1), |
| 89 | DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1), |
| 90 | DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1), |
| 91 | DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1), |
| 92 | DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1), |
| 93 | DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1), |
| 94 | DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1), |
| 95 | DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1), |
| 96 | DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1), |
| 97 | |
| 98 | DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074), |
| 99 | DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078), |
| 100 | DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268), |
| 101 | DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c), |
| 102 | |
| 103 | DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1), |
| 104 | DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1), |
| 105 | |
| 106 | DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244), |
| 107 | DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), |
| 108 | DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014), |
| 109 | DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250), |
| 110 | |
| 111 | DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), |
| 112 | DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), |
| 113 | |
| 114 | DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), |
| 115 | }; |
| 116 | |
| 117 | static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { |
| 118 | DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */ |
| 119 | DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1), |
| 120 | DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1), |
| 121 | DEF_MOD("scif5", 202, R8A7795_CLK_S3D4), |
| 122 | DEF_MOD("scif4", 203, R8A7795_CLK_S3D4), |
| 123 | DEF_MOD("scif3", 204, R8A7795_CLK_S3D4), |
| 124 | DEF_MOD("scif1", 206, R8A7795_CLK_S3D4), |
| 125 | DEF_MOD("scif0", 207, R8A7795_CLK_S3D4), |
| 126 | DEF_MOD("msiof3", 208, R8A7795_CLK_MSO), |
| 127 | DEF_MOD("msiof2", 209, R8A7795_CLK_MSO), |
| 128 | DEF_MOD("msiof1", 210, R8A7795_CLK_MSO), |
| 129 | DEF_MOD("msiof0", 211, R8A7795_CLK_MSO), |
| 130 | DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3), |
| 131 | DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3), |
| 132 | DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3), |
| 133 | DEF_MOD("cmt3", 300, R8A7795_CLK_R), |
| 134 | DEF_MOD("cmt2", 301, R8A7795_CLK_R), |
| 135 | DEF_MOD("cmt1", 302, R8A7795_CLK_R), |
| 136 | DEF_MOD("cmt0", 303, R8A7795_CLK_R), |
| 137 | DEF_MOD("scif2", 310, R8A7795_CLK_S3D4), |
| 138 | DEF_MOD("sdif3", 311, R8A7795_CLK_SD3), |
| 139 | DEF_MOD("sdif2", 312, R8A7795_CLK_SD2), |
| 140 | DEF_MOD("sdif1", 313, R8A7795_CLK_SD1), |
| 141 | DEF_MOD("sdif0", 314, R8A7795_CLK_SD0), |
| 142 | DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1), |
| 143 | DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1), |
| 144 | DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1), |
| 145 | DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */ |
| 146 | DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1), |
| 147 | DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1), |
| 148 | DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1), |
| 149 | DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1), |
| 150 | DEF_MOD("rwdt", 402, R8A7795_CLK_R), |
| 151 | DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), |
| 152 | DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1), |
| 153 | DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3), |
| 154 | DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3), |
| 155 | DEF_MOD("drif7", 508, R8A7795_CLK_S3D2), |
| 156 | DEF_MOD("drif6", 509, R8A7795_CLK_S3D2), |
| 157 | DEF_MOD("drif5", 510, R8A7795_CLK_S3D2), |
| 158 | DEF_MOD("drif4", 511, R8A7795_CLK_S3D2), |
| 159 | DEF_MOD("drif3", 512, R8A7795_CLK_S3D2), |
| 160 | DEF_MOD("drif2", 513, R8A7795_CLK_S3D2), |
| 161 | DEF_MOD("drif1", 514, R8A7795_CLK_S3D2), |
| 162 | DEF_MOD("drif0", 515, R8A7795_CLK_S3D2), |
| 163 | DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1), |
| 164 | DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1), |
| 165 | DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1), |
| 166 | DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1), |
| 167 | DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1), |
| 168 | DEF_MOD("thermal", 522, R8A7795_CLK_CP), |
| 169 | DEF_MOD("pwm", 523, R8A7795_CLK_S0D12), |
| 170 | DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */ |
| 171 | DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2), |
| 172 | DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2), |
| 173 | DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2), |
| 174 | DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1), |
| 175 | DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1), |
| 176 | DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */ |
| 177 | DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1), |
| 178 | DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1), |
| 179 | DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */ |
| 180 | DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1), |
| 181 | DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1), |
| 182 | DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */ |
| 183 | DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */ |
| 184 | DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1), |
| 185 | DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */ |
| 186 | DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2), |
| 187 | DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2), |
| 188 | DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2), |
| 189 | DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1), |
| 190 | DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1), |
| 191 | DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */ |
| 192 | DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1), |
| 193 | DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1), |
| 194 | DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4), |
| 195 | DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4), |
| 196 | DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4), |
| 197 | DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4), |
| 198 | DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4), |
| 199 | DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4), |
| 200 | DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */ |
| 201 | DEF_MOD("csi20", 714, R8A7795_CLK_CSI0), |
| 202 | DEF_MOD("csi41", 715, R8A7795_CLK_CSI0), |
| 203 | DEF_MOD("csi40", 716, R8A7795_CLK_CSI0), |
| 204 | DEF_MOD("du3", 721, R8A7795_CLK_S2D1), |
| 205 | DEF_MOD("du2", 722, R8A7795_CLK_S2D1), |
| 206 | DEF_MOD("du1", 723, R8A7795_CLK_S2D1), |
| 207 | DEF_MOD("du0", 724, R8A7795_CLK_S2D1), |
| 208 | DEF_MOD("lvds", 727, R8A7795_CLK_S0D4), |
| 209 | DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI), |
| 210 | DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI), |
| 211 | DEF_MOD("vin7", 804, R8A7795_CLK_S0D2), |
| 212 | DEF_MOD("vin6", 805, R8A7795_CLK_S0D2), |
| 213 | DEF_MOD("vin5", 806, R8A7795_CLK_S0D2), |
| 214 | DEF_MOD("vin4", 807, R8A7795_CLK_S0D2), |
| 215 | DEF_MOD("vin3", 808, R8A7795_CLK_S0D2), |
| 216 | DEF_MOD("vin2", 809, R8A7795_CLK_S0D2), |
| 217 | DEF_MOD("vin1", 810, R8A7795_CLK_S0D2), |
| 218 | DEF_MOD("vin0", 811, R8A7795_CLK_S0D2), |
| 219 | DEF_MOD("etheravb", 812, R8A7795_CLK_S0D6), |
| 220 | DEF_MOD("sata0", 815, R8A7795_CLK_S3D2), |
| 221 | DEF_MOD("imr3", 820, R8A7795_CLK_S0D2), |
| 222 | DEF_MOD("imr2", 821, R8A7795_CLK_S0D2), |
| 223 | DEF_MOD("imr1", 822, R8A7795_CLK_S0D2), |
| 224 | DEF_MOD("imr0", 823, R8A7795_CLK_S0D2), |
| 225 | DEF_MOD("gpio7", 905, R8A7795_CLK_S3D4), |
| 226 | DEF_MOD("gpio6", 906, R8A7795_CLK_S3D4), |
| 227 | DEF_MOD("gpio5", 907, R8A7795_CLK_S3D4), |
| 228 | DEF_MOD("gpio4", 908, R8A7795_CLK_S3D4), |
| 229 | DEF_MOD("gpio3", 909, R8A7795_CLK_S3D4), |
| 230 | DEF_MOD("gpio2", 910, R8A7795_CLK_S3D4), |
| 231 | DEF_MOD("gpio1", 911, R8A7795_CLK_S3D4), |
| 232 | DEF_MOD("gpio0", 912, R8A7795_CLK_S3D4), |
| 233 | DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2), |
| 234 | DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4), |
| 235 | DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4), |
| 236 | DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6), |
| 237 | DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6), |
| 238 | DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP), |
| 239 | DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6), |
| 240 | DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6), |
| 241 | DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2), |
| 242 | DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2), |
| 243 | DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2), |
| 244 | DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4), |
| 245 | DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), |
| 246 | DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), |
| 247 | DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), |
| 248 | DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), |
| 249 | DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), |
| 250 | DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), |
| 251 | DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), |
| 252 | DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), |
| 253 | DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), |
| 254 | DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), |
| 255 | DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4), |
| 256 | DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), |
| 257 | DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), |
| 258 | DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), |
| 259 | DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), |
| 260 | DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), |
| 261 | DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), |
| 262 | DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), |
| 263 | DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), |
| 264 | DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), |
| 265 | DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), |
| 266 | DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), |
| 267 | DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), |
| 268 | DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), |
| 269 | DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), |
| 270 | }; |
| 271 | |
| 272 | static const unsigned int r8a7795_crit_mod_clks[] __initconst = { |
| 273 | MOD_CLK_ID(408), /* INTC-AP (GIC) */ |
| 274 | }; |
| 275 | |
| 276 | |
| 277 | /* |
| 278 | * CPG Clock Data |
| 279 | */ |
| 280 | |
| 281 | /* |
| 282 | * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 |
| 283 | * 14 13 19 17 (MHz) |
| 284 | *------------------------------------------------------------------- |
| 285 | * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 |
| 286 | * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 |
| 287 | * 0 0 1 0 Prohibited setting |
| 288 | * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 |
| 289 | * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 |
| 290 | * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 |
| 291 | * 0 1 1 0 Prohibited setting |
| 292 | * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 |
| 293 | * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 |
| 294 | * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 |
| 295 | * 1 0 1 0 Prohibited setting |
| 296 | * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 |
| 297 | * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 |
| 298 | * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 |
| 299 | * 1 1 1 0 Prohibited setting |
| 300 | * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 |
| 301 | */ |
| 302 | #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ |
| 303 | (((md) & BIT(13)) >> 11) | \ |
| 304 | (((md) & BIT(19)) >> 18) | \ |
| 305 | (((md) & BIT(17)) >> 17)) |
| 306 | |
| 307 | static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { |
| 308 | /* EXTAL div PLL1 mult/div PLL3 mult/div */ |
| 309 | { 1, 192, 1, 192, 1, }, |
| 310 | { 1, 192, 1, 128, 1, }, |
| 311 | { 0, /* Prohibited setting */ }, |
| 312 | { 1, 192, 1, 192, 1, }, |
| 313 | { 1, 160, 1, 160, 1, }, |
| 314 | { 1, 160, 1, 106, 1, }, |
| 315 | { 0, /* Prohibited setting */ }, |
| 316 | { 1, 160, 1, 160, 1, }, |
| 317 | { 1, 128, 1, 128, 1, }, |
| 318 | { 1, 128, 1, 84, 1, }, |
| 319 | { 0, /* Prohibited setting */ }, |
| 320 | { 1, 128, 1, 128, 1, }, |
| 321 | { 2, 192, 1, 192, 1, }, |
| 322 | { 2, 192, 1, 128, 1, }, |
| 323 | { 0, /* Prohibited setting */ }, |
| 324 | { 2, 192, 1, 192, 1, }, |
| 325 | }; |
| 326 | |
| 327 | static const struct soc_device_attribute r8a7795es1[] __initconst = { |
| 328 | { .soc_id = "r8a7795", .revision = "ES1.*" }, |
| 329 | { /* sentinel */ } |
| 330 | }; |
| 331 | |
| 332 | |
| 333 | /* |
| 334 | * Fixups for R-Car H3 ES1.x |
| 335 | */ |
| 336 | |
| 337 | static const unsigned int r8a7795es1_mod_nullify[] __initconst = { |
| 338 | MOD_CLK_ID(326), /* USB-DMAC3-0 */ |
| 339 | MOD_CLK_ID(329), /* USB-DMAC3-1 */ |
| 340 | MOD_CLK_ID(700), /* EHCI/OHCI3 */ |
| 341 | MOD_CLK_ID(705), /* HS-USB-IF3 */ |
| 342 | |
| 343 | }; |
| 344 | |
| 345 | static const struct mssr_mod_reparent r8a7795es1_mod_reparent[] __initconst = { |
| 346 | { MOD_CLK_ID(118), R8A7795_CLK_S2D1 }, /* FDP1-1 */ |
| 347 | { MOD_CLK_ID(119), R8A7795_CLK_S2D1 }, /* FDP1-0 */ |
| 348 | { MOD_CLK_ID(217), R8A7795_CLK_S3D1 }, /* SYS-DMAC2 */ |
| 349 | { MOD_CLK_ID(218), R8A7795_CLK_S3D1 }, /* SYS-DMAC1 */ |
| 350 | { MOD_CLK_ID(219), R8A7795_CLK_S3D1 }, /* SYS-DMAC0 */ |
| 351 | { MOD_CLK_ID(501), R8A7795_CLK_S3D1 }, /* AUDMAC1 */ |
| 352 | { MOD_CLK_ID(502), R8A7795_CLK_S3D1 }, /* AUDMAC0 */ |
| 353 | { MOD_CLK_ID(523), R8A7795_CLK_S3D4 }, /* PWM */ |
| 354 | { MOD_CLK_ID(601), R8A7795_CLK_S2D1 }, /* FCPVD2 */ |
| 355 | { MOD_CLK_ID(602), R8A7795_CLK_S2D1 }, /* FCPVD1 */ |
| 356 | { MOD_CLK_ID(603), R8A7795_CLK_S2D1 }, /* FCPVD0 */ |
| 357 | { MOD_CLK_ID(606), R8A7795_CLK_S2D1 }, /* FCPVB1 */ |
| 358 | { MOD_CLK_ID(607), R8A7795_CLK_S2D1 }, /* FCPVB0 */ |
| 359 | { MOD_CLK_ID(610), R8A7795_CLK_S2D1 }, /* FCPVI1 */ |
| 360 | { MOD_CLK_ID(611), R8A7795_CLK_S2D1 }, /* FCPVI0 */ |
| 361 | { MOD_CLK_ID(614), R8A7795_CLK_S2D1 }, /* FCPF1 */ |
| 362 | { MOD_CLK_ID(615), R8A7795_CLK_S2D1 }, /* FCPF0 */ |
| 363 | { MOD_CLK_ID(619), R8A7795_CLK_S2D1 }, /* FCPCS */ |
| 364 | { MOD_CLK_ID(621), R8A7795_CLK_S2D1 }, /* VSPD2 */ |
| 365 | { MOD_CLK_ID(622), R8A7795_CLK_S2D1 }, /* VSPD1 */ |
| 366 | { MOD_CLK_ID(623), R8A7795_CLK_S2D1 }, /* VSPD0 */ |
| 367 | { MOD_CLK_ID(624), R8A7795_CLK_S2D1 }, /* VSPBC */ |
| 368 | { MOD_CLK_ID(626), R8A7795_CLK_S2D1 }, /* VSPBD */ |
| 369 | { MOD_CLK_ID(630), R8A7795_CLK_S2D1 }, /* VSPI1 */ |
| 370 | { MOD_CLK_ID(631), R8A7795_CLK_S2D1 }, /* VSPI0 */ |
| 371 | { MOD_CLK_ID(804), R8A7795_CLK_S2D1 }, /* VIN7 */ |
| 372 | { MOD_CLK_ID(805), R8A7795_CLK_S2D1 }, /* VIN6 */ |
| 373 | { MOD_CLK_ID(806), R8A7795_CLK_S2D1 }, /* VIN5 */ |
| 374 | { MOD_CLK_ID(807), R8A7795_CLK_S2D1 }, /* VIN4 */ |
| 375 | { MOD_CLK_ID(808), R8A7795_CLK_S2D1 }, /* VIN3 */ |
| 376 | { MOD_CLK_ID(809), R8A7795_CLK_S2D1 }, /* VIN2 */ |
| 377 | { MOD_CLK_ID(810), R8A7795_CLK_S2D1 }, /* VIN1 */ |
| 378 | { MOD_CLK_ID(811), R8A7795_CLK_S2D1 }, /* VIN0 */ |
| 379 | { MOD_CLK_ID(812), R8A7795_CLK_S3D2 }, /* EAVB-IF */ |
| 380 | { MOD_CLK_ID(820), R8A7795_CLK_S2D1 }, /* IMR3 */ |
| 381 | { MOD_CLK_ID(821), R8A7795_CLK_S2D1 }, /* IMR2 */ |
| 382 | { MOD_CLK_ID(822), R8A7795_CLK_S2D1 }, /* IMR1 */ |
| 383 | { MOD_CLK_ID(823), R8A7795_CLK_S2D1 }, /* IMR0 */ |
| 384 | { MOD_CLK_ID(905), R8A7795_CLK_CP }, /* GPIO7 */ |
| 385 | { MOD_CLK_ID(906), R8A7795_CLK_CP }, /* GPIO6 */ |
| 386 | { MOD_CLK_ID(907), R8A7795_CLK_CP }, /* GPIO5 */ |
| 387 | { MOD_CLK_ID(908), R8A7795_CLK_CP }, /* GPIO4 */ |
| 388 | { MOD_CLK_ID(909), R8A7795_CLK_CP }, /* GPIO3 */ |
| 389 | { MOD_CLK_ID(910), R8A7795_CLK_CP }, /* GPIO2 */ |
| 390 | { MOD_CLK_ID(911), R8A7795_CLK_CP }, /* GPIO1 */ |
| 391 | { MOD_CLK_ID(912), R8A7795_CLK_CP }, /* GPIO0 */ |
| 392 | { MOD_CLK_ID(918), R8A7795_CLK_S3D2 }, /* I2C6 */ |
| 393 | { MOD_CLK_ID(919), R8A7795_CLK_S3D2 }, /* I2C5 */ |
| 394 | { MOD_CLK_ID(927), R8A7795_CLK_S3D2 }, /* I2C4 */ |
| 395 | { MOD_CLK_ID(928), R8A7795_CLK_S3D2 }, /* I2C3 */ |
| 396 | }; |
| 397 | |
| 398 | |
| 399 | /* |
| 400 | * Fixups for R-Car H3 ES2.x |
| 401 | */ |
| 402 | |
| 403 | static const unsigned int r8a7795es2_mod_nullify[] __initconst = { |
| 404 | MOD_CLK_ID(117), /* FDP1-2 */ |
| 405 | MOD_CLK_ID(327), /* USB3-IF1 */ |
| 406 | MOD_CLK_ID(600), /* FCPVD3 */ |
| 407 | MOD_CLK_ID(609), /* FCPVI2 */ |
| 408 | MOD_CLK_ID(613), /* FCPF2 */ |
| 409 | MOD_CLK_ID(616), /* FCPCI1 */ |
| 410 | MOD_CLK_ID(617), /* FCPCI0 */ |
| 411 | MOD_CLK_ID(620), /* VSPD3 */ |
| 412 | MOD_CLK_ID(629), /* VSPI2 */ |
| 413 | MOD_CLK_ID(713), /* CSI21 */ |
| 414 | }; |
| 415 | |
| 416 | static int __init r8a7795_cpg_mssr_init(struct device *dev) |
| 417 | { |
| 418 | const struct rcar_gen3_cpg_pll_config *cpg_pll_config; |
| 419 | u32 cpg_mode; |
| 420 | int error; |
| 421 | |
| 422 | error = rcar_rst_read_mode_pins(&cpg_mode); |
| 423 | if (error) |
| 424 | return error; |
| 425 | |
| 426 | cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; |
| 427 | if (!cpg_pll_config->extal_div) { |
| 428 | dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode); |
| 429 | return -EINVAL; |
| 430 | } |
| 431 | |
| 432 | if (soc_device_match(r8a7795es1)) { |
| 433 | cpg_core_nullify_range(r8a7795_core_clks, |
| 434 | ARRAY_SIZE(r8a7795_core_clks), |
| 435 | R8A7795_CLK_S0D2, R8A7795_CLK_S0D12); |
| 436 | mssr_mod_nullify(r8a7795_mod_clks, |
| 437 | ARRAY_SIZE(r8a7795_mod_clks), |
| 438 | r8a7795es1_mod_nullify, |
| 439 | ARRAY_SIZE(r8a7795es1_mod_nullify)); |
| 440 | mssr_mod_reparent(r8a7795_mod_clks, |
| 441 | ARRAY_SIZE(r8a7795_mod_clks), |
| 442 | r8a7795es1_mod_reparent, |
| 443 | ARRAY_SIZE(r8a7795es1_mod_reparent)); |
| 444 | } else { |
| 445 | mssr_mod_nullify(r8a7795_mod_clks, |
| 446 | ARRAY_SIZE(r8a7795_mod_clks), |
| 447 | r8a7795es2_mod_nullify, |
| 448 | ARRAY_SIZE(r8a7795es2_mod_nullify)); |
| 449 | } |
| 450 | |
| 451 | return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); |
| 452 | } |
| 453 | |
| 454 | const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = { |
| 455 | /* Core Clocks */ |
| 456 | .core_clks = r8a7795_core_clks, |
| 457 | .num_core_clks = ARRAY_SIZE(r8a7795_core_clks), |
| 458 | .last_dt_core_clk = LAST_DT_CORE_CLK, |
| 459 | .num_total_core_clks = MOD_CLK_BASE, |
| 460 | |
| 461 | /* Module Clocks */ |
| 462 | .mod_clks = r8a7795_mod_clks, |
| 463 | .num_mod_clks = ARRAY_SIZE(r8a7795_mod_clks), |
| 464 | .num_hw_mod_clks = 12 * 32, |
| 465 | |
| 466 | /* Critical Module Clocks */ |
| 467 | .crit_mod_clks = r8a7795_crit_mod_clks, |
| 468 | .num_crit_mod_clks = ARRAY_SIZE(r8a7795_crit_mod_clks), |
| 469 | |
| 470 | /* Callbacks */ |
| 471 | .init = r8a7795_cpg_mssr_init, |
| 472 | .cpg_clk_register = rcar_gen3_cpg_clk_register, |
| 473 | }; |