blob: 7ce0fa86c5ff821b0a2745e589b8f047b66b4e1b [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +08001/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 * Author: Thomas Abraham <thomas.ab@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This file includes utility functions to register clocks to common
11 * clock framework for Samsung platforms.
12*/
13
14#include <linux/slab.h>
15#include <linux/clkdev.h>
16#include <linux/clk.h>
17#include <linux/clk-provider.h>
18#include <linux/of_address.h>
19#include <linux/syscore_ops.h>
20
21#include "clk.h"
22
23static LIST_HEAD(clock_reg_cache_list);
24
25void samsung_clk_save(void __iomem *base,
26 struct samsung_clk_reg_dump *rd,
27 unsigned int num_regs)
28{
29 for (; num_regs > 0; --num_regs, ++rd)
30 rd->value = readl(base + rd->offset);
31}
32
33void samsung_clk_restore(void __iomem *base,
34 const struct samsung_clk_reg_dump *rd,
35 unsigned int num_regs)
36{
37 for (; num_regs > 0; --num_regs, ++rd)
38 writel(rd->value, base + rd->offset);
39}
40
41struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
42 const unsigned long *rdump,
43 unsigned long nr_rdump)
44{
45 struct samsung_clk_reg_dump *rd;
46 unsigned int i;
47
48 rd = kcalloc(nr_rdump, sizeof(*rd), GFP_KERNEL);
49 if (!rd)
50 return NULL;
51
52 for (i = 0; i < nr_rdump; ++i)
53 rd[i].offset = rdump[i];
54
55 return rd;
56}
57
58/* setup the essentials required to support clock lookup using ccf */
59struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
60 void __iomem *base, unsigned long nr_clks)
61{
62 struct samsung_clk_provider *ctx;
63 int i;
64
65 ctx = kzalloc(sizeof(struct samsung_clk_provider) +
66 sizeof(*ctx->clk_data.hws) * nr_clks, GFP_KERNEL);
67 if (!ctx)
68 panic("could not allocate clock provider context.\n");
69
70 for (i = 0; i < nr_clks; ++i)
71 ctx->clk_data.hws[i] = ERR_PTR(-ENOENT);
72
73 ctx->reg_base = base;
74 ctx->clk_data.num = nr_clks;
75 spin_lock_init(&ctx->lock);
76
77 return ctx;
78}
79
80void __init samsung_clk_of_add_provider(struct device_node *np,
81 struct samsung_clk_provider *ctx)
82{
83 if (np) {
84 if (of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
85 &ctx->clk_data))
86 panic("could not register clk provider\n");
87 }
88}
89
90/* add a clock instance to the clock lookup table used for dt based lookup */
91void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
92 struct clk_hw *clk_hw, unsigned int id)
93{
94 if (id)
95 ctx->clk_data.hws[id] = clk_hw;
96}
97
98/* register a list of aliases */
99void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx,
100 const struct samsung_clock_alias *list,
101 unsigned int nr_clk)
102{
103 struct clk_hw *clk_hw;
104 unsigned int idx, ret;
105
106 for (idx = 0; idx < nr_clk; idx++, list++) {
107 if (!list->id) {
108 pr_err("%s: clock id missing for index %d\n", __func__,
109 idx);
110 continue;
111 }
112
113 clk_hw = ctx->clk_data.hws[list->id];
114 if (!clk_hw) {
115 pr_err("%s: failed to find clock %d\n", __func__,
116 list->id);
117 continue;
118 }
119
120 ret = clk_hw_register_clkdev(clk_hw, list->alias,
121 list->dev_name);
122 if (ret)
123 pr_err("%s: failed to register lookup %s\n",
124 __func__, list->alias);
125 }
126}
127
128/* register a list of fixed clocks */
129void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx,
130 const struct samsung_fixed_rate_clock *list,
131 unsigned int nr_clk)
132{
133 struct clk_hw *clk_hw;
134 unsigned int idx, ret;
135
136 for (idx = 0; idx < nr_clk; idx++, list++) {
137 clk_hw = clk_hw_register_fixed_rate(NULL, list->name,
138 list->parent_name, list->flags, list->fixed_rate);
139 if (IS_ERR(clk_hw)) {
140 pr_err("%s: failed to register clock %s\n", __func__,
141 list->name);
142 continue;
143 }
144
145 samsung_clk_add_lookup(ctx, clk_hw, list->id);
146
147 /*
148 * Unconditionally add a clock lookup for the fixed rate clocks.
149 * There are not many of these on any of Samsung platforms.
150 */
151 ret = clk_hw_register_clkdev(clk_hw, list->name, NULL);
152 if (ret)
153 pr_err("%s: failed to register clock lookup for %s",
154 __func__, list->name);
155 }
156}
157
158/* register a list of fixed factor clocks */
159void __init samsung_clk_register_fixed_factor(struct samsung_clk_provider *ctx,
160 const struct samsung_fixed_factor_clock *list, unsigned int nr_clk)
161{
162 struct clk_hw *clk_hw;
163 unsigned int idx;
164
165 for (idx = 0; idx < nr_clk; idx++, list++) {
166 clk_hw = clk_hw_register_fixed_factor(NULL, list->name,
167 list->parent_name, list->flags, list->mult, list->div);
168 if (IS_ERR(clk_hw)) {
169 pr_err("%s: failed to register clock %s\n", __func__,
170 list->name);
171 continue;
172 }
173
174 samsung_clk_add_lookup(ctx, clk_hw, list->id);
175 }
176}
177
178/* register a list of mux clocks */
179void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
180 const struct samsung_mux_clock *list,
181 unsigned int nr_clk)
182{
183 struct clk_hw *clk_hw;
184 unsigned int idx, ret;
185
186 for (idx = 0; idx < nr_clk; idx++, list++) {
187 clk_hw = clk_hw_register_mux(NULL, list->name,
188 list->parent_names, list->num_parents, list->flags,
189 ctx->reg_base + list->offset,
190 list->shift, list->width, list->mux_flags, &ctx->lock);
191 if (IS_ERR(clk_hw)) {
192 pr_err("%s: failed to register clock %s\n", __func__,
193 list->name);
194 continue;
195 }
196
197 samsung_clk_add_lookup(ctx, clk_hw, list->id);
198
199 /* register a clock lookup only if a clock alias is specified */
200 if (list->alias) {
201 ret = clk_hw_register_clkdev(clk_hw, list->alias,
202 list->dev_name);
203 if (ret)
204 pr_err("%s: failed to register lookup %s\n",
205 __func__, list->alias);
206 }
207 }
208}
209
210/* register a list of div clocks */
211void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
212 const struct samsung_div_clock *list,
213 unsigned int nr_clk)
214{
215 struct clk_hw *clk_hw;
216 unsigned int idx, ret;
217
218 for (idx = 0; idx < nr_clk; idx++, list++) {
219 if (list->table)
220 clk_hw = clk_hw_register_divider_table(NULL,
221 list->name, list->parent_name, list->flags,
222 ctx->reg_base + list->offset,
223 list->shift, list->width, list->div_flags,
224 list->table, &ctx->lock);
225 else
226 clk_hw = clk_hw_register_divider(NULL, list->name,
227 list->parent_name, list->flags,
228 ctx->reg_base + list->offset, list->shift,
229 list->width, list->div_flags, &ctx->lock);
230 if (IS_ERR(clk_hw)) {
231 pr_err("%s: failed to register clock %s\n", __func__,
232 list->name);
233 continue;
234 }
235
236 samsung_clk_add_lookup(ctx, clk_hw, list->id);
237
238 /* register a clock lookup only if a clock alias is specified */
239 if (list->alias) {
240 ret = clk_hw_register_clkdev(clk_hw, list->alias,
241 list->dev_name);
242 if (ret)
243 pr_err("%s: failed to register lookup %s\n",
244 __func__, list->alias);
245 }
246 }
247}
248
249/* register a list of gate clocks */
250void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
251 const struct samsung_gate_clock *list,
252 unsigned int nr_clk)
253{
254 struct clk_hw *clk_hw;
255 unsigned int idx, ret;
256
257 for (idx = 0; idx < nr_clk; idx++, list++) {
258 clk_hw = clk_hw_register_gate(NULL, list->name, list->parent_name,
259 list->flags, ctx->reg_base + list->offset,
260 list->bit_idx, list->gate_flags, &ctx->lock);
261 if (IS_ERR(clk_hw)) {
262 pr_err("%s: failed to register clock %s\n", __func__,
263 list->name);
264 continue;
265 }
266
267 /* register a clock lookup only if a clock alias is specified */
268 if (list->alias) {
269 ret = clk_hw_register_clkdev(clk_hw, list->alias,
270 list->dev_name);
271 if (ret)
272 pr_err("%s: failed to register lookup %s\n",
273 __func__, list->alias);
274 }
275
276 samsung_clk_add_lookup(ctx, clk_hw, list->id);
277 }
278}
279
280/*
281 * obtain the clock speed of all external fixed clock sources from device
282 * tree and register it
283 */
284void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx,
285 struct samsung_fixed_rate_clock *fixed_rate_clk,
286 unsigned int nr_fixed_rate_clk,
287 const struct of_device_id *clk_matches)
288{
289 const struct of_device_id *match;
290 struct device_node *clk_np;
291 u32 freq;
292
293 for_each_matching_node_and_match(clk_np, clk_matches, &match) {
294 if (of_property_read_u32(clk_np, "clock-frequency", &freq))
295 continue;
296 fixed_rate_clk[(unsigned long)match->data].fixed_rate = freq;
297 }
298 samsung_clk_register_fixed_rate(ctx, fixed_rate_clk, nr_fixed_rate_clk);
299}
300
301/* utility function to get the rate of a specified clock */
302unsigned long _get_rate(const char *clk_name)
303{
304 struct clk *clk;
305
306 clk = __clk_lookup(clk_name);
307 if (!clk) {
308 pr_err("%s: could not find clock %s\n", __func__, clk_name);
309 return 0;
310 }
311
312 return clk_get_rate(clk);
313}
314
315#ifdef CONFIG_PM_SLEEP
316static int samsung_clk_suspend(void)
317{
318 struct samsung_clock_reg_cache *reg_cache;
319
320 list_for_each_entry(reg_cache, &clock_reg_cache_list, node)
321 samsung_clk_save(reg_cache->reg_base, reg_cache->rdump,
322 reg_cache->rd_num);
323 return 0;
324}
325
326static void samsung_clk_resume(void)
327{
328 struct samsung_clock_reg_cache *reg_cache;
329
330 list_for_each_entry(reg_cache, &clock_reg_cache_list, node)
331 samsung_clk_restore(reg_cache->reg_base, reg_cache->rdump,
332 reg_cache->rd_num);
333}
334
335static struct syscore_ops samsung_clk_syscore_ops = {
336 .suspend = samsung_clk_suspend,
337 .resume = samsung_clk_resume,
338};
339
340void samsung_clk_sleep_init(void __iomem *reg_base,
341 const unsigned long *rdump,
342 unsigned long nr_rdump)
343{
344 struct samsung_clock_reg_cache *reg_cache;
345
346 reg_cache = kzalloc(sizeof(struct samsung_clock_reg_cache),
347 GFP_KERNEL);
348 if (!reg_cache)
349 panic("could not allocate register reg_cache.\n");
350 reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
351
352 if (!reg_cache->rdump)
353 panic("could not allocate register dump storage.\n");
354
355 if (list_empty(&clock_reg_cache_list))
356 register_syscore_ops(&samsung_clk_syscore_ops);
357
358 reg_cache->reg_base = reg_base;
359 reg_cache->rd_num = nr_rdump;
360 list_add_tail(&reg_cache->node, &clock_reg_cache_list);
361}
362
363#else
364void samsung_clk_sleep_init(void __iomem *reg_base,
365 const unsigned long *rdump,
366 unsigned long nr_rdump) {}
367#endif
368
369/*
370 * Common function which registers plls, muxes, dividers and gates
371 * for each CMU. It also add CMU register list to register cache.
372 */
373struct samsung_clk_provider * __init samsung_cmu_register_one(
374 struct device_node *np,
375 const struct samsung_cmu_info *cmu)
376{
377 void __iomem *reg_base;
378 struct samsung_clk_provider *ctx;
379
380 reg_base = of_iomap(np, 0);
381 if (!reg_base) {
382 panic("%s: failed to map registers\n", __func__);
383 return NULL;
384 }
385
386 ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids);
387 if (!ctx) {
388 panic("%s: unable to allocate ctx\n", __func__);
389 return ctx;
390 }
391
392 if (cmu->pll_clks)
393 samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks,
394 reg_base);
395 if (cmu->mux_clks)
396 samsung_clk_register_mux(ctx, cmu->mux_clks,
397 cmu->nr_mux_clks);
398 if (cmu->div_clks)
399 samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks);
400 if (cmu->gate_clks)
401 samsung_clk_register_gate(ctx, cmu->gate_clks,
402 cmu->nr_gate_clks);
403 if (cmu->fixed_clks)
404 samsung_clk_register_fixed_rate(ctx, cmu->fixed_clks,
405 cmu->nr_fixed_clks);
406 if (cmu->fixed_factor_clks)
407 samsung_clk_register_fixed_factor(ctx, cmu->fixed_factor_clks,
408 cmu->nr_fixed_factor_clks);
409 if (cmu->clk_regs)
410 samsung_clk_sleep_init(reg_base, cmu->clk_regs,
411 cmu->nr_clk_regs);
412
413 samsung_clk_of_add_provider(np, ctx);
414
415 return ctx;
416}