blob: 9cf1230115b176d42d6143232383e685c2b44b7b [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +08001/*
2 * Copyright (c) 2013, Steffen Trumtrar <s.trumtrar@pengutronix.de>
3 *
4 * based on drivers/clk/tegra/clk.h
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 */
16
17#ifndef __SOCFPGA_CLK_H
18#define __SOCFPGA_CLK_H
19
20#include <linux/clk-provider.h>
21
22/* Clock Manager offsets */
23#define CLKMGR_CTRL 0x0
24#define CLKMGR_BYPASS 0x4
25#define CLKMGR_DBCTRL 0x10
26#define CLKMGR_L4SRC 0x70
27#define CLKMGR_PERPLL_SRC 0xAC
28
29#define SOCFPGA_MAX_PARENTS 5
30
31#define streq(a, b) (strcmp((a), (b)) == 0)
32#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
33 ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
34
35#define SYSMGR_SDMMC_CTRL_SET_AS10(smplsel, drvsel) \
36 ((((smplsel) & 0x7) << 4) | (((drvsel) & 0x7) << 0))
37
38extern void __iomem *clk_mgr_base_addr;
39extern void __iomem *clk_mgr_a10_base_addr;
40
41void __init socfpga_pll_init(struct device_node *node);
42void __init socfpga_periph_init(struct device_node *node);
43void __init socfpga_gate_init(struct device_node *node);
44void socfpga_a10_pll_init(struct device_node *node);
45void socfpga_a10_periph_init(struct device_node *node);
46void socfpga_a10_gate_init(struct device_node *node);
47
48struct socfpga_pll {
49 struct clk_gate hw;
50};
51
52struct socfpga_gate_clk {
53 struct clk_gate hw;
54 char *parent_name;
55 u32 fixed_div;
56 void __iomem *div_reg;
57 struct regmap *sys_mgr_base_addr;
58 u32 width; /* only valid if div_reg != 0 */
59 u32 shift; /* only valid if div_reg != 0 */
60 u32 clk_phase[2];
61};
62
63struct socfpga_periph_clk {
64 struct clk_gate hw;
65 char *parent_name;
66 u32 fixed_div;
67 void __iomem *div_reg;
68 u32 width; /* only valid if div_reg != 0 */
69 u32 shift; /* only valid if div_reg != 0 */
70};
71
72#endif /* SOCFPGA_CLK_H */