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192.168.1.100 / T103 / 1f884588077ad3476b9c91cbb0ee9ee0332bbb68 / . / src / kernel / linux / v4.14 / drivers / clk / sunxi-ng / ccu-sun4i-a10.c
blob: a48fde191c0ae0e96824311e10bf590d364f1afb [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +0800[diff] [blame^]1/*
2 * Copyright (c) 2017 Priit Laes <plaes@plaes.org>.
3 * Copyright (c) 2017 Maxime Ripard.
4 * Copyright (c) 2017 Jonathan Liu.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk-provider.h>
17#include <linux/of_address.h>
18
19#include "ccu_common.h"
20#include "ccu_reset.h"
21
22#include "ccu_div.h"
23#include "ccu_gate.h"
24#include "ccu_mp.h"
25#include "ccu_mult.h"
26#include "ccu_nk.h"
27#include "ccu_nkm.h"
28#include "ccu_nkmp.h"
29#include "ccu_nm.h"
30#include "ccu_phase.h"
31
32#include "ccu-sun4i-a10.h"
33
34static struct ccu_nkmp pll_core_clk = {
35 .enable = BIT(31),
36 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
37 .k = _SUNXI_CCU_MULT(4, 2),
38 .m = _SUNXI_CCU_DIV(0, 2),
39 .p = _SUNXI_CCU_DIV(16, 2),
40 .common = {
41 .reg = 0x000,
42 .hw.init = CLK_HW_INIT("pll-core",
43 "hosc",
44 &ccu_nkmp_ops,
45 0),
46 },
47};
48
49/*
50 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
51 * the base (2x, 4x and 8x), and one variable divider (the one true
52 * pll audio).
53 *
54 * We don't have any need for the variable divider for now, so we just
55 * hardcode it to match with the clock names.
56 */
57#define SUN4I_PLL_AUDIO_REG 0x008
58static struct ccu_nm pll_audio_base_clk = {
59 .enable = BIT(31),
60 .n = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
61 .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
62 .common = {
63 .reg = 0x008,
64 .hw.init = CLK_HW_INIT("pll-audio-base",
65 "hosc",
66 &ccu_nm_ops,
67 0),
68 },
69
70};
71
72static struct ccu_mult pll_video0_clk = {
73 .enable = BIT(31),
74 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
75 .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
76 270000000, 297000000),
77 .common = {
78 .reg = 0x010,
79 .features = (CCU_FEATURE_FRACTIONAL |
80 CCU_FEATURE_ALL_PREDIV),
81 .prediv = 8,
82 .hw.init = CLK_HW_INIT("pll-video0",
83 "hosc",
84 &ccu_mult_ops,
85 0),
86 },
87};
88
89static struct ccu_nkmp pll_ve_sun4i_clk = {
90 .enable = BIT(31),
91 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
92 .k = _SUNXI_CCU_MULT(4, 2),
93 .m = _SUNXI_CCU_DIV(0, 2),
94 .p = _SUNXI_CCU_DIV(16, 2),
95 .common = {
96 .reg = 0x018,
97 .hw.init = CLK_HW_INIT("pll-ve",
98 "hosc",
99 &ccu_nkmp_ops,
100 0),
101 },
102};
103
104static struct ccu_nk pll_ve_sun7i_clk = {
105 .enable = BIT(31),
106 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
107 .k = _SUNXI_CCU_MULT(4, 2),
108 .common = {
109 .reg = 0x018,
110 .hw.init = CLK_HW_INIT("pll-ve",
111 "hosc",
112 &ccu_nk_ops,
113 0),
114 },
115};
116
117static struct ccu_nk pll_ddr_base_clk = {
118 .enable = BIT(31),
119 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
120 .k = _SUNXI_CCU_MULT(4, 2),
121 .common = {
122 .reg = 0x020,
123 .hw.init = CLK_HW_INIT("pll-ddr-base",
124 "hosc",
125 &ccu_nk_ops,
126 0),
127 },
128};
129
130static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2,
131 CLK_IS_CRITICAL);
132
133static struct ccu_div pll_ddr_other_clk = {
134 .div = _SUNXI_CCU_DIV_FLAGS(16, 2, CLK_DIVIDER_POWER_OF_TWO),
135 .common = {
136 .reg = 0x020,
137 .hw.init = CLK_HW_INIT("pll-ddr-other", "pll-ddr-base",
138 &ccu_div_ops,
139 0),
140 },
141};
142
143static struct ccu_nk pll_periph_base_clk = {
144 .enable = BIT(31),
145 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
146 .k = _SUNXI_CCU_MULT(4, 2),
147 .common = {
148 .reg = 0x028,
149 .hw.init = CLK_HW_INIT("pll-periph-base",
150 "hosc",
151 &ccu_nk_ops,
152 0),
153 },
154};
155
156static CLK_FIXED_FACTOR(pll_periph_clk, "pll-periph", "pll-periph-base",
157 2, 1, CLK_SET_RATE_PARENT);
158
159/* Not documented on A10 */
160static struct ccu_div pll_periph_sata_clk = {
161 .enable = BIT(14),
162 .div = _SUNXI_CCU_DIV(0, 2),
163 .fixed_post_div = 6,
164 .common = {
165 .reg = 0x028,
166 .features = CCU_FEATURE_FIXED_POSTDIV,
167 .hw.init = CLK_HW_INIT("pll-periph-sata",
168 "pll-periph-base",
169 &ccu_div_ops, 0),
170 },
171};
172
173static struct ccu_mult pll_video1_clk = {
174 .enable = BIT(31),
175 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
176 .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
177 270000000, 297000000),
178 .common = {
179 .reg = 0x030,
180 .features = (CCU_FEATURE_FRACTIONAL |
181 CCU_FEATURE_ALL_PREDIV),
182 .prediv = 8,
183 .hw.init = CLK_HW_INIT("pll-video1",
184 "hosc",
185 &ccu_mult_ops,
186 0),
187 },
188};
189
190/* Not present on A10 */
191static struct ccu_nk pll_gpu_clk = {
192 .enable = BIT(31),
193 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
194 .k = _SUNXI_CCU_MULT(4, 2),
195 .common = {
196 .reg = 0x040,
197 .hw.init = CLK_HW_INIT("pll-gpu",
198 "hosc",
199 &ccu_nk_ops,
200 0),
201 },
202};
203
204static SUNXI_CCU_GATE(hosc_clk, "hosc", "osc24M", 0x050, BIT(0), 0);
205
206static const char *const cpu_parents[] = { "osc32k", "hosc",
207 "pll-core", "pll-periph" };
208static const struct ccu_mux_fixed_prediv cpu_predivs[] = {
209 { .index = 3, .div = 3, },
210};
211
212#define SUN4I_AHB_REG 0x054
213static struct ccu_mux cpu_clk = {
214 .mux = {
215 .shift = 16,
216 .width = 2,
217 .fixed_predivs = cpu_predivs,
218 .n_predivs = ARRAY_SIZE(cpu_predivs),
219 },
220 .common = {
221 .reg = 0x054,
222 .features = CCU_FEATURE_FIXED_PREDIV,
223 .hw.init = CLK_HW_INIT_PARENTS("cpu",
224 cpu_parents,
225 &ccu_mux_ops,
226 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
227 }
228};
229
230static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x054, 0, 2, 0);
231
232static struct ccu_div ahb_sun4i_clk = {
233 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
234 .common = {
235 .reg = 0x054,
236 .hw.init = CLK_HW_INIT("ahb", "axi", &ccu_div_ops, 0),
237 },
238};
239
240static const char *const ahb_sun7i_parents[] = { "axi", "pll-periph",
241 "pll-periph" };
242static const struct ccu_mux_fixed_prediv ahb_sun7i_predivs[] = {
243 { .index = 1, .div = 2, },
244 { /* Sentinel */ },
245};
246static struct ccu_div ahb_sun7i_clk = {
247 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
248 .mux = {
249 .shift = 6,
250 .width = 2,
251 .fixed_predivs = ahb_sun7i_predivs,
252 .n_predivs = ARRAY_SIZE(ahb_sun7i_predivs),
253 },
254
255 .common = {
256 .reg = 0x054,
257 .hw.init = CLK_HW_INIT_PARENTS("ahb",
258 ahb_sun7i_parents,
259 &ccu_div_ops,
260 0),
261 },
262};
263
264static struct clk_div_table apb0_div_table[] = {
265 { .val = 0, .div = 2 },
266 { .val = 1, .div = 2 },
267 { .val = 2, .div = 4 },
268 { .val = 3, .div = 8 },
269 { /* Sentinel */ },
270};
271static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
272 0x054, 8, 2, apb0_div_table, 0);
273
274static const char *const apb1_parents[] = { "hosc", "pll-periph", "osc32k" };
275static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x058,
276 0, 5, /* M */
277 16, 2, /* P */
278 24, 2, /* mux */
279 0);
280
281/* Not present on A20 */
282static SUNXI_CCU_GATE(axi_dram_clk, "axi-dram", "ahb",
283 0x05c, BIT(31), 0);
284
285static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb",
286 0x060, BIT(0), 0);
287static SUNXI_CCU_GATE(ahb_ehci0_clk, "ahb-ehci0", "ahb",
288 0x060, BIT(1), 0);
289static SUNXI_CCU_GATE(ahb_ohci0_clk, "ahb-ohci0", "ahb",
290 0x060, BIT(2), 0);
291static SUNXI_CCU_GATE(ahb_ehci1_clk, "ahb-ehci1", "ahb",
292 0x060, BIT(3), 0);
293static SUNXI_CCU_GATE(ahb_ohci1_clk, "ahb-ohci1", "ahb",
294 0x060, BIT(4), 0);
295static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
296 0x060, BIT(5), 0);
297static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",
298 0x060, BIT(6), 0);
299static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
300 0x060, BIT(7), 0);
301static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
302 0x060, BIT(8), 0);
303static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
304 0x060, BIT(9), 0);
305static SUNXI_CCU_GATE(ahb_mmc2_clk, "ahb-mmc2", "ahb",
306 0x060, BIT(10), 0);
307static SUNXI_CCU_GATE(ahb_mmc3_clk, "ahb-mmc3", "ahb",
308 0x060, BIT(11), 0);
309static SUNXI_CCU_GATE(ahb_ms_clk, "ahb-ms", "ahb",
310 0x060, BIT(12), 0);
311static SUNXI_CCU_GATE(ahb_nand_clk, "ahb-nand", "ahb",
312 0x060, BIT(13), 0);
313static SUNXI_CCU_GATE(ahb_sdram_clk, "ahb-sdram", "ahb",
314 0x060, BIT(14), CLK_IS_CRITICAL);
315
316static SUNXI_CCU_GATE(ahb_ace_clk, "ahb-ace", "ahb",
317 0x060, BIT(16), 0);
318static SUNXI_CCU_GATE(ahb_emac_clk, "ahb-emac", "ahb",
319 0x060, BIT(17), 0);
320static SUNXI_CCU_GATE(ahb_ts_clk, "ahb-ts", "ahb",
321 0x060, BIT(18), 0);
322static SUNXI_CCU_GATE(ahb_spi0_clk, "ahb-spi0", "ahb",
323 0x060, BIT(20), 0);
324static SUNXI_CCU_GATE(ahb_spi1_clk, "ahb-spi1", "ahb",
325 0x060, BIT(21), 0);
326static SUNXI_CCU_GATE(ahb_spi2_clk, "ahb-spi2", "ahb",
327 0x060, BIT(22), 0);
328static SUNXI_CCU_GATE(ahb_spi3_clk, "ahb-spi3", "ahb",
329 0x060, BIT(23), 0);
330static SUNXI_CCU_GATE(ahb_pata_clk, "ahb-pata", "ahb",
331 0x060, BIT(24), 0);
332/* Not documented on A20 */
333static SUNXI_CCU_GATE(ahb_sata_clk, "ahb-sata", "ahb",
334 0x060, BIT(25), 0);
335/* Not present on A20 */
336static SUNXI_CCU_GATE(ahb_gps_clk, "ahb-gps", "ahb",
337 0x060, BIT(26), 0);
338/* Not present on A10 */
339static SUNXI_CCU_GATE(ahb_hstimer_clk, "ahb-hstimer", "ahb",
340 0x060, BIT(28), 0);
341
342static SUNXI_CCU_GATE(ahb_ve_clk, "ahb-ve", "ahb",
343 0x064, BIT(0), 0);
344static SUNXI_CCU_GATE(ahb_tvd_clk, "ahb-tvd", "ahb",
345 0x064, BIT(1), 0);
346static SUNXI_CCU_GATE(ahb_tve0_clk, "ahb-tve0", "ahb",
347 0x064, BIT(2), 0);
348static SUNXI_CCU_GATE(ahb_tve1_clk, "ahb-tve1", "ahb",
349 0x064, BIT(3), 0);
350static SUNXI_CCU_GATE(ahb_lcd0_clk, "ahb-lcd0", "ahb",
351 0x064, BIT(4), 0);
352static SUNXI_CCU_GATE(ahb_lcd1_clk, "ahb-lcd1", "ahb",
353 0x064, BIT(5), 0);
354static SUNXI_CCU_GATE(ahb_csi0_clk, "ahb-csi0", "ahb",
355 0x064, BIT(8), 0);
356static SUNXI_CCU_GATE(ahb_csi1_clk, "ahb-csi1", "ahb",
357 0x064, BIT(9), 0);
358/* Not present on A10 */
359static SUNXI_CCU_GATE(ahb_hdmi1_clk, "ahb-hdmi1", "ahb",
360 0x064, BIT(10), 0);
361static SUNXI_CCU_GATE(ahb_hdmi0_clk, "ahb-hdmi0", "ahb",
362 0x064, BIT(11), 0);
363static SUNXI_CCU_GATE(ahb_de_be0_clk, "ahb-de-be0", "ahb",
364 0x064, BIT(12), 0);
365static SUNXI_CCU_GATE(ahb_de_be1_clk, "ahb-de-be1", "ahb",
366 0x064, BIT(13), 0);
367static SUNXI_CCU_GATE(ahb_de_fe0_clk, "ahb-de-fe0", "ahb",
368 0x064, BIT(14), 0);
369static SUNXI_CCU_GATE(ahb_de_fe1_clk, "ahb-de-fe1", "ahb",
370 0x064, BIT(15), 0);
371/* Not present on A10 */
372static SUNXI_CCU_GATE(ahb_gmac_clk, "ahb-gmac", "ahb",
373 0x064, BIT(17), 0);
374static SUNXI_CCU_GATE(ahb_mp_clk, "ahb-mp", "ahb",
375 0x064, BIT(18), 0);
376static SUNXI_CCU_GATE(ahb_gpu_clk, "ahb-gpu", "ahb",
377 0x064, BIT(20), 0);
378
379static SUNXI_CCU_GATE(apb0_codec_clk, "apb0-codec", "apb0",
380 0x068, BIT(0), 0);
381static SUNXI_CCU_GATE(apb0_spdif_clk, "apb0-spdif", "apb0",
382 0x068, BIT(1), 0);
383static SUNXI_CCU_GATE(apb0_ac97_clk, "apb0-ac97", "apb0",
384 0x068, BIT(2), 0);
385static SUNXI_CCU_GATE(apb0_i2s0_clk, "apb0-i2s0", "apb0",
386 0x068, BIT(3), 0);
387/* Not present on A10 */
388static SUNXI_CCU_GATE(apb0_i2s1_clk, "apb0-i2s1", "apb0",
389 0x068, BIT(4), 0);
390static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0",
391 0x068, BIT(5), 0);
392static SUNXI_CCU_GATE(apb0_ir0_clk, "apb0-ir0", "apb0",
393 0x068, BIT(6), 0);
394static SUNXI_CCU_GATE(apb0_ir1_clk, "apb0-ir1", "apb0",
395 0x068, BIT(7), 0);
396/* Not present on A10 */
397static SUNXI_CCU_GATE(apb0_i2s2_clk, "apb0-i2s2", "apb0",
398 0x068, BIT(8), 0);
399static SUNXI_CCU_GATE(apb0_keypad_clk, "apb0-keypad", "apb0",
400 0x068, BIT(10), 0);
401
402static SUNXI_CCU_GATE(apb1_i2c0_clk, "apb1-i2c0", "apb1",
403 0x06c, BIT(0), 0);
404static SUNXI_CCU_GATE(apb1_i2c1_clk, "apb1-i2c1", "apb1",
405 0x06c, BIT(1), 0);
406static SUNXI_CCU_GATE(apb1_i2c2_clk, "apb1-i2c2", "apb1",
407 0x06c, BIT(2), 0);
408/* Not present on A10 */
409static SUNXI_CCU_GATE(apb1_i2c3_clk, "apb1-i2c3", "apb1",
410 0x06c, BIT(3), 0);
411static SUNXI_CCU_GATE(apb1_can_clk, "apb1-can", "apb1",
412 0x06c, BIT(4), 0);
413static SUNXI_CCU_GATE(apb1_scr_clk, "apb1-scr", "apb1",
414 0x06c, BIT(5), 0);
415static SUNXI_CCU_GATE(apb1_ps20_clk, "apb1-ps20", "apb1",
416 0x06c, BIT(6), 0);
417static SUNXI_CCU_GATE(apb1_ps21_clk, "apb1-ps21", "apb1",
418 0x06c, BIT(7), 0);
419/* Not present on A10 */
420static SUNXI_CCU_GATE(apb1_i2c4_clk, "apb1-i2c4", "apb1",
421 0x06c, BIT(15), 0);
422static SUNXI_CCU_GATE(apb1_uart0_clk, "apb1-uart0", "apb1",
423 0x06c, BIT(16), 0);
424static SUNXI_CCU_GATE(apb1_uart1_clk, "apb1-uart1", "apb1",
425 0x06c, BIT(17), 0);
426static SUNXI_CCU_GATE(apb1_uart2_clk, "apb1-uart2", "apb1",
427 0x06c, BIT(18), 0);
428static SUNXI_CCU_GATE(apb1_uart3_clk, "apb1-uart3", "apb1",
429 0x06c, BIT(19), 0);
430static SUNXI_CCU_GATE(apb1_uart4_clk, "apb1-uart4", "apb1",
431 0x06c, BIT(20), 0);
432static SUNXI_CCU_GATE(apb1_uart5_clk, "apb1-uart5", "apb1",
433 0x06c, BIT(21), 0);
434static SUNXI_CCU_GATE(apb1_uart6_clk, "apb1-uart6", "apb1",
435 0x06c, BIT(22), 0);
436static SUNXI_CCU_GATE(apb1_uart7_clk, "apb1-uart7", "apb1",
437 0x06c, BIT(23), 0);
438
439static const char *const mod0_default_parents[] = { "hosc", "pll-periph",
440 "pll-ddr-other" };
441static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
442 0, 4, /* M */
443 16, 2, /* P */
444 24, 2, /* mux */
445 BIT(31), /* gate */
446 0);
447
448/* Undocumented on A10 */
449static SUNXI_CCU_MP_WITH_MUX_GATE(ms_clk, "ms", mod0_default_parents, 0x084,
450 0, 4, /* M */
451 16, 2, /* P */
452 24, 2, /* mux */
453 BIT(31), /* gate */
454 0);
455
456static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
457 0, 4, /* M */
458 16, 2, /* P */
459 24, 2, /* mux */
460 BIT(31), /* gate */
461 0);
462
463/* MMC output and sample clocks are not present on A10 */
464static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
465 0x088, 8, 3, 0);
466static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
467 0x088, 20, 3, 0);
468
469static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
470 0, 4, /* M */
471 16, 2, /* P */
472 24, 2, /* mux */
473 BIT(31), /* gate */
474 0);
475
476/* MMC output and sample clocks are not present on A10 */
477static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
478 0x08c, 8, 3, 0);
479static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
480 0x08c, 20, 3, 0);
481
482static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
483 0, 4, /* M */
484 16, 2, /* P */
485 24, 2, /* mux */
486 BIT(31), /* gate */
487 0);
488
489/* MMC output and sample clocks are not present on A10 */
490static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
491 0x090, 8, 3, 0);
492static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
493 0x090, 20, 3, 0);
494
495static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094,
496 0, 4, /* M */
497 16, 2, /* P */
498 24, 2, /* mux */
499 BIT(31), /* gate */
500 0);
501
502/* MMC output and sample clocks are not present on A10 */
503static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3_output", "mmc3",
504 0x094, 8, 3, 0);
505static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3_sample", "mmc3",
506 0x094, 20, 3, 0);
507
508static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
509 0, 4, /* M */
510 16, 2, /* P */
511 24, 2, /* mux */
512 BIT(31), /* gate */
513 0);
514
515static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
516 0, 4, /* M */
517 16, 2, /* P */
518 24, 2, /* mux */
519 BIT(31), /* gate */
520 0);
521
522static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
523 0, 4, /* M */
524 16, 2, /* P */
525 24, 2, /* mux */
526 BIT(31), /* gate */
527 0);
528
529static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
530 0, 4, /* M */
531 16, 2, /* P */
532 24, 2, /* mux */
533 BIT(31), /* gate */
534 0);
535
536static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
537 0, 4, /* M */
538 16, 2, /* P */
539 24, 2, /* mux */
540 BIT(31), /* gate */
541 0);
542
543/* Undocumented on A10 */
544static SUNXI_CCU_MP_WITH_MUX_GATE(pata_clk, "pata", mod0_default_parents, 0x0ac,
545 0, 4, /* M */
546 16, 2, /* P */
547 24, 2, /* mux */
548 BIT(31), /* gate */
549 0);
550
551/* TODO: Check whether A10 actually supports osc32k as 4th parent? */
552static const char *const ir_parents_sun4i[] = { "hosc", "pll-periph",
553 "pll-ddr-other" };
554static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_sun4i_clk, "ir0", ir_parents_sun4i, 0x0b0,
555 0, 4, /* M */
556 16, 2, /* P */
557 24, 2, /* mux */
558 BIT(31), /* gate */
559 0);
560
561static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_sun4i_clk, "ir1", ir_parents_sun4i, 0x0b4,
562 0, 4, /* M */
563 16, 2, /* P */
564 24, 2, /* mux */
565 BIT(31), /* gate */
566 0);
567static const char *const ir_parents_sun7i[] = { "hosc", "pll-periph",
568 "pll-ddr-other", "osc32k" };
569static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_sun7i_clk, "ir0", ir_parents_sun7i, 0x0b0,
570 0, 4, /* M */
571 16, 2, /* P */
572 24, 2, /* mux */
573 BIT(31), /* gate */
574 0);
575
576static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_sun7i_clk, "ir1", ir_parents_sun7i, 0x0b4,
577 0, 4, /* M */
578 16, 2, /* P */
579 24, 2, /* mux */
580 BIT(31), /* gate */
581 0);
582
583static const char *const audio_parents[] = { "pll-audio-8x", "pll-audio-4x",
584 "pll-audio-2x", "pll-audio" };
585static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", audio_parents,
586 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
587
588static SUNXI_CCU_MUX_WITH_GATE(ac97_clk, "ac97", audio_parents,
589 0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
590
591/* Undocumented on A10 */
592static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", audio_parents,
593 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
594
595static const char *const keypad_parents[] = { "hosc", "losc"};
596static const u8 keypad_table[] = { 0, 2 };
597static struct ccu_mp keypad_clk = {
598 .enable = BIT(31),
599 .m = _SUNXI_CCU_DIV(0, 5),
600 .p = _SUNXI_CCU_DIV(16, 2),
601 .mux = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
602 .common = {
603 .reg = 0x0c4,
604 .hw.init = CLK_HW_INIT_PARENTS("keypad",
605 keypad_parents,
606 &ccu_mp_ops,
607 0),
608 },
609};
610
611/*
612 * SATA supports external clock as parent via BIT(24) and is probably an
613 * optional crystal or oscillator that can be connected to the
614 * SATA-CLKM / SATA-CLKP pins.
615 */
616static const char *const sata_parents[] = {"pll-periph-sata", "sata-ext"};
617static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents,
618 0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT);
619
620
621static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "pll-periph",
622 0x0cc, BIT(6), 0);
623static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "pll-periph",
624 0x0cc, BIT(7), 0);
625static SUNXI_CCU_GATE(usb_phy_clk, "usb-phy", "pll-periph",
626 0x0cc, BIT(8), 0);
627
628/* TODO: GPS CLK 0x0d0 */
629
630static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0d4,
631 0, 4, /* M */
632 16, 2, /* P */
633 24, 2, /* mux */
634 BIT(31), /* gate */
635 0);
636
637/* Not present on A10 */
638static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", audio_parents,
639 0x0d8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
640
641/* Not present on A10 */
642static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", audio_parents,
643 0x0dc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
644
645static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
646 0x100, BIT(0), 0);
647static SUNXI_CCU_GATE(dram_csi0_clk, "dram-csi0", "pll-ddr",
648 0x100, BIT(1), 0);
649static SUNXI_CCU_GATE(dram_csi1_clk, "dram-csi1", "pll-ddr",
650 0x100, BIT(2), 0);
651static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "pll-ddr",
652 0x100, BIT(3), 0);
653static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "pll-ddr",
654 0x100, BIT(4), 0);
655static SUNXI_CCU_GATE(dram_tve0_clk, "dram-tve0", "pll-ddr",
656 0x100, BIT(5), 0);
657static SUNXI_CCU_GATE(dram_tve1_clk, "dram-tve1", "pll-ddr",
658 0x100, BIT(6), 0);
659
660/* Clock seems to be critical only on sun4i */
661static SUNXI_CCU_GATE(dram_out_clk, "dram-out", "pll-ddr",
662 0x100, BIT(15), CLK_IS_CRITICAL);
663static SUNXI_CCU_GATE(dram_de_fe1_clk, "dram-de-fe1", "pll-ddr",
664 0x100, BIT(24), 0);
665static SUNXI_CCU_GATE(dram_de_fe0_clk, "dram-de-fe0", "pll-ddr",
666 0x100, BIT(25), 0);
667static SUNXI_CCU_GATE(dram_de_be0_clk, "dram-de-be0", "pll-ddr",
668 0x100, BIT(26), 0);
669static SUNXI_CCU_GATE(dram_de_be1_clk, "dram-de-be1", "pll-ddr",
670 0x100, BIT(27), 0);
671static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "pll-ddr",
672 0x100, BIT(28), 0);
673static SUNXI_CCU_GATE(dram_ace_clk, "dram-ace", "pll-ddr",
674 0x100, BIT(29), 0);
675
676static const char *const de_parents[] = { "pll-video0", "pll-video1",
677 "pll-ddr-other" };
678static SUNXI_CCU_M_WITH_MUX_GATE(de_be0_clk, "de-be0", de_parents,
679 0x104, 0, 4, 24, 2, BIT(31), 0);
680
681static SUNXI_CCU_M_WITH_MUX_GATE(de_be1_clk, "de-be1", de_parents,
682 0x108, 0, 4, 24, 2, BIT(31), 0);
683
684static SUNXI_CCU_M_WITH_MUX_GATE(de_fe0_clk, "de-fe0", de_parents,
685 0x10c, 0, 4, 24, 2, BIT(31), 0);
686
687static SUNXI_CCU_M_WITH_MUX_GATE(de_fe1_clk, "de-fe1", de_parents,
688 0x110, 0, 4, 24, 2, BIT(31), 0);
689
690/* Undocumented on A10 */
691static SUNXI_CCU_M_WITH_MUX_GATE(de_mp_clk, "de-mp", de_parents,
692 0x114, 0, 4, 24, 2, BIT(31), 0);
693
694static const char *const disp_parents[] = { "pll-video0", "pll-video1",
695 "pll-video0-2x", "pll-video1-2x" };
696static SUNXI_CCU_MUX_WITH_GATE(tcon0_ch0_clk, "tcon0-ch0-sclk", disp_parents,
697 0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
698static SUNXI_CCU_MUX_WITH_GATE(tcon1_ch0_clk, "tcon1-ch0-sclk", disp_parents,
699 0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
700
701static const char *const csi_sclk_parents[] = { "pll-video0", "pll-ve",
702 "pll-ddr-other", "pll-periph" };
703
704static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk",
705 csi_sclk_parents,
706 0x120, 0, 4, 24, 2, BIT(31), 0);
707
708/* TVD clock setup for A10 */
709static const char *const tvd_parents[] = { "pll-video0", "pll-video1" };
710static SUNXI_CCU_MUX_WITH_GATE(tvd_sun4i_clk, "tvd", tvd_parents,
711 0x128, 24, 1, BIT(31), 0);
712
713/* TVD clock setup for A20 */
714static SUNXI_CCU_MP_WITH_MUX_GATE(tvd_sclk2_sun7i_clk,
715 "tvd-sclk2", tvd_parents,
716 0x128,
717 0, 4, /* M */
718 16, 4, /* P */
719 8, 1, /* mux */
720 BIT(15), /* gate */
721 0);
722
723static SUNXI_CCU_M_WITH_GATE(tvd_sclk1_sun7i_clk, "tvd-sclk1", "tvd-sclk2",
724 0x128, 0, 4, BIT(31), 0);
725
726static SUNXI_CCU_M_WITH_MUX_GATE(tcon0_ch1_sclk2_clk, "tcon0-ch1-sclk2",
727 disp_parents,
728 0x12c, 0, 4, 24, 2, BIT(31),
729 CLK_SET_RATE_PARENT);
730
731static SUNXI_CCU_M_WITH_GATE(tcon0_ch1_clk,
732 "tcon0-ch1-sclk1", "tcon0-ch1-sclk2",
733 0x12c, 11, 1, BIT(15),
734 CLK_SET_RATE_PARENT);
735
736static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_ch1_sclk2_clk, "tcon1-ch1-sclk2",
737 disp_parents,
738 0x130, 0, 4, 24, 2, BIT(31),
739 CLK_SET_RATE_PARENT);
740
741static SUNXI_CCU_M_WITH_GATE(tcon1_ch1_clk,
742 "tcon1-ch1-sclk1", "tcon1-ch1-sclk2",
743 0x130, 11, 1, BIT(15),
744 CLK_SET_RATE_PARENT);
745
746static const char *const csi_parents[] = { "hosc", "pll-video0", "pll-video1",
747 "pll-video0-2x", "pll-video1-2x"};
748static const u8 csi_table[] = { 0, 1, 2, 5, 6};
749static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi0_clk, "csi0",
750 csi_parents, csi_table,
751 0x134, 0, 5, 24, 3, BIT(31), 0);
752
753static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi1_clk, "csi1",
754 csi_parents, csi_table,
755 0x138, 0, 5, 24, 3, BIT(31), 0);
756
757static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c, 16, 8, BIT(31), 0);
758
759static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
760 0x140, BIT(31), CLK_SET_RATE_PARENT);
761
762static SUNXI_CCU_GATE(avs_clk, "avs", "hosc", 0x144, BIT(31), 0);
763
764static const char *const ace_parents[] = { "pll-ve", "pll-ddr-other" };
765static SUNXI_CCU_M_WITH_MUX_GATE(ace_clk, "ace", ace_parents,
766 0x148, 0, 4, 24, 1, BIT(31), 0);
767
768static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", disp_parents,
769 0x150, 0, 4, 24, 2, BIT(31),
770 CLK_SET_RATE_PARENT);
771
772static const char *const gpu_parents_sun4i[] = { "pll-video0", "pll-ve",
773 "pll-ddr-other",
774 "pll-video1" };
775static SUNXI_CCU_M_WITH_MUX_GATE(gpu_sun4i_clk, "gpu", gpu_parents_sun4i,
776 0x154, 0, 4, 24, 2, BIT(31),
777 CLK_SET_RATE_PARENT);
778
779static const char *const gpu_parents_sun7i[] = { "pll-video0", "pll-ve",
780 "pll-ddr-other", "pll-video1",
781 "pll-gpu" };
782static const u8 gpu_table_sun7i[] = { 0, 1, 2, 3, 4 };
783static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(gpu_sun7i_clk, "gpu",
784 gpu_parents_sun7i, gpu_table_sun7i,
785 0x154, 0, 4, 24, 3, BIT(31),
786 CLK_SET_RATE_PARENT);
787
788static const char *const mbus_sun4i_parents[] = { "hosc", "pll-periph",
789 "pll-ddr-other" };
790static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_sun4i_clk, "mbus", mbus_sun4i_parents,
791 0x15c, 0, 4, 16, 2, 24, 2, BIT(31),
792 0);
793static const char *const mbus_sun7i_parents[] = { "hosc", "pll-periph-base",
794 "pll-ddr-other" };
795static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_sun7i_clk, "mbus", mbus_sun7i_parents,
796 0x15c, 0, 4, 16, 2, 24, 2, BIT(31),
797 CLK_IS_CRITICAL);
798
799static SUNXI_CCU_GATE(hdmi1_slow_clk, "hdmi1-slow", "hosc", 0x178, BIT(31), 0);
800
801static const char *const hdmi1_parents[] = { "pll-video0", "pll-video1" };
802static const u8 hdmi1_table[] = { 0, 1};
803static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(hdmi1_clk, "hdmi1",
804 hdmi1_parents, hdmi1_table,
805 0x17c, 0, 4, 24, 2, BIT(31),
806 CLK_SET_RATE_PARENT);
807
808static const char *const out_parents[] = { "hosc", "osc32k", "hosc" };
809static const struct ccu_mux_fixed_prediv clk_out_predivs[] = {
810 { .index = 0, .div = 750, },
811};
812
813static struct ccu_mp out_a_clk = {
814 .enable = BIT(31),
815 .m = _SUNXI_CCU_DIV(8, 5),
816 .p = _SUNXI_CCU_DIV(20, 2),
817 .mux = {
818 .shift = 24,
819 .width = 2,
820 .fixed_predivs = clk_out_predivs,
821 .n_predivs = ARRAY_SIZE(clk_out_predivs),
822 },
823 .common = {
824 .reg = 0x1f0,
825 .features = CCU_FEATURE_FIXED_PREDIV,
826 .hw.init = CLK_HW_INIT_PARENTS("out-a",
827 out_parents,
828 &ccu_mp_ops,
829 0),
830 },
831};
832static struct ccu_mp out_b_clk = {
833 .enable = BIT(31),
834 .m = _SUNXI_CCU_DIV(8, 5),
835 .p = _SUNXI_CCU_DIV(20, 2),
836 .mux = {
837 .shift = 24,
838 .width = 2,
839 .fixed_predivs = clk_out_predivs,
840 .n_predivs = ARRAY_SIZE(clk_out_predivs),
841 },
842 .common = {
843 .reg = 0x1f4,
844 .features = CCU_FEATURE_FIXED_PREDIV,
845 .hw.init = CLK_HW_INIT_PARENTS("out-b",
846 out_parents,
847 &ccu_mp_ops,
848 0),
849 },
850};
851
852static struct ccu_common *sun4i_sun7i_ccu_clks[] = {
853 &hosc_clk.common,
854 &pll_core_clk.common,
855 &pll_audio_base_clk.common,
856 &pll_video0_clk.common,
857 &pll_ve_sun4i_clk.common,
858 &pll_ve_sun7i_clk.common,
859 &pll_ddr_base_clk.common,
860 &pll_ddr_clk.common,
861 &pll_ddr_other_clk.common,
862 &pll_periph_base_clk.common,
863 &pll_periph_sata_clk.common,
864 &pll_video1_clk.common,
865 &pll_gpu_clk.common,
866 &cpu_clk.common,
867 &axi_clk.common,
868 &axi_dram_clk.common,
869 &ahb_sun4i_clk.common,
870 &ahb_sun7i_clk.common,
871 &apb0_clk.common,
872 &apb1_clk.common,
873 &ahb_otg_clk.common,
874 &ahb_ehci0_clk.common,
875 &ahb_ohci0_clk.common,
876 &ahb_ehci1_clk.common,
877 &ahb_ohci1_clk.common,
878 &ahb_ss_clk.common,
879 &ahb_dma_clk.common,
880 &ahb_bist_clk.common,
881 &ahb_mmc0_clk.common,
882 &ahb_mmc1_clk.common,
883 &ahb_mmc2_clk.common,
884 &ahb_mmc3_clk.common,
885 &ahb_ms_clk.common,
886 &ahb_nand_clk.common,
887 &ahb_sdram_clk.common,
888 &ahb_ace_clk.common,
889 &ahb_emac_clk.common,
890 &ahb_ts_clk.common,
891 &ahb_spi0_clk.common,
892 &ahb_spi1_clk.common,
893 &ahb_spi2_clk.common,
894 &ahb_spi3_clk.common,
895 &ahb_pata_clk.common,
896 &ahb_sata_clk.common,
897 &ahb_gps_clk.common,
898 &ahb_hstimer_clk.common,
899 &ahb_ve_clk.common,
900 &ahb_tvd_clk.common,
901 &ahb_tve0_clk.common,
902 &ahb_tve1_clk.common,
903 &ahb_lcd0_clk.common,
904 &ahb_lcd1_clk.common,
905 &ahb_csi0_clk.common,
906 &ahb_csi1_clk.common,
907 &ahb_hdmi1_clk.common,
908 &ahb_hdmi0_clk.common,
909 &ahb_de_be0_clk.common,
910 &ahb_de_be1_clk.common,
911 &ahb_de_fe0_clk.common,
912 &ahb_de_fe1_clk.common,
913 &ahb_gmac_clk.common,
914 &ahb_mp_clk.common,
915 &ahb_gpu_clk.common,
916 &apb0_codec_clk.common,
917 &apb0_spdif_clk.common,
918 &apb0_ac97_clk.common,
919 &apb0_i2s0_clk.common,
920 &apb0_i2s1_clk.common,
921 &apb0_pio_clk.common,
922 &apb0_ir0_clk.common,
923 &apb0_ir1_clk.common,
924 &apb0_i2s2_clk.common,
925 &apb0_keypad_clk.common,
926 &apb1_i2c0_clk.common,
927 &apb1_i2c1_clk.common,
928 &apb1_i2c2_clk.common,
929 &apb1_i2c3_clk.common,
930 &apb1_can_clk.common,
931 &apb1_scr_clk.common,
932 &apb1_ps20_clk.common,
933 &apb1_ps21_clk.common,
934 &apb1_i2c4_clk.common,
935 &apb1_uart0_clk.common,
936 &apb1_uart1_clk.common,
937 &apb1_uart2_clk.common,
938 &apb1_uart3_clk.common,
939 &apb1_uart4_clk.common,
940 &apb1_uart5_clk.common,
941 &apb1_uart6_clk.common,
942 &apb1_uart7_clk.common,
943 &nand_clk.common,
944 &ms_clk.common,
945 &mmc0_clk.common,
946 &mmc0_output_clk.common,
947 &mmc0_sample_clk.common,
948 &mmc1_clk.common,
949 &mmc1_output_clk.common,
950 &mmc1_sample_clk.common,
951 &mmc2_clk.common,
952 &mmc2_output_clk.common,
953 &mmc2_sample_clk.common,
954 &mmc3_clk.common,
955 &mmc3_output_clk.common,
956 &mmc3_sample_clk.common,
957 &ts_clk.common,
958 &ss_clk.common,
959 &spi0_clk.common,
960 &spi1_clk.common,
961 &spi2_clk.common,
962 &pata_clk.common,
963 &ir0_sun4i_clk.common,
964 &ir1_sun4i_clk.common,
965 &ir0_sun7i_clk.common,
966 &ir1_sun7i_clk.common,
967 &i2s0_clk.common,
968 &ac97_clk.common,
969 &spdif_clk.common,
970 &keypad_clk.common,
971 &sata_clk.common,
972 &usb_ohci0_clk.common,
973 &usb_ohci1_clk.common,
974 &usb_phy_clk.common,
975 &spi3_clk.common,
976 &i2s1_clk.common,
977 &i2s2_clk.common,
978 &dram_ve_clk.common,
979 &dram_csi0_clk.common,
980 &dram_csi1_clk.common,
981 &dram_ts_clk.common,
982 &dram_tvd_clk.common,
983 &dram_tve0_clk.common,
984 &dram_tve1_clk.common,
985 &dram_out_clk.common,
986 &dram_de_fe1_clk.common,
987 &dram_de_fe0_clk.common,
988 &dram_de_be0_clk.common,
989 &dram_de_be1_clk.common,
990 &dram_mp_clk.common,
991 &dram_ace_clk.common,
992 &de_be0_clk.common,
993 &de_be1_clk.common,
994 &de_fe0_clk.common,
995 &de_fe1_clk.common,
996 &de_mp_clk.common,
997 &tcon0_ch0_clk.common,
998 &tcon1_ch0_clk.common,
999 &csi_sclk_clk.common,
1000 &tvd_sun4i_clk.common,
1001 &tvd_sclk1_sun7i_clk.common,
1002 &tvd_sclk2_sun7i_clk.common,
1003 &tcon0_ch1_sclk2_clk.common,
1004 &tcon0_ch1_clk.common,
1005 &tcon1_ch1_sclk2_clk.common,
1006 &tcon1_ch1_clk.common,
1007 &csi0_clk.common,
1008 &csi1_clk.common,
1009 &ve_clk.common,
1010 &codec_clk.common,
1011 &avs_clk.common,
1012 &ace_clk.common,
1013 &hdmi_clk.common,
1014 &gpu_sun4i_clk.common,
1015 &gpu_sun7i_clk.common,
1016 &mbus_sun4i_clk.common,
1017 &mbus_sun7i_clk.common,
1018 &hdmi1_slow_clk.common,
1019 &hdmi1_clk.common,
1020 &out_a_clk.common,
1021 &out_b_clk.common
1022};
1023
1024/* Post-divider for pll-audio is hardcoded to 4 */
1025static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
1026 "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
1027static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
1028 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
1029static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
1030 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
1031static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
1032 "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
1033static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
1034 "pll-video0", 1, 2, CLK_SET_RATE_PARENT);
1035static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
1036 "pll-video1", 1, 2, CLK_SET_RATE_PARENT);
1037
1038
1039static struct clk_hw_onecell_data sun4i_a10_hw_clks = {
1040 .hws = {
1041 [CLK_HOSC] = &hosc_clk.common.hw,
1042 [CLK_PLL_CORE] = &pll_core_clk.common.hw,
1043 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
1044 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
1045 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
1046 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
1047 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
1048 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
1049 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
1050 [CLK_PLL_VE] = &pll_ve_sun4i_clk.common.hw,
1051 [CLK_PLL_DDR_BASE] = &pll_ddr_base_clk.common.hw,
1052 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
1053 [CLK_PLL_DDR_OTHER] = &pll_ddr_other_clk.common.hw,
1054 [CLK_PLL_PERIPH_BASE] = &pll_periph_base_clk.common.hw,
1055 [CLK_PLL_PERIPH] = &pll_periph_clk.hw,
1056 [CLK_PLL_PERIPH_SATA] = &pll_periph_sata_clk.common.hw,
1057 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
1058 [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
1059 [CLK_CPU] = &cpu_clk.common.hw,
1060 [CLK_AXI] = &axi_clk.common.hw,
1061 [CLK_AXI_DRAM] = &axi_dram_clk.common.hw,
1062 [CLK_AHB] = &ahb_sun4i_clk.common.hw,
1063 [CLK_APB0] = &apb0_clk.common.hw,
1064 [CLK_APB1] = &apb1_clk.common.hw,
1065 [CLK_AHB_OTG] = &ahb_otg_clk.common.hw,
1066 [CLK_AHB_EHCI0] = &ahb_ehci0_clk.common.hw,
1067 [CLK_AHB_OHCI0] = &ahb_ohci0_clk.common.hw,
1068 [CLK_AHB_EHCI1] = &ahb_ehci1_clk.common.hw,
1069 [CLK_AHB_OHCI1] = &ahb_ohci1_clk.common.hw,
1070 [CLK_AHB_SS] = &ahb_ss_clk.common.hw,
1071 [CLK_AHB_DMA] = &ahb_dma_clk.common.hw,
1072 [CLK_AHB_BIST] = &ahb_bist_clk.common.hw,
1073 [CLK_AHB_MMC0] = &ahb_mmc0_clk.common.hw,
1074 [CLK_AHB_MMC1] = &ahb_mmc1_clk.common.hw,
1075 [CLK_AHB_MMC2] = &ahb_mmc2_clk.common.hw,
1076 [CLK_AHB_MMC3] = &ahb_mmc3_clk.common.hw,
1077 [CLK_AHB_MS] = &ahb_ms_clk.common.hw,
1078 [CLK_AHB_NAND] = &ahb_nand_clk.common.hw,
1079 [CLK_AHB_SDRAM] = &ahb_sdram_clk.common.hw,
1080 [CLK_AHB_ACE] = &ahb_ace_clk.common.hw,
1081 [CLK_AHB_EMAC] = &ahb_emac_clk.common.hw,
1082 [CLK_AHB_TS] = &ahb_ts_clk.common.hw,
1083 [CLK_AHB_SPI0] = &ahb_spi0_clk.common.hw,
1084 [CLK_AHB_SPI1] = &ahb_spi1_clk.common.hw,
1085 [CLK_AHB_SPI2] = &ahb_spi2_clk.common.hw,
1086 [CLK_AHB_SPI3] = &ahb_spi3_clk.common.hw,
1087 [CLK_AHB_PATA] = &ahb_pata_clk.common.hw,
1088 [CLK_AHB_SATA] = &ahb_sata_clk.common.hw,
1089 [CLK_AHB_GPS] = &ahb_gps_clk.common.hw,
1090 [CLK_AHB_VE] = &ahb_ve_clk.common.hw,
1091 [CLK_AHB_TVD] = &ahb_tvd_clk.common.hw,
1092 [CLK_AHB_TVE0] = &ahb_tve0_clk.common.hw,
1093 [CLK_AHB_TVE1] = &ahb_tve1_clk.common.hw,
1094 [CLK_AHB_LCD0] = &ahb_lcd0_clk.common.hw,
1095 [CLK_AHB_LCD1] = &ahb_lcd1_clk.common.hw,
1096 [CLK_AHB_CSI0] = &ahb_csi0_clk.common.hw,
1097 [CLK_AHB_CSI1] = &ahb_csi1_clk.common.hw,
1098 [CLK_AHB_HDMI0] = &ahb_hdmi0_clk.common.hw,
1099 [CLK_AHB_DE_BE0] = &ahb_de_be0_clk.common.hw,
1100 [CLK_AHB_DE_BE1] = &ahb_de_be1_clk.common.hw,
1101 [CLK_AHB_DE_FE0] = &ahb_de_fe0_clk.common.hw,
1102 [CLK_AHB_DE_FE1] = &ahb_de_fe1_clk.common.hw,
1103 [CLK_AHB_MP] = &ahb_mp_clk.common.hw,
1104 [CLK_AHB_GPU] = &ahb_gpu_clk.common.hw,
1105 [CLK_APB0_CODEC] = &apb0_codec_clk.common.hw,
1106 [CLK_APB0_SPDIF] = &apb0_spdif_clk.common.hw,
1107 [CLK_APB0_AC97] = &apb0_ac97_clk.common.hw,
1108 [CLK_APB0_I2S0] = &apb0_i2s0_clk.common.hw,
1109 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
1110 [CLK_APB0_IR0] = &apb0_ir0_clk.common.hw,
1111 [CLK_APB0_IR1] = &apb0_ir1_clk.common.hw,
1112 [CLK_APB0_KEYPAD] = &apb0_keypad_clk.common.hw,
1113 [CLK_APB1_I2C0] = &apb1_i2c0_clk.common.hw,
1114 [CLK_APB1_I2C1] = &apb1_i2c1_clk.common.hw,
1115 [CLK_APB1_I2C2] = &apb1_i2c2_clk.common.hw,
1116 [CLK_APB1_CAN] = &apb1_can_clk.common.hw,
1117 [CLK_APB1_SCR] = &apb1_scr_clk.common.hw,
1118 [CLK_APB1_PS20] = &apb1_ps20_clk.common.hw,
1119 [CLK_APB1_PS21] = &apb1_ps21_clk.common.hw,
1120 [CLK_APB1_UART0] = &apb1_uart0_clk.common.hw,
1121 [CLK_APB1_UART1] = &apb1_uart1_clk.common.hw,
1122 [CLK_APB1_UART2] = &apb1_uart2_clk.common.hw,
1123 [CLK_APB1_UART3] = &apb1_uart3_clk.common.hw,
1124 [CLK_APB1_UART4] = &apb1_uart4_clk.common.hw,
1125 [CLK_APB1_UART5] = &apb1_uart5_clk.common.hw,
1126 [CLK_APB1_UART6] = &apb1_uart6_clk.common.hw,
1127 [CLK_APB1_UART7] = &apb1_uart7_clk.common.hw,
1128 [CLK_NAND] = &nand_clk.common.hw,
1129 [CLK_MS] = &ms_clk.common.hw,
1130 [CLK_MMC0] = &mmc0_clk.common.hw,
1131 [CLK_MMC1] = &mmc1_clk.common.hw,
1132 [CLK_MMC2] = &mmc2_clk.common.hw,
1133 [CLK_MMC3] = &mmc3_clk.common.hw,
1134 [CLK_TS] = &ts_clk.common.hw,
1135 [CLK_SS] = &ss_clk.common.hw,
1136 [CLK_SPI0] = &spi0_clk.common.hw,
1137 [CLK_SPI1] = &spi1_clk.common.hw,
1138 [CLK_SPI2] = &spi2_clk.common.hw,
1139 [CLK_PATA] = &pata_clk.common.hw,
1140 [CLK_IR0] = &ir0_sun4i_clk.common.hw,
1141 [CLK_IR1] = &ir1_sun4i_clk.common.hw,
1142 [CLK_I2S0] = &i2s0_clk.common.hw,
1143 [CLK_AC97] = &ac97_clk.common.hw,
1144 [CLK_SPDIF] = &spdif_clk.common.hw,
1145 [CLK_KEYPAD] = &keypad_clk.common.hw,
1146 [CLK_SATA] = &sata_clk.common.hw,
1147 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
1148 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
1149 [CLK_USB_PHY] = &usb_phy_clk.common.hw,
1150 /* CLK_GPS is unimplemented */
1151 [CLK_SPI3] = &spi3_clk.common.hw,
1152 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
1153 [CLK_DRAM_CSI0] = &dram_csi0_clk.common.hw,
1154 [CLK_DRAM_CSI1] = &dram_csi1_clk.common.hw,
1155 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
1156 [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,
1157 [CLK_DRAM_TVE0] = &dram_tve0_clk.common.hw,
1158 [CLK_DRAM_TVE1] = &dram_tve1_clk.common.hw,
1159 [CLK_DRAM_OUT] = &dram_out_clk.common.hw,
1160 [CLK_DRAM_DE_FE1] = &dram_de_fe1_clk.common.hw,
1161 [CLK_DRAM_DE_FE0] = &dram_de_fe0_clk.common.hw,
1162 [CLK_DRAM_DE_BE0] = &dram_de_be0_clk.common.hw,
1163 [CLK_DRAM_DE_BE1] = &dram_de_be1_clk.common.hw,
1164 [CLK_DRAM_MP] = &dram_mp_clk.common.hw,
1165 [CLK_DRAM_ACE] = &dram_ace_clk.common.hw,
1166 [CLK_DE_BE0] = &de_be0_clk.common.hw,
1167 [CLK_DE_BE1] = &de_be1_clk.common.hw,
1168 [CLK_DE_FE0] = &de_fe0_clk.common.hw,
1169 [CLK_DE_FE1] = &de_fe1_clk.common.hw,
1170 [CLK_DE_MP] = &de_mp_clk.common.hw,
1171 [CLK_TCON0_CH0] = &tcon0_ch0_clk.common.hw,
1172 [CLK_TCON1_CH0] = &tcon1_ch0_clk.common.hw,
1173 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
1174 [CLK_TVD] = &tvd_sun4i_clk.common.hw,
1175 [CLK_TCON0_CH1_SCLK2] = &tcon0_ch1_sclk2_clk.common.hw,
1176 [CLK_TCON0_CH1] = &tcon0_ch1_clk.common.hw,
1177 [CLK_TCON1_CH1_SCLK2] = &tcon1_ch1_sclk2_clk.common.hw,
1178 [CLK_TCON1_CH1] = &tcon1_ch1_clk.common.hw,
1179 [CLK_CSI0] = &csi0_clk.common.hw,
1180 [CLK_CSI1] = &csi1_clk.common.hw,
1181 [CLK_VE] = &ve_clk.common.hw,
1182 [CLK_CODEC] = &codec_clk.common.hw,
1183 [CLK_AVS] = &avs_clk.common.hw,
1184 [CLK_ACE] = &ace_clk.common.hw,
1185 [CLK_HDMI] = &hdmi_clk.common.hw,
1186 [CLK_GPU] = &gpu_sun7i_clk.common.hw,
1187 [CLK_MBUS] = &mbus_sun4i_clk.common.hw,
1188 },
1189 .num = CLK_NUMBER_SUN4I,
1190};
1191static struct clk_hw_onecell_data sun7i_a20_hw_clks = {
1192 .hws = {
1193 [CLK_HOSC] = &hosc_clk.common.hw,
1194 [CLK_PLL_CORE] = &pll_core_clk.common.hw,
1195 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
1196 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
1197 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
1198 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
1199 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
1200 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
1201 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
1202 [CLK_PLL_VE] = &pll_ve_sun7i_clk.common.hw,
1203 [CLK_PLL_DDR_BASE] = &pll_ddr_base_clk.common.hw,
1204 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
1205 [CLK_PLL_DDR_OTHER] = &pll_ddr_other_clk.common.hw,
1206 [CLK_PLL_PERIPH_BASE] = &pll_periph_base_clk.common.hw,
1207 [CLK_PLL_PERIPH] = &pll_periph_clk.hw,
1208 [CLK_PLL_PERIPH_SATA] = &pll_periph_sata_clk.common.hw,
1209 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
1210 [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
1211 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
1212 [CLK_CPU] = &cpu_clk.common.hw,
1213 [CLK_AXI] = &axi_clk.common.hw,
1214 [CLK_AHB] = &ahb_sun7i_clk.common.hw,
1215 [CLK_APB0] = &apb0_clk.common.hw,
1216 [CLK_APB1] = &apb1_clk.common.hw,
1217 [CLK_AHB_OTG] = &ahb_otg_clk.common.hw,
1218 [CLK_AHB_EHCI0] = &ahb_ehci0_clk.common.hw,
1219 [CLK_AHB_OHCI0] = &ahb_ohci0_clk.common.hw,
1220 [CLK_AHB_EHCI1] = &ahb_ehci1_clk.common.hw,
1221 [CLK_AHB_OHCI1] = &ahb_ohci1_clk.common.hw,
1222 [CLK_AHB_SS] = &ahb_ss_clk.common.hw,
1223 [CLK_AHB_DMA] = &ahb_dma_clk.common.hw,
1224 [CLK_AHB_BIST] = &ahb_bist_clk.common.hw,
1225 [CLK_AHB_MMC0] = &ahb_mmc0_clk.common.hw,
1226 [CLK_AHB_MMC1] = &ahb_mmc1_clk.common.hw,
1227 [CLK_AHB_MMC2] = &ahb_mmc2_clk.common.hw,
1228 [CLK_AHB_MMC3] = &ahb_mmc3_clk.common.hw,
1229 [CLK_AHB_MS] = &ahb_ms_clk.common.hw,
1230 [CLK_AHB_NAND] = &ahb_nand_clk.common.hw,
1231 [CLK_AHB_SDRAM] = &ahb_sdram_clk.common.hw,
1232 [CLK_AHB_ACE] = &ahb_ace_clk.common.hw,
1233 [CLK_AHB_EMAC] = &ahb_emac_clk.common.hw,
1234 [CLK_AHB_TS] = &ahb_ts_clk.common.hw,
1235 [CLK_AHB_SPI0] = &ahb_spi0_clk.common.hw,
1236 [CLK_AHB_SPI1] = &ahb_spi1_clk.common.hw,
1237 [CLK_AHB_SPI2] = &ahb_spi2_clk.common.hw,
1238 [CLK_AHB_SPI3] = &ahb_spi3_clk.common.hw,
1239 [CLK_AHB_PATA] = &ahb_pata_clk.common.hw,
1240 [CLK_AHB_SATA] = &ahb_sata_clk.common.hw,
1241 [CLK_AHB_HSTIMER] = &ahb_hstimer_clk.common.hw,
1242 [CLK_AHB_VE] = &ahb_ve_clk.common.hw,
1243 [CLK_AHB_TVD] = &ahb_tvd_clk.common.hw,
1244 [CLK_AHB_TVE0] = &ahb_tve0_clk.common.hw,
1245 [CLK_AHB_TVE1] = &ahb_tve1_clk.common.hw,
1246 [CLK_AHB_LCD0] = &ahb_lcd0_clk.common.hw,
1247 [CLK_AHB_LCD1] = &ahb_lcd1_clk.common.hw,
1248 [CLK_AHB_CSI0] = &ahb_csi0_clk.common.hw,
1249 [CLK_AHB_CSI1] = &ahb_csi1_clk.common.hw,
1250 [CLK_AHB_HDMI1] = &ahb_hdmi1_clk.common.hw,
1251 [CLK_AHB_HDMI0] = &ahb_hdmi0_clk.common.hw,
1252 [CLK_AHB_DE_BE0] = &ahb_de_be0_clk.common.hw,
1253 [CLK_AHB_DE_BE1] = &ahb_de_be1_clk.common.hw,
1254 [CLK_AHB_DE_FE0] = &ahb_de_fe0_clk.common.hw,
1255 [CLK_AHB_DE_FE1] = &ahb_de_fe1_clk.common.hw,
1256 [CLK_AHB_GMAC] = &ahb_gmac_clk.common.hw,
1257 [CLK_AHB_MP] = &ahb_mp_clk.common.hw,
1258 [CLK_AHB_GPU] = &ahb_gpu_clk.common.hw,
1259 [CLK_APB0_CODEC] = &apb0_codec_clk.common.hw,
1260 [CLK_APB0_SPDIF] = &apb0_spdif_clk.common.hw,
1261 [CLK_APB0_AC97] = &apb0_ac97_clk.common.hw,
1262 [CLK_APB0_I2S0] = &apb0_i2s0_clk.common.hw,
1263 [CLK_APB0_I2S1] = &apb0_i2s1_clk.common.hw,
1264 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
1265 [CLK_APB0_IR0] = &apb0_ir0_clk.common.hw,
1266 [CLK_APB0_IR1] = &apb0_ir1_clk.common.hw,
1267 [CLK_APB0_I2S2] = &apb0_i2s2_clk.common.hw,
1268 [CLK_APB0_KEYPAD] = &apb0_keypad_clk.common.hw,
1269 [CLK_APB1_I2C0] = &apb1_i2c0_clk.common.hw,
1270 [CLK_APB1_I2C1] = &apb1_i2c1_clk.common.hw,
1271 [CLK_APB1_I2C2] = &apb1_i2c2_clk.common.hw,
1272 [CLK_APB1_I2C3] = &apb1_i2c3_clk.common.hw,
1273 [CLK_APB1_CAN] = &apb1_can_clk.common.hw,
1274 [CLK_APB1_SCR] = &apb1_scr_clk.common.hw,
1275 [CLK_APB1_PS20] = &apb1_ps20_clk.common.hw,
1276 [CLK_APB1_PS21] = &apb1_ps21_clk.common.hw,
1277 [CLK_APB1_I2C4] = &apb1_i2c4_clk.common.hw,
1278 [CLK_APB1_UART0] = &apb1_uart0_clk.common.hw,
1279 [CLK_APB1_UART1] = &apb1_uart1_clk.common.hw,
1280 [CLK_APB1_UART2] = &apb1_uart2_clk.common.hw,
1281 [CLK_APB1_UART3] = &apb1_uart3_clk.common.hw,
1282 [CLK_APB1_UART4] = &apb1_uart4_clk.common.hw,
1283 [CLK_APB1_UART5] = &apb1_uart5_clk.common.hw,
1284 [CLK_APB1_UART6] = &apb1_uart6_clk.common.hw,
1285 [CLK_APB1_UART7] = &apb1_uart7_clk.common.hw,
1286 [CLK_NAND] = &nand_clk.common.hw,
1287 [CLK_MS] = &ms_clk.common.hw,
1288 [CLK_MMC0] = &mmc0_clk.common.hw,
1289 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
1290 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
1291 [CLK_MMC1] = &mmc1_clk.common.hw,
1292 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
1293 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
1294 [CLK_MMC2] = &mmc2_clk.common.hw,
1295 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
1296 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
1297 [CLK_MMC3] = &mmc3_clk.common.hw,
1298 [CLK_MMC3_OUTPUT] = &mmc3_output_clk.common.hw,
1299 [CLK_MMC3_SAMPLE] = &mmc3_sample_clk.common.hw,
1300 [CLK_TS] = &ts_clk.common.hw,
1301 [CLK_SS] = &ss_clk.common.hw,
1302 [CLK_SPI0] = &spi0_clk.common.hw,
1303 [CLK_SPI1] = &spi1_clk.common.hw,
1304 [CLK_SPI2] = &spi2_clk.common.hw,
1305 [CLK_PATA] = &pata_clk.common.hw,
1306 [CLK_IR0] = &ir0_sun7i_clk.common.hw,
1307 [CLK_IR1] = &ir1_sun7i_clk.common.hw,
1308 [CLK_I2S0] = &i2s0_clk.common.hw,
1309 [CLK_AC97] = &ac97_clk.common.hw,
1310 [CLK_SPDIF] = &spdif_clk.common.hw,
1311 [CLK_KEYPAD] = &keypad_clk.common.hw,
1312 [CLK_SATA] = &sata_clk.common.hw,
1313 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
1314 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
1315 [CLK_USB_PHY] = &usb_phy_clk.common.hw,
1316 /* CLK_GPS is unimplemented */
1317 [CLK_SPI3] = &spi3_clk.common.hw,
1318 [CLK_I2S1] = &i2s1_clk.common.hw,
1319 [CLK_I2S2] = &i2s2_clk.common.hw,
1320 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
1321 [CLK_DRAM_CSI0] = &dram_csi0_clk.common.hw,
1322 [CLK_DRAM_CSI1] = &dram_csi1_clk.common.hw,
1323 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
1324 [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,
1325 [CLK_DRAM_TVE0] = &dram_tve0_clk.common.hw,
1326 [CLK_DRAM_TVE1] = &dram_tve1_clk.common.hw,
1327 [CLK_DRAM_OUT] = &dram_out_clk.common.hw,
1328 [CLK_DRAM_DE_FE1] = &dram_de_fe1_clk.common.hw,
1329 [CLK_DRAM_DE_FE0] = &dram_de_fe0_clk.common.hw,
1330 [CLK_DRAM_DE_BE0] = &dram_de_be0_clk.common.hw,
1331 [CLK_DRAM_DE_BE1] = &dram_de_be1_clk.common.hw,
1332 [CLK_DRAM_MP] = &dram_mp_clk.common.hw,
1333 [CLK_DRAM_ACE] = &dram_ace_clk.common.hw,
1334 [CLK_DE_BE0] = &de_be0_clk.common.hw,
1335 [CLK_DE_BE1] = &de_be1_clk.common.hw,
1336 [CLK_DE_FE0] = &de_fe0_clk.common.hw,
1337 [CLK_DE_FE1] = &de_fe1_clk.common.hw,
1338 [CLK_DE_MP] = &de_mp_clk.common.hw,
1339 [CLK_TCON0_CH0] = &tcon0_ch0_clk.common.hw,
1340 [CLK_TCON1_CH0] = &tcon1_ch0_clk.common.hw,
1341 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
1342 [CLK_TVD_SCLK2] = &tvd_sclk2_sun7i_clk.common.hw,
1343 [CLK_TVD] = &tvd_sclk1_sun7i_clk.common.hw,
1344 [CLK_TCON0_CH1_SCLK2] = &tcon0_ch1_sclk2_clk.common.hw,
1345 [CLK_TCON0_CH1] = &tcon0_ch1_clk.common.hw,
1346 [CLK_TCON1_CH1_SCLK2] = &tcon1_ch1_sclk2_clk.common.hw,
1347 [CLK_TCON1_CH1] = &tcon1_ch1_clk.common.hw,
1348 [CLK_CSI0] = &csi0_clk.common.hw,
1349 [CLK_CSI1] = &csi1_clk.common.hw,
1350 [CLK_VE] = &ve_clk.common.hw,
1351 [CLK_CODEC] = &codec_clk.common.hw,
1352 [CLK_AVS] = &avs_clk.common.hw,
1353 [CLK_ACE] = &ace_clk.common.hw,
1354 [CLK_HDMI] = &hdmi_clk.common.hw,
1355 [CLK_GPU] = &gpu_sun7i_clk.common.hw,
1356 [CLK_MBUS] = &mbus_sun7i_clk.common.hw,
1357 [CLK_HDMI1_SLOW] = &hdmi1_slow_clk.common.hw,
1358 [CLK_HDMI1] = &hdmi1_clk.common.hw,
1359 [CLK_OUT_A] = &out_a_clk.common.hw,
1360 [CLK_OUT_B] = &out_b_clk.common.hw,
1361 },
1362 .num = CLK_NUMBER_SUN7I,
1363};
1364
1365static struct ccu_reset_map sunxi_a10_a20_ccu_resets[] = {
1366 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
1367 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
1368 [RST_USB_PHY2] = { 0x0cc, BIT(2) },
1369 [RST_GPS] = { 0x0d0, BIT(0) },
1370 [RST_DE_BE0] = { 0x104, BIT(30) },
1371 [RST_DE_BE1] = { 0x108, BIT(30) },
1372 [RST_DE_FE0] = { 0x10c, BIT(30) },
1373 [RST_DE_FE1] = { 0x110, BIT(30) },
1374 [RST_DE_MP] = { 0x114, BIT(30) },
1375 [RST_TVE0] = { 0x118, BIT(29) },
1376 [RST_TCON0] = { 0x118, BIT(30) },
1377 [RST_TVE1] = { 0x11c, BIT(29) },
1378 [RST_TCON1] = { 0x11c, BIT(30) },
1379 [RST_CSI0] = { 0x134, BIT(30) },
1380 [RST_CSI1] = { 0x138, BIT(30) },
1381 [RST_VE] = { 0x13c, BIT(0) },
1382 [RST_ACE] = { 0x148, BIT(16) },
1383 [RST_LVDS] = { 0x14c, BIT(0) },
1384 [RST_GPU] = { 0x154, BIT(30) },
1385 [RST_HDMI_H] = { 0x170, BIT(0) },
1386 [RST_HDMI_SYS] = { 0x170, BIT(1) },
1387 [RST_HDMI_AUDIO_DMA] = { 0x170, BIT(2) },
1388};
1389
1390static const struct sunxi_ccu_desc sun4i_a10_ccu_desc = {
1391 .ccu_clks = sun4i_sun7i_ccu_clks,
1392 .num_ccu_clks = ARRAY_SIZE(sun4i_sun7i_ccu_clks),
1393
1394 .hw_clks = &sun4i_a10_hw_clks,
1395
1396 .resets = sunxi_a10_a20_ccu_resets,
1397 .num_resets = ARRAY_SIZE(sunxi_a10_a20_ccu_resets),
1398};
1399
1400static const struct sunxi_ccu_desc sun7i_a20_ccu_desc = {
1401 .ccu_clks = sun4i_sun7i_ccu_clks,
1402 .num_ccu_clks = ARRAY_SIZE(sun4i_sun7i_ccu_clks),
1403
1404 .hw_clks = &sun7i_a20_hw_clks,
1405
1406 .resets = sunxi_a10_a20_ccu_resets,
1407 .num_resets = ARRAY_SIZE(sunxi_a10_a20_ccu_resets),
1408};
1409
1410static void __init sun4i_ccu_init(struct device_node *node,
1411 const struct sunxi_ccu_desc *desc)
1412{
1413 void __iomem *reg;
1414 u32 val;
1415
1416 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
1417 if (IS_ERR(reg)) {
1418 pr_err("%s: Could not map the clock registers\n",
1419 of_node_full_name(node));
1420 return;
1421 }
1422
1423 /* Force the PLL-Audio-1x divider to 4 */
1424 val = readl(reg + SUN4I_PLL_AUDIO_REG);
1425 val &= ~GENMASK(29, 26);
1426 writel(val | (4 << 26), reg + SUN4I_PLL_AUDIO_REG);
1427
1428 /*
1429 * Use the peripheral PLL6 as the AHB parent, instead of CPU /
1430 * AXI which have rate changes due to cpufreq.
1431 *
1432 * This is especially a big deal for the HS timer whose parent
1433 * clock is AHB.
1434 *
1435 * NB! These bits are undocumented in A10 manual.
1436 */
1437 val = readl(reg + SUN4I_AHB_REG);
1438 val &= ~GENMASK(7, 6);
1439 writel(val | (2 << 6), reg + SUN4I_AHB_REG);
1440
1441 sunxi_ccu_probe(node, reg, desc);
1442}
1443
1444static void __init sun4i_a10_ccu_setup(struct device_node *node)
1445{
1446 sun4i_ccu_init(node, &sun4i_a10_ccu_desc);
1447}
1448CLK_OF_DECLARE(sun4i_a10_ccu, "allwinner,sun4i-a10-ccu",
1449 sun4i_a10_ccu_setup);
1450
1451static void __init sun7i_a20_ccu_setup(struct device_node *node)
1452{
1453 sun4i_ccu_init(node, &sun7i_a20_ccu_desc);
1454}
1455CLK_OF_DECLARE(sun7i_a20_ccu, "allwinner,sun7i-a20-ccu",
1456 sun7i_a20_ccu_setup);