| rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright 2016 Maxime Ripard |
| 3 | * |
| 4 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #ifndef _CCU_SUN5I_H_ |
| 18 | #define _CCU_SUN5I_H_ |
| 19 | |
| 20 | #include <dt-bindings/clock/sun5i-ccu.h> |
| 21 | #include <dt-bindings/reset/sun5i-ccu.h> |
| 22 | |
| 23 | /* The HOSC is exported */ |
| 24 | #define CLK_PLL_CORE 2 |
| 25 | #define CLK_PLL_AUDIO_BASE 3 |
| 26 | #define CLK_PLL_AUDIO 4 |
| 27 | #define CLK_PLL_AUDIO_2X 5 |
| 28 | #define CLK_PLL_AUDIO_4X 6 |
| 29 | #define CLK_PLL_AUDIO_8X 7 |
| 30 | #define CLK_PLL_VIDEO0 8 |
| 31 | |
| 32 | /* The PLL_VIDEO0_2X is exported for HDMI */ |
| 33 | |
| 34 | #define CLK_PLL_VE 10 |
| 35 | #define CLK_PLL_DDR_BASE 11 |
| 36 | #define CLK_PLL_DDR 12 |
| 37 | #define CLK_PLL_DDR_OTHER 13 |
| 38 | #define CLK_PLL_PERIPH 14 |
| 39 | #define CLK_PLL_VIDEO1 15 |
| 40 | |
| 41 | /* The PLL_VIDEO1_2X is exported for HDMI */ |
| 42 | /* The CPU clock is exported */ |
| 43 | |
| 44 | #define CLK_AXI 18 |
| 45 | #define CLK_AHB 19 |
| 46 | #define CLK_APB0 20 |
| 47 | #define CLK_APB1 21 |
| 48 | #define CLK_DRAM_AXI 22 |
| 49 | |
| 50 | /* AHB gates are exported */ |
| 51 | /* APB0 gates are exported */ |
| 52 | /* APB1 gates are exported */ |
| 53 | /* Modules clocks are exported */ |
| 54 | /* USB clocks are exported */ |
| 55 | /* GPS clock is exported */ |
| 56 | /* DRAM gates are exported */ |
| 57 | /* More display modules clocks are exported */ |
| 58 | |
| 59 | #define CLK_TCON_CH1_SCLK 91 |
| 60 | |
| 61 | /* The rest of the module clocks are exported */ |
| 62 | |
| 63 | #define CLK_MBUS 99 |
| 64 | |
| 65 | /* And finally the IEP clock */ |
| 66 | |
| 67 | #define CLK_NUMBER (CLK_IEP + 1) |
| 68 | |
| 69 | #endif /* _CCU_SUN5I_H_ */ |