| rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright 2017 Icenowy Zheng <icenowy@aosc.io> |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #ifndef _CCU_SUN8I_R40_H_ |
| 16 | #define _CCU_SUN8I_R40_H_ |
| 17 | |
| 18 | #include <dt-bindings/clock/sun8i-r40-ccu.h> |
| 19 | #include <dt-bindings/reset/sun8i-r40-ccu.h> |
| 20 | |
| 21 | #define CLK_OSC_12M 0 |
| 22 | #define CLK_PLL_CPU 1 |
| 23 | #define CLK_PLL_AUDIO_BASE 2 |
| 24 | #define CLK_PLL_AUDIO 3 |
| 25 | #define CLK_PLL_AUDIO_2X 4 |
| 26 | #define CLK_PLL_AUDIO_4X 5 |
| 27 | #define CLK_PLL_AUDIO_8X 6 |
| 28 | #define CLK_PLL_VIDEO0 7 |
| 29 | #define CLK_PLL_VIDEO0_2X 8 |
| 30 | #define CLK_PLL_VE 9 |
| 31 | #define CLK_PLL_DDR0 10 |
| 32 | #define CLK_PLL_PERIPH0 11 |
| 33 | #define CLK_PLL_PERIPH0_SATA 12 |
| 34 | #define CLK_PLL_PERIPH0_2X 13 |
| 35 | #define CLK_PLL_PERIPH1 14 |
| 36 | #define CLK_PLL_PERIPH1_2X 15 |
| 37 | #define CLK_PLL_VIDEO1 16 |
| 38 | #define CLK_PLL_VIDEO1_2X 17 |
| 39 | #define CLK_PLL_SATA 18 |
| 40 | #define CLK_PLL_SATA_OUT 19 |
| 41 | #define CLK_PLL_GPU 20 |
| 42 | #define CLK_PLL_MIPI 21 |
| 43 | #define CLK_PLL_DE 22 |
| 44 | #define CLK_PLL_DDR1 23 |
| 45 | |
| 46 | /* The CPU clock is exported */ |
| 47 | |
| 48 | #define CLK_AXI 25 |
| 49 | #define CLK_AHB1 26 |
| 50 | #define CLK_APB1 27 |
| 51 | #define CLK_APB2 28 |
| 52 | |
| 53 | /* All the bus gates are exported */ |
| 54 | |
| 55 | /* The first bunch of module clocks are exported */ |
| 56 | |
| 57 | #define CLK_DRAM 132 |
| 58 | |
| 59 | /* All the DRAM gates are exported */ |
| 60 | |
| 61 | /* Some more module clocks are exported */ |
| 62 | |
| 63 | #define CLK_MBUS 155 |
| 64 | |
| 65 | /* Another bunch of module clocks are exported */ |
| 66 | |
| 67 | #define CLK_NUMBER (CLK_OUTB + 1) |
| 68 | |
| 69 | #endif /* _CCU_SUN8I_R40_H_ */ |