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192.168.1.100 / T103 / 1f884588077ad3476b9c91cbb0ee9ee0332bbb68 / . / src / kernel / linux / v4.14 / drivers / clk / uniphier / clk-uniphier-sys.c
blob: d244e724e19858dfb8b8c5297e9852a61ba0ce50 [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +0800[diff] [blame^]1/*
2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/stddef.h>
17
18#include "clk-uniphier.h"
19
20#define UNIPHIER_LD4_SYS_CLK_SD \
21 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
22 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
23
24#define UNIPHIER_PRO5_SYS_CLK_SD \
25 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
26 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
27
28#define UNIPHIER_LD20_SYS_CLK_SD \
29 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
30 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
31
32/* Denali driver requires clk_x rate (clk: 50MHz, clk_x & ecc_clk: 200MHz) */
33#define UNIPHIER_LD4_SYS_CLK_NAND(idx) \
34 UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 8), \
35 UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x2104, 2)
36
37#define UNIPHIER_PRO5_SYS_CLK_NAND(idx) \
38 UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 12), \
39 UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x2104, 2)
40
41#define UNIPHIER_LD11_SYS_CLK_NAND(idx) \
42 UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 10), \
43 UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x210c, 0)
44
45#define UNIPHIER_LD11_SYS_CLK_EMMC(idx) \
46 UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2)
47
48#define UNIPHIER_LD4_SYS_CLK_STDMAC(idx) \
49 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10)
50
51#define UNIPHIER_LD11_SYS_CLK_STDMAC(idx) \
52 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8)
53
54#define UNIPHIER_PRO4_SYS_CLK_GIO(idx) \
55 UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6)
56
57#define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch) \
58 UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch))
59
60#define UNIPHIER_LD11_SYS_CLK_AIO(idx) \
61 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 10), \
62 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2108, 0)
63
64#define UNIPHIER_LD11_SYS_CLK_EVEA(idx) \
65 UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20), \
66 UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1)
67
68#define UNIPHIER_LD11_SYS_CLK_EXIV(idx) \
69 UNIPHIER_CLK_FACTOR("exiv-io200m", -1, "spll", 1, 10), \
70 UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2)
71
72#define UNIPHIER_PRO4_SYS_CLK_ETHER(idx) \
73 UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x2104, 12)
74
75#define UNIPHIER_LD11_SYS_CLK_ETHER(idx) \
76 UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x210c, 6)
77
78const struct uniphier_clk_data uniphier_ld4_sys_clk_data[] = {
79 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
80 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
81 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
82 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
83 UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),
84 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
85 UNIPHIER_LD4_SYS_CLK_NAND(2),
86 UNIPHIER_LD4_SYS_CLK_SD,
87 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
88 UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */
89 { /* sentinel */ }
90};
91
92const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = {
93 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
94 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
95 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
96 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
97 UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8),
98 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32),
99 UNIPHIER_LD4_SYS_CLK_NAND(2),
100 UNIPHIER_LD4_SYS_CLK_SD,
101 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
102 UNIPHIER_PRO4_SYS_CLK_ETHER(6),
103 UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC, MIO, RLE */
104 UNIPHIER_PRO4_SYS_CLK_GIO(12), /* Ether, SATA, USB3 */
105 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
106 UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
107 { /* sentinel */ }
108};
109
110const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = {
111 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
112 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
113 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
114 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20),
115 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
116 UNIPHIER_LD4_SYS_CLK_NAND(2),
117 UNIPHIER_LD4_SYS_CLK_SD,
118 UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
119 UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */
120 { /* sentinel */ }
121};
122
123const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {
124 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */
125 UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1), /* 2560 MHz */
126 UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125), /* 2949.12 MHz */
127 UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),
128 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
129 UNIPHIER_PRO5_SYS_CLK_NAND(2),
130 UNIPHIER_PRO5_SYS_CLK_SD,
131 UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC */
132 UNIPHIER_PRO4_SYS_CLK_GIO(12), /* PCIe, USB3 */
133 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
134 UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
135 { /* sentinel */ }
136};
137
138const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
139 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1), /* 2400 MHz */
140 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27),
141 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
142 UNIPHIER_PRO5_SYS_CLK_NAND(2),
143 UNIPHIER_PRO5_SYS_CLK_SD,
144 UNIPHIER_PRO4_SYS_CLK_ETHER(6),
145 UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC, RLE */
146 /* GIO is always clock-enabled: no function for 0x2104 bit6 */
147 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
148 UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
149 /* The document mentions 0x2104 bit 18, but not functional */
150 UNIPHIER_CLK_GATE("usb30-phy", 16, NULL, 0x2104, 19),
151 UNIPHIER_CLK_GATE("usb31-phy", 20, NULL, 0x2104, 20),
152 { /* sentinel */ }
153};
154
155const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
156 UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 392, 5), /* 1960 MHz */
157 UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* 1600 MHz */
158 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
159 UNIPHIER_CLK_FACTOR("vspll", -1, "ref", 80, 1), /* 2000 MHz */
160 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
161 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
162 UNIPHIER_LD11_SYS_CLK_NAND(2),
163 UNIPHIER_LD11_SYS_CLK_EMMC(4),
164 /* Index 5 reserved for eMMC PHY */
165 UNIPHIER_LD11_SYS_CLK_ETHER(6),
166 UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC, MIO */
167 UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
168 UNIPHIER_LD11_SYS_CLK_AIO(40),
169 UNIPHIER_LD11_SYS_CLK_EVEA(41),
170 UNIPHIER_LD11_SYS_CLK_EXIV(42),
171 /* CPU gears */
172 UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
173 UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8),
174 UNIPHIER_CLK_DIV3("spll", 3, 4, 8),
175 /* Note: both gear1 and gear4 are spll/4. This is not a bug. */
176 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
177 "cpll/2", "spll/4", "cpll/3", "spll/3",
178 "spll/4", "spll/8", "cpll/4", "cpll/8"),
179 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
180 "mpll/2", "spll/4", "mpll/3", "spll/3",
181 "spll/4", "spll/8", "mpll/4", "mpll/8"),
182 { /* sentinel */ }
183};
184
185const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
186 UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 88, 1), /* ARM: 2200 MHz */
187 UNIPHIER_CLK_FACTOR("gppll", -1, "ref", 52, 1), /* Mali: 1300 MHz */
188 UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* Codec: 1600 MHz */
189 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
190 UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1), /* IPP: 2200 MHz */
191 UNIPHIER_CLK_FACTOR("vppll", -1, "ref", 504, 5), /* 2520 MHz */
192 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
193 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
194 UNIPHIER_LD11_SYS_CLK_NAND(2),
195 UNIPHIER_LD11_SYS_CLK_EMMC(4),
196 /* Index 5 reserved for eMMC PHY */
197 UNIPHIER_LD20_SYS_CLK_SD,
198 UNIPHIER_LD11_SYS_CLK_ETHER(6),
199 UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC */
200 /* GIO is always clock-enabled: no function for 0x210c bit5 */
201 /*
202 * clock for USB Link is enabled by the logic "OR" of bit 14 and bit 15.
203 * We do not use bit 15 here.
204 */
205 UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14),
206 UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 12),
207 UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13),
208 UNIPHIER_LD11_SYS_CLK_AIO(40),
209 UNIPHIER_LD11_SYS_CLK_EVEA(41),
210 UNIPHIER_LD11_SYS_CLK_EXIV(42),
211 /* CPU gears */
212 UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
213 UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
214 UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8),
215 UNIPHIER_CLK_CPUGEAR("cpu-ca72", 32, 0x8000, 0xf, 8,
216 "cpll/2", "spll/2", "cpll/3", "spll/3",
217 "spll/4", "spll/8", "cpll/4", "cpll/8"),
218 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
219 "cpll/2", "spll/2", "cpll/3", "spll/3",
220 "spll/4", "spll/8", "cpll/4", "cpll/8"),
221 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
222 "s2pll/2", "spll/2", "s2pll/3", "spll/3",
223 "spll/4", "spll/8", "s2pll/4", "s2pll/8"),
224 { /* sentinel */ }
225};
226
227const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
228 UNIPHIER_CLK_FACTOR("cpll", -1, "ref", 104, 1), /* ARM: 2600 MHz */
229 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
230 UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1), /* IPP: 2400 MHz */
231 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
232 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
233 UNIPHIER_LD20_SYS_CLK_SD,
234 UNIPHIER_LD11_SYS_CLK_NAND(2),
235 UNIPHIER_LD11_SYS_CLK_EMMC(4),
236 UNIPHIER_CLK_GATE("usb30", 12, NULL, 0x210c, 4), /* =GIO0 */
237 UNIPHIER_CLK_GATE("usb31-0", 13, NULL, 0x210c, 5), /* =GIO1 */
238 UNIPHIER_CLK_GATE("usb31-1", 14, NULL, 0x210c, 6), /* =GIO1-1 */
239 UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 16),
240 UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 18),
241 UNIPHIER_CLK_GATE("usb30-phy2", 18, NULL, 0x210c, 20),
242 UNIPHIER_CLK_GATE("usb31-phy0", 20, NULL, 0x210c, 17),
243 UNIPHIER_CLK_GATE("usb31-phy1", 21, NULL, 0x210c, 19),
244 /* CPU gears */
245 UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
246 UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
247 UNIPHIER_CLK_DIV4("s2pll", 2, 3, 4, 8),
248 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
249 "cpll/2", "spll/2", "cpll/3", "spll/3",
250 "spll/4", "spll/8", "cpll/4", "cpll/8"),
251 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
252 "s2pll/2", "spll/2", "s2pll/3", "spll/3",
253 "spll/4", "spll/8", "s2pll/4", "s2pll/8"),
254 { /* sentinel */ }
255};