rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Freescale vf610 GPIO support through PORT and GPIO |
| 3 | * |
| 4 | * Copyright (c) 2014 Toradex AG. |
| 5 | * |
| 6 | * Author: Stefan Agner <stefan@agner.ch>. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License |
| 10 | * as published by the Free Software Foundation; either version 2 |
| 11 | * of the License, or (at your option) any later version. |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <linux/bitops.h> |
| 19 | #include <linux/err.h> |
| 20 | #include <linux/gpio.h> |
| 21 | #include <linux/init.h> |
| 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/io.h> |
| 24 | #include <linux/ioport.h> |
| 25 | #include <linux/irq.h> |
| 26 | #include <linux/platform_device.h> |
| 27 | #include <linux/of.h> |
| 28 | #include <linux/of_device.h> |
| 29 | #include <linux/of_irq.h> |
| 30 | |
| 31 | #define VF610_GPIO_PER_PORT 32 |
| 32 | |
| 33 | struct fsl_gpio_soc_data { |
| 34 | /* SoCs has a Port Data Direction Register (PDDR) */ |
| 35 | bool have_paddr; |
| 36 | }; |
| 37 | |
| 38 | struct vf610_gpio_port { |
| 39 | struct gpio_chip gc; |
| 40 | struct irq_chip ic; |
| 41 | void __iomem *base; |
| 42 | void __iomem *gpio_base; |
| 43 | const struct fsl_gpio_soc_data *sdata; |
| 44 | u8 irqc[VF610_GPIO_PER_PORT]; |
| 45 | int irq; |
| 46 | }; |
| 47 | |
| 48 | #define GPIO_PDOR 0x00 |
| 49 | #define GPIO_PSOR 0x04 |
| 50 | #define GPIO_PCOR 0x08 |
| 51 | #define GPIO_PTOR 0x0c |
| 52 | #define GPIO_PDIR 0x10 |
| 53 | #define GPIO_PDDR 0x14 |
| 54 | |
| 55 | #define PORT_PCR(n) ((n) * 0x4) |
| 56 | #define PORT_PCR_IRQC_OFFSET 16 |
| 57 | |
| 58 | #define PORT_ISFR 0xa0 |
| 59 | #define PORT_DFER 0xc0 |
| 60 | #define PORT_DFCR 0xc4 |
| 61 | #define PORT_DFWR 0xc8 |
| 62 | |
| 63 | #define PORT_INT_OFF 0x0 |
| 64 | #define PORT_INT_LOGIC_ZERO 0x8 |
| 65 | #define PORT_INT_RISING_EDGE 0x9 |
| 66 | #define PORT_INT_FALLING_EDGE 0xa |
| 67 | #define PORT_INT_EITHER_EDGE 0xb |
| 68 | #define PORT_INT_LOGIC_ONE 0xc |
| 69 | |
| 70 | static const struct fsl_gpio_soc_data imx_data = { |
| 71 | .have_paddr = true, |
| 72 | }; |
| 73 | |
| 74 | static const struct of_device_id vf610_gpio_dt_ids[] = { |
| 75 | { .compatible = "fsl,vf610-gpio", .data = NULL, }, |
| 76 | { .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, }, |
| 77 | { /* sentinel */ } |
| 78 | }; |
| 79 | |
| 80 | static inline void vf610_gpio_writel(u32 val, void __iomem *reg) |
| 81 | { |
| 82 | writel_relaxed(val, reg); |
| 83 | } |
| 84 | |
| 85 | static inline u32 vf610_gpio_readl(void __iomem *reg) |
| 86 | { |
| 87 | return readl_relaxed(reg); |
| 88 | } |
| 89 | |
| 90 | static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio) |
| 91 | { |
| 92 | struct vf610_gpio_port *port = gpiochip_get_data(gc); |
| 93 | unsigned long mask = BIT(gpio); |
| 94 | void __iomem *addr; |
| 95 | |
| 96 | if (port->sdata && port->sdata->have_paddr) { |
| 97 | mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR); |
| 98 | addr = mask ? port->gpio_base + GPIO_PDOR : |
| 99 | port->gpio_base + GPIO_PDIR; |
| 100 | return !!(vf610_gpio_readl(addr) & BIT(gpio)); |
| 101 | } else { |
| 102 | return !!(vf610_gpio_readl(port->gpio_base + GPIO_PDIR) |
| 103 | & BIT(gpio)); |
| 104 | } |
| 105 | } |
| 106 | |
| 107 | static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) |
| 108 | { |
| 109 | struct vf610_gpio_port *port = gpiochip_get_data(gc); |
| 110 | unsigned long mask = BIT(gpio); |
| 111 | |
| 112 | if (val) |
| 113 | vf610_gpio_writel(mask, port->gpio_base + GPIO_PSOR); |
| 114 | else |
| 115 | vf610_gpio_writel(mask, port->gpio_base + GPIO_PCOR); |
| 116 | } |
| 117 | |
| 118 | static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) |
| 119 | { |
| 120 | struct vf610_gpio_port *port = gpiochip_get_data(chip); |
| 121 | unsigned long mask = BIT(gpio); |
| 122 | u32 val; |
| 123 | |
| 124 | if (port->sdata && port->sdata->have_paddr) { |
| 125 | val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR); |
| 126 | val &= ~mask; |
| 127 | vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR); |
| 128 | } |
| 129 | |
| 130 | return pinctrl_gpio_direction_input(chip->base + gpio); |
| 131 | } |
| 132 | |
| 133 | static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, |
| 134 | int value) |
| 135 | { |
| 136 | struct vf610_gpio_port *port = gpiochip_get_data(chip); |
| 137 | unsigned long mask = BIT(gpio); |
| 138 | |
| 139 | if (port->sdata && port->sdata->have_paddr) |
| 140 | vf610_gpio_writel(mask, port->gpio_base + GPIO_PDDR); |
| 141 | |
| 142 | vf610_gpio_set(chip, gpio, value); |
| 143 | |
| 144 | return pinctrl_gpio_direction_output(chip->base + gpio); |
| 145 | } |
| 146 | |
| 147 | static void vf610_gpio_irq_handler(struct irq_desc *desc) |
| 148 | { |
| 149 | struct vf610_gpio_port *port = |
| 150 | gpiochip_get_data(irq_desc_get_handler_data(desc)); |
| 151 | struct irq_chip *chip = irq_desc_get_chip(desc); |
| 152 | int pin; |
| 153 | unsigned long irq_isfr; |
| 154 | |
| 155 | chained_irq_enter(chip, desc); |
| 156 | |
| 157 | irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR); |
| 158 | |
| 159 | for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) { |
| 160 | vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR); |
| 161 | |
| 162 | generic_handle_irq(irq_find_mapping(port->gc.irqdomain, pin)); |
| 163 | } |
| 164 | |
| 165 | chained_irq_exit(chip, desc); |
| 166 | } |
| 167 | |
| 168 | static void vf610_gpio_irq_ack(struct irq_data *d) |
| 169 | { |
| 170 | struct vf610_gpio_port *port = |
| 171 | gpiochip_get_data(irq_data_get_irq_chip_data(d)); |
| 172 | int gpio = d->hwirq; |
| 173 | |
| 174 | vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR); |
| 175 | } |
| 176 | |
| 177 | static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type) |
| 178 | { |
| 179 | struct vf610_gpio_port *port = |
| 180 | gpiochip_get_data(irq_data_get_irq_chip_data(d)); |
| 181 | u8 irqc; |
| 182 | |
| 183 | switch (type) { |
| 184 | case IRQ_TYPE_EDGE_RISING: |
| 185 | irqc = PORT_INT_RISING_EDGE; |
| 186 | break; |
| 187 | case IRQ_TYPE_EDGE_FALLING: |
| 188 | irqc = PORT_INT_FALLING_EDGE; |
| 189 | break; |
| 190 | case IRQ_TYPE_EDGE_BOTH: |
| 191 | irqc = PORT_INT_EITHER_EDGE; |
| 192 | break; |
| 193 | case IRQ_TYPE_LEVEL_LOW: |
| 194 | irqc = PORT_INT_LOGIC_ZERO; |
| 195 | break; |
| 196 | case IRQ_TYPE_LEVEL_HIGH: |
| 197 | irqc = PORT_INT_LOGIC_ONE; |
| 198 | break; |
| 199 | default: |
| 200 | return -EINVAL; |
| 201 | } |
| 202 | |
| 203 | port->irqc[d->hwirq] = irqc; |
| 204 | |
| 205 | if (type & IRQ_TYPE_LEVEL_MASK) |
| 206 | irq_set_handler_locked(d, handle_level_irq); |
| 207 | else |
| 208 | irq_set_handler_locked(d, handle_edge_irq); |
| 209 | |
| 210 | return 0; |
| 211 | } |
| 212 | |
| 213 | static void vf610_gpio_irq_mask(struct irq_data *d) |
| 214 | { |
| 215 | struct vf610_gpio_port *port = |
| 216 | gpiochip_get_data(irq_data_get_irq_chip_data(d)); |
| 217 | void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq); |
| 218 | |
| 219 | vf610_gpio_writel(0, pcr_base); |
| 220 | } |
| 221 | |
| 222 | static void vf610_gpio_irq_unmask(struct irq_data *d) |
| 223 | { |
| 224 | struct vf610_gpio_port *port = |
| 225 | gpiochip_get_data(irq_data_get_irq_chip_data(d)); |
| 226 | void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq); |
| 227 | |
| 228 | vf610_gpio_writel(port->irqc[d->hwirq] << PORT_PCR_IRQC_OFFSET, |
| 229 | pcr_base); |
| 230 | } |
| 231 | |
| 232 | static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable) |
| 233 | { |
| 234 | struct vf610_gpio_port *port = |
| 235 | gpiochip_get_data(irq_data_get_irq_chip_data(d)); |
| 236 | |
| 237 | if (enable) |
| 238 | enable_irq_wake(port->irq); |
| 239 | else |
| 240 | disable_irq_wake(port->irq); |
| 241 | |
| 242 | return 0; |
| 243 | } |
| 244 | |
| 245 | static int vf610_gpio_probe(struct platform_device *pdev) |
| 246 | { |
| 247 | const struct of_device_id *of_id = of_match_device(vf610_gpio_dt_ids, |
| 248 | &pdev->dev); |
| 249 | struct device *dev = &pdev->dev; |
| 250 | struct device_node *np = dev->of_node; |
| 251 | struct vf610_gpio_port *port; |
| 252 | struct resource *iores; |
| 253 | struct gpio_chip *gc; |
| 254 | struct irq_chip *ic; |
| 255 | int i; |
| 256 | int ret; |
| 257 | |
| 258 | port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); |
| 259 | if (!port) |
| 260 | return -ENOMEM; |
| 261 | |
| 262 | port->sdata = of_id->data; |
| 263 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 264 | port->base = devm_ioremap_resource(dev, iores); |
| 265 | if (IS_ERR(port->base)) |
| 266 | return PTR_ERR(port->base); |
| 267 | |
| 268 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
| 269 | port->gpio_base = devm_ioremap_resource(dev, iores); |
| 270 | if (IS_ERR(port->gpio_base)) |
| 271 | return PTR_ERR(port->gpio_base); |
| 272 | |
| 273 | port->irq = platform_get_irq(pdev, 0); |
| 274 | if (port->irq < 0) |
| 275 | return port->irq; |
| 276 | |
| 277 | gc = &port->gc; |
| 278 | gc->of_node = np; |
| 279 | gc->parent = dev; |
| 280 | gc->label = "vf610-gpio"; |
| 281 | gc->ngpio = VF610_GPIO_PER_PORT; |
| 282 | gc->base = of_alias_get_id(np, "gpio") * VF610_GPIO_PER_PORT; |
| 283 | |
| 284 | gc->request = gpiochip_generic_request; |
| 285 | gc->free = gpiochip_generic_free; |
| 286 | gc->direction_input = vf610_gpio_direction_input; |
| 287 | gc->get = vf610_gpio_get; |
| 288 | gc->direction_output = vf610_gpio_direction_output; |
| 289 | gc->set = vf610_gpio_set; |
| 290 | |
| 291 | ic = &port->ic; |
| 292 | ic->name = "gpio-vf610"; |
| 293 | ic->irq_ack = vf610_gpio_irq_ack; |
| 294 | ic->irq_mask = vf610_gpio_irq_mask; |
| 295 | ic->irq_unmask = vf610_gpio_irq_unmask; |
| 296 | ic->irq_set_type = vf610_gpio_irq_set_type; |
| 297 | ic->irq_set_wake = vf610_gpio_irq_set_wake; |
| 298 | |
| 299 | ret = gpiochip_add_data(gc, port); |
| 300 | if (ret < 0) |
| 301 | return ret; |
| 302 | |
| 303 | /* Mask all GPIO interrupts */ |
| 304 | for (i = 0; i < gc->ngpio; i++) |
| 305 | vf610_gpio_writel(0, port->base + PORT_PCR(i)); |
| 306 | |
| 307 | /* Clear the interrupt status register for all GPIO's */ |
| 308 | vf610_gpio_writel(~0, port->base + PORT_ISFR); |
| 309 | |
| 310 | ret = gpiochip_irqchip_add(gc, ic, 0, handle_edge_irq, IRQ_TYPE_NONE); |
| 311 | if (ret) { |
| 312 | dev_err(dev, "failed to add irqchip\n"); |
| 313 | gpiochip_remove(gc); |
| 314 | return ret; |
| 315 | } |
| 316 | gpiochip_set_chained_irqchip(gc, ic, port->irq, |
| 317 | vf610_gpio_irq_handler); |
| 318 | |
| 319 | return 0; |
| 320 | } |
| 321 | |
| 322 | static struct platform_driver vf610_gpio_driver = { |
| 323 | .driver = { |
| 324 | .name = "gpio-vf610", |
| 325 | .of_match_table = vf610_gpio_dt_ids, |
| 326 | }, |
| 327 | .probe = vf610_gpio_probe, |
| 328 | }; |
| 329 | |
| 330 | builtin_platform_driver(vf610_gpio_driver); |