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192.168.1.100 / T103 / 1f884588077ad3476b9c91cbb0ee9ee0332bbb68 / . / src / kernel / linux / v4.14 / drivers / i2c / busses / i2c-mt65xx.c
blob: cbbf48d3cccb7101192155502cfb929ba9087b64 [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +0800[diff] [blame^]1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Xudong Chen <xudong.chen@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clk.h>
16#include <linux/completion.h>
17#include <linux/delay.h>
18#include <linux/device.h>
19#include <linux/dma-mapping.h>
20#include <linux/err.h>
21#include <linux/errno.h>
22#include <linux/i2c.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/kernel.h>
27#include <linux/mm.h>
28#include <linux/module.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/platform_device.h>
32#include <linux/scatterlist.h>
33#include <linux/sched.h>
34#include <linux/slab.h>
35
36#define I2C_RS_TRANSFER (1 << 4)
37#define I2C_ARB_LOST (1 << 3)
38#define I2C_HS_NACKERR (1 << 2)
39#define I2C_ACKERR (1 << 1)
40#define I2C_TRANSAC_COMP (1 << 0)
41#define I2C_TRANSAC_START (1 << 0)
42#define I2C_RESUME_ARBIT (1 << 1)
43#define I2C_RS_MUL_CNFG (1 << 15)
44#define I2C_RS_MUL_TRIG (1 << 14)
45#define I2C_DCM_DISABLE 0x0000
46#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
47#define I2C_IO_CONFIG_PUSH_PULL 0x0000
48#define I2C_SOFT_RST 0x0001
49#define I2C_FIFO_ADDR_CLR 0x0003
50#define I2C_HFIFO_DATA 0x8208
51#define I2C_FIFO_ADDR_CLR_MCH 0x0004
52#define I2C_DELAY_LEN 0x0002
53#define I2C_ST_START_CON 0x8001
54#define I2C_FS_START_CON 0x1800
55#define I2C_TIME_CLR_VALUE 0x0000
56#define I2C_TIME_DEFAULT_VALUE 0x0083
57#define I2C_WRRD_TRANAC_VALUE 0x0002
58#define I2C_RD_TRANAC_VALUE 0x0001
59
60#define I2C_DMA_CON_TX 0x0000
61#define I2C_DMA_CON_RX 0x0001
62#define I2C_DMA_START_EN 0x0001
63#define I2C_DMA_INT_FLAG_NONE 0x0000
64#define I2C_DMA_CLR_FLAG 0x0000
65#define I2C_DMA_HARD_RST 0x0002
66#define I2C_DMA_4G_MODE 0x0001
67
68#define I2C_DEFAULT_CLK_DIV 5
69#define I2C_DEFAULT_SPEED 100000 /* hz */
70#define MAX_FS_MODE_SPEED 400000
71#define MAX_HS_MODE_SPEED 3400000
72#define MAX_SAMPLE_CNT_DIV 8
73#define MAX_STEP_CNT_DIV 64
74#define MAX_HS_STEP_CNT_DIV 8
75
76#define I2C_CONTROL_RS (0x1 << 1)
77#define I2C_CONTROL_DMA_EN (0x1 << 2)
78#define I2C_CONTROL_CLK_EXT_EN (0x1 << 3)
79#define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
80#define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
81#define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
82#define I2C_CONTROL_DMAACK_EN (0x1 << 8)
83#define I2C_CONTROL_ASYNC_MODE (0x1 << 9)
84#define I2C_CONTROL_WRAPPER (0x1 << 0)
85
86#define I2C_DRV_NAME "i2c-mt65xx"
87
88enum DMA_REGS_OFFSET {
89 OFFSET_INT_FLAG = 0x0,
90 OFFSET_INT_EN = 0x04,
91 OFFSET_EN = 0x08,
92 OFFSET_RST = 0x0c,
93 OFFSET_CON = 0x18,
94 OFFSET_TX_MEM_ADDR = 0x1c,
95 OFFSET_RX_MEM_ADDR = 0x20,
96 OFFSET_TX_LEN = 0x24,
97 OFFSET_RX_LEN = 0x28,
98 OFFSET_TX_4G_MODE = 0x54,
99 OFFSET_RX_4G_MODE = 0x58,
100};
101
102enum i2c_trans_st_rs {
103 I2C_TRANS_STOP = 0,
104 I2C_TRANS_REPEATED_START,
105};
106
107enum mtk_trans_op {
108 I2C_MASTER_WR = 1,
109 I2C_MASTER_RD,
110 I2C_MASTER_WRRD,
111};
112
113enum I2C_REGS_OFFSET {
114 OFFSET_DATA_PORT,
115 OFFSET_SLAVE_ADDR,
116 OFFSET_INTR_MASK,
117 OFFSET_INTR_STAT,
118 OFFSET_CONTROL,
119 OFFSET_TRANSFER_LEN,
120 OFFSET_TRANSAC_LEN,
121 OFFSET_DELAY_LEN,
122 OFFSET_TIMING,
123 OFFSET_START,
124 OFFSET_EXT_CONF,
125 OFFSET_FIFO_STAT,
126 OFFSET_FIFO_THRESH,
127 OFFSET_FIFO_ADDR_CLR,
128 OFFSET_IO_CONFIG,
129 OFFSET_RSV_DEBUG,
130 OFFSET_HS,
131 OFFSET_SOFTRESET,
132 OFFSET_DCM_EN,
133 OFFSET_PATH_DIR,
134 OFFSET_DEBUGSTAT,
135 OFFSET_DEBUGCTRL,
136 OFFSET_TRANSFER_LEN_AUX,
137 OFFSET_CLOCK_DIV,
138 /* MT8183 only regs */
139 OFFSET_LTIMING,
140 OFFSET_DATA_TIMING,
141 OFFSET_MCU_INTR,
142 OFFSET_HW_TIMEOUT,
143 OFFSET_HFIFO_DATA,
144 OFFSET_HFIFO_STAT,
145 OFFSET_MULTI_DMA,
146 OFFSET_ROLLBACK,
147};
148
149static const u16 mt_i2c_regs_v1[] = {
150 [OFFSET_DATA_PORT] = 0x0,
151 [OFFSET_SLAVE_ADDR] = 0x4,
152 [OFFSET_INTR_MASK] = 0x8,
153 [OFFSET_INTR_STAT] = 0xc,
154 [OFFSET_CONTROL] = 0x10,
155 [OFFSET_TRANSFER_LEN] = 0x14,
156 [OFFSET_TRANSAC_LEN] = 0x18,
157 [OFFSET_DELAY_LEN] = 0x1c,
158 [OFFSET_TIMING] = 0x20,
159 [OFFSET_START] = 0x24,
160 [OFFSET_EXT_CONF] = 0x28,
161 [OFFSET_FIFO_STAT] = 0x30,
162 [OFFSET_FIFO_THRESH] = 0x34,
163 [OFFSET_FIFO_ADDR_CLR] = 0x38,
164 [OFFSET_IO_CONFIG] = 0x40,
165 [OFFSET_RSV_DEBUG] = 0x44,
166 [OFFSET_HS] = 0x48,
167 [OFFSET_SOFTRESET] = 0x50,
168 [OFFSET_DCM_EN] = 0x54,
169 [OFFSET_PATH_DIR] = 0x60,
170 [OFFSET_DEBUGSTAT] = 0x64,
171 [OFFSET_DEBUGCTRL] = 0x68,
172 [OFFSET_TRANSFER_LEN_AUX] = 0x6c,
173 [OFFSET_CLOCK_DIV] = 0x70,
174};
175
176static const u16 mt_i2c_regs_v2[] = {
177 [OFFSET_DATA_PORT] = 0x0,
178 [OFFSET_SLAVE_ADDR] = 0x4,
179 [OFFSET_INTR_MASK] = 0x8,
180 [OFFSET_INTR_STAT] = 0xc,
181 [OFFSET_CONTROL] = 0x10,
182 [OFFSET_TRANSFER_LEN] = 0x14,
183 [OFFSET_TRANSAC_LEN] = 0x18,
184 [OFFSET_DELAY_LEN] = 0x1c,
185 [OFFSET_TIMING] = 0x20,
186 [OFFSET_START] = 0x24,
187 [OFFSET_EXT_CONF] = 0x28,
188 [OFFSET_LTIMING] = 0x2c,
189 [OFFSET_HS] = 0x30,
190 [OFFSET_IO_CONFIG] = 0x34,
191 [OFFSET_FIFO_ADDR_CLR] = 0x38,
192 [OFFSET_DATA_TIMING] = 0x3c,
193 [OFFSET_MCU_INTR] = 0x40,
194 [OFFSET_TRANSFER_LEN_AUX] = 0x44,
195 [OFFSET_CLOCK_DIV] = 0x48,
196 [OFFSET_HW_TIMEOUT] = 0x4c,
197 [OFFSET_SOFTRESET] = 0x50,
198 [OFFSET_HFIFO_DATA] = 0x70,
199 [OFFSET_DEBUGSTAT] = 0xe0,
200 [OFFSET_DEBUGCTRL] = 0xe8,
201 [OFFSET_FIFO_STAT] = 0xf4,
202 [OFFSET_FIFO_THRESH] = 0xf8,
203 [OFFSET_HFIFO_STAT] = 0xfc,
204 [OFFSET_DCM_EN] = 0xf88,
205 [OFFSET_MULTI_DMA] = 0xf8c,
206 [OFFSET_ROLLBACK] = 0xf98,
207};
208
209struct mtk_i2c_compatible {
210 const struct i2c_adapter_quirks *quirks;
211 const u16 *regs;
212 unsigned char pmic_i2c: 1;
213 unsigned char dcm: 1;
214 unsigned char auto_restart: 1;
215 unsigned char aux_len_reg: 1;
216 unsigned char support_33bits: 1;
217 unsigned char timing_adjust: 1;
218};
219
220struct mtk_i2c {
221 struct i2c_adapter adap; /* i2c host adapter */
222 struct device *dev;
223 struct completion msg_complete;
224
225 /* set in i2c probe */
226 void __iomem *base; /* i2c base addr */
227 void __iomem *pdmabase; /* dma base address*/
228 struct clk *clk_main; /* main clock for i2c bus */
229 struct clk *clk_dma; /* DMA clock for i2c via DMA */
230 struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */
231 struct clk *clk_arb; /* Arbitrator clock for i2c */
232 bool have_pmic; /* can use i2c pins from PMIC */
233 bool use_push_pull; /* IO config push-pull mode */
234 u32 ch_offset; /* i2c multi-user channel offset */
235
236 u16 irq_stat; /* interrupt status */
237 unsigned int clk_src_div;
238 unsigned int speed_hz; /* The speed in transfer */
239 enum mtk_trans_op op;
240 u16 timing_reg;
241 u16 high_speed_reg;
242 u16 ltiming_reg;
243 unsigned char auto_restart;
244 bool ignore_restart_irq;
245 const struct mtk_i2c_compatible *dev_comp;
246};
247
248static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
249 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
250 .max_num_msgs = 1,
251 .max_write_len = 255,
252 .max_read_len = 255,
253 .max_comb_1st_msg_len = 255,
254 .max_comb_2nd_msg_len = 31,
255};
256
257static const struct i2c_adapter_quirks mt7622_i2c_quirks = {
258 .max_num_msgs = 255,
259};
260
261static const struct mtk_i2c_compatible mt2712_compat = {
262 .regs = mt_i2c_regs_v1,
263 .pmic_i2c = 0,
264 .dcm = 1,
265 .auto_restart = 1,
266 .aux_len_reg = 1,
267 .support_33bits = 1,
268 .timing_adjust = 1,
269};
270
271static const struct mtk_i2c_compatible mt6577_compat = {
272 .quirks = &mt6577_i2c_quirks,
273 .regs = mt_i2c_regs_v1,
274 .pmic_i2c = 0,
275 .dcm = 1,
276 .auto_restart = 0,
277 .aux_len_reg = 0,
278 .support_33bits = 0,
279 .timing_adjust = 0,
280};
281
282static const struct mtk_i2c_compatible mt6589_compat = {
283 .quirks = &mt6577_i2c_quirks,
284 .regs = mt_i2c_regs_v1,
285 .pmic_i2c = 1,
286 .dcm = 0,
287 .auto_restart = 0,
288 .aux_len_reg = 0,
289 .support_33bits = 0,
290 .timing_adjust = 0,
291};
292
293static const struct mtk_i2c_compatible mt7622_compat = {
294 .quirks = &mt7622_i2c_quirks,
295 .regs = mt_i2c_regs_v1,
296 .pmic_i2c = 0,
297 .dcm = 1,
298 .auto_restart = 1,
299 .aux_len_reg = 1,
300 .support_33bits = 0,
301 .timing_adjust = 0,
302};
303
304static const struct mtk_i2c_compatible mt8173_compat = {
305 .regs = mt_i2c_regs_v1,
306 .pmic_i2c = 0,
307 .dcm = 1,
308 .auto_restart = 1,
309 .aux_len_reg = 1,
310 .support_33bits = 1,
311 .timing_adjust = 0,
312};
313
314static const struct mtk_i2c_compatible mt8183_compat = {
315 .regs = mt_i2c_regs_v2,
316 .pmic_i2c = 0,
317 .dcm = 0,
318 .auto_restart = 1,
319 .aux_len_reg = 1,
320 .support_33bits = 1,
321 .timing_adjust = 1,
322};
323
324static const struct of_device_id mtk_i2c_of_match[] = {
325 { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat },
326 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
327 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
328 { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
329 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
330 { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
331 {}
332};
333MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
334
335static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg)
336{
337 return readw(i2c->base + i2c->ch_offset + i2c->dev_comp->regs[reg]);
338}
339
340static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val,
341 enum I2C_REGS_OFFSET reg)
342{
343 writew(val, i2c->base + i2c->ch_offset + i2c->dev_comp->regs[reg]);
344}
345
346static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
347{
348 int ret;
349
350 ret = clk_prepare_enable(i2c->clk_dma);
351 if (ret)
352 return ret;
353
354 ret = clk_prepare_enable(i2c->clk_main);
355 if (ret)
356 goto err_main;
357
358 if (i2c->have_pmic) {
359 ret = clk_prepare_enable(i2c->clk_pmic);
360 if (ret)
361 goto err_pmic;
362 }
363
364 if (i2c->clk_arb) {
365 ret = clk_prepare_enable(i2c->clk_arb);
366 if (ret)
367 goto err_arb;
368 }
369
370 return 0;
371
372err_arb:
373 if (i2c->have_pmic)
374 clk_disable_unprepare(i2c->clk_pmic);
375err_pmic:
376 clk_disable_unprepare(i2c->clk_main);
377err_main:
378 clk_disable_unprepare(i2c->clk_dma);
379
380 return ret;
381}
382
383static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
384{
385 if (i2c->clk_arb)
386 clk_disable_unprepare(i2c->clk_arb);
387
388 if (i2c->have_pmic)
389 clk_disable_unprepare(i2c->clk_pmic);
390
391 clk_disable_unprepare(i2c->clk_main);
392 clk_disable_unprepare(i2c->clk_dma);
393}
394
395static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
396{
397 u16 control_reg;
398
399 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET);
400
401 /* Set ioconfig */
402 if (i2c->use_push_pull)
403 mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG);
404 else
405 mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG);
406
407 if (i2c->dev_comp->dcm)
408 mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN);
409
410 if (i2c->ch_offset)
411 writew(I2C_RESUME_ARBIT, i2c->base +
412 i2c->dev_comp->regs[OFFSET_START]);
413
414 if (i2c->dev_comp->timing_adjust)
415 mtk_i2c_writew(i2c, (I2C_DEFAULT_CLK_DIV - 1) |
416 (I2C_DEFAULT_CLK_DIV - 1) << 8,
417 OFFSET_CLOCK_DIV);
418
419 mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING);
420 mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS);
421 if (i2c->dev_comp->regs == mt_i2c_regs_v2)
422 mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING);
423
424 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
425 if (i2c->have_pmic)
426 mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR);
427
428 control_reg = I2C_CONTROL_ACKERR_DET_EN | I2C_CONTROL_DMAACK_EN |
429 I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN |
430 I2C_CONTROL_ASYNC_MODE;
431 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
432 mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN);
433
434 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
435 udelay(50);
436 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
437}
438
439/*
440 * Calculate i2c port speed
441 *
442 * Hardware design:
443 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
444 * clock_div: fixed in hardware, but may be various in different SoCs
445 *
446 * The calculation want to pick the highest bus frequency that is still
447 * less than or equal to i2c->speed_hz. The calculation try to get
448 * sample_cnt and step_cn
449 */
450static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src,
451 unsigned int target_speed,
452 unsigned int *timing_step_cnt,
453 unsigned int *timing_sample_cnt)
454{
455 unsigned int step_cnt;
456 unsigned int sample_cnt;
457 unsigned int max_step_cnt;
458 unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV;
459 unsigned int base_step_cnt;
460 unsigned int opt_div;
461 unsigned int best_mul;
462 unsigned int cnt_mul;
463
464 if (target_speed > MAX_HS_MODE_SPEED)
465 target_speed = MAX_HS_MODE_SPEED;
466
467 if (target_speed > MAX_FS_MODE_SPEED)
468 max_step_cnt = MAX_HS_STEP_CNT_DIV;
469 else
470 max_step_cnt = MAX_STEP_CNT_DIV;
471
472 base_step_cnt = max_step_cnt;
473 /* Find the best combination */
474 opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
475 best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
476
477 /* Search for the best pair (sample_cnt, step_cnt) with
478 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
479 * 0 < step_cnt < max_step_cnt
480 * sample_cnt * step_cnt >= opt_div
481 * optimizing for sample_cnt * step_cnt being minimal
482 */
483 for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
484 step_cnt = DIV_ROUND_UP(opt_div, sample_cnt);
485 cnt_mul = step_cnt * sample_cnt;
486 if (step_cnt > max_step_cnt)
487 continue;
488
489 if (cnt_mul < best_mul) {
490 best_mul = cnt_mul;
491 base_sample_cnt = sample_cnt;
492 base_step_cnt = step_cnt;
493 if (best_mul == opt_div)
494 break;
495 }
496 }
497
498 sample_cnt = base_sample_cnt;
499 step_cnt = base_step_cnt;
500
501 if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) {
502 /* In this case, hardware can't support such
503 * low i2c_bus_freq
504 */
505 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed);
506 return -EINVAL;
507 }
508
509 *timing_step_cnt = step_cnt - 1;
510 *timing_sample_cnt = sample_cnt - 1;
511
512 return 0;
513}
514
515static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
516{
517 unsigned int clk_src;
518 unsigned int step_cnt;
519 unsigned int sample_cnt;
520 unsigned int l_step_cnt;
521 unsigned int l_sample_cnt;
522 unsigned int target_speed;
523 int ret;
524
525 clk_src = parent_clk / i2c->clk_src_div;
526 target_speed = i2c->speed_hz;
527
528 if (target_speed > MAX_FS_MODE_SPEED) {
529 /* Set master code speed register */
530 ret = mtk_i2c_calculate_speed(i2c, clk_src, MAX_FS_MODE_SPEED,
531 &l_step_cnt, &l_sample_cnt);
532 if (ret < 0)
533 return ret;
534
535 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
536
537 /* Set the high speed mode register */
538 ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
539 &step_cnt, &sample_cnt);
540 if (ret < 0)
541 return ret;
542
543 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
544 (sample_cnt << 12) | (step_cnt << 8);
545 i2c->ltiming_reg = (l_sample_cnt << 6) | l_step_cnt |
546 (sample_cnt << 12) | (step_cnt << 9);
547 } else {
548 ret = mtk_i2c_calculate_speed(i2c, clk_src, target_speed,
549 &step_cnt, &sample_cnt);
550 if (ret < 0)
551 return ret;
552
553 i2c->timing_reg = (sample_cnt << 8) | step_cnt;
554
555 /* Disable the high speed transaction */
556 i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
557
558 i2c->ltiming_reg = (sample_cnt << 6) | step_cnt;
559 }
560
561 return 0;
562}
563
564static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr)
565{
566 return (addr & BIT_ULL(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;
567}
568
569static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
570 int num, int left_num)
571{
572 u16 addr_reg;
573 u16 start_reg;
574 u16 control_reg;
575 u16 restart_flag = 0;
576 u32 reg_4g_mode;
577 u8 *w_buf = NULL;
578 u8 *r_buf = NULL;
579 dma_addr_t rpaddr = 0;
580 dma_addr_t wpaddr = 0;
581 int ret;
582
583 i2c->irq_stat = 0;
584
585 if (i2c->auto_restart)
586 restart_flag = I2C_RS_TRANSFER;
587
588 reinit_completion(&i2c->msg_complete);
589
590 control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
591 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
592 if ((i2c->speed_hz > 400000) || (left_num >= 1))
593 control_reg |= I2C_CONTROL_RS;
594
595 if (i2c->op == I2C_MASTER_WRRD)
596 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
597
598 mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
599
600 /* set start condition */
601 if (i2c->speed_hz <= 100000)
602 mtk_i2c_writew(i2c, I2C_ST_START_CON, OFFSET_EXT_CONF);
603 else
604 mtk_i2c_writew(i2c, I2C_FS_START_CON, OFFSET_EXT_CONF);
605
606 addr_reg = i2c_8bit_addr_from_msg(msgs);
607 mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR);
608
609 /* Clear interrupt status */
610 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
611 I2C_ARB_LOST | I2C_TRANSAC_COMP,
612 OFFSET_INTR_STAT);
613
614 mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR_MCH | I2C_FIFO_ADDR_CLR,
615 OFFSET_FIFO_ADDR_CLR);
616
617 if ((i2c->speed_hz > 400000) && (i2c->dev_comp->regs == mt_i2c_regs_v2))
618 mtk_i2c_writew(i2c, I2C_HFIFO_DATA, OFFSET_HFIFO_DATA);
619
620 /* Enable interrupt */
621 mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
622 I2C_ARB_LOST | I2C_TRANSAC_COMP,
623 OFFSET_INTR_MASK);
624
625 /* Set transfer and transaction len */
626 if (i2c->op == I2C_MASTER_WRRD) {
627 if (i2c->dev_comp->aux_len_reg) {
628 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
629 mtk_i2c_writew(i2c, (msgs + 1)->len,
630 OFFSET_TRANSFER_LEN_AUX);
631 } else {
632 mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8,
633 OFFSET_TRANSFER_LEN);
634 }
635 mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN);
636 } else {
637 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
638 mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
639 }
640
641 /* Prepare buffer data to start transfer */
642 if (i2c->op == I2C_MASTER_RD) {
643 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
644 writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON);
645
646 r_buf = kzalloc(msgs->len, GFP_KERNEL);
647 if (r_buf == NULL)
648 return -ENOMEM;
649
650 rpaddr = dma_map_single(i2c->dev, r_buf,
651 msgs->len, DMA_FROM_DEVICE);
652 if (dma_mapping_error(i2c->dev, rpaddr)) {
653 kfree(r_buf);
654 return -ENOMEM;
655 }
656
657 if (i2c->dev_comp->support_33bits) {
658 reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
659 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
660 }
661
662 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
663 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
664 } else if (i2c->op == I2C_MASTER_WR) {
665 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
666 writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON);
667
668 w_buf = kzalloc(msgs->len, GFP_KERNEL);
669 if (w_buf == NULL)
670 return -ENOMEM;
671
672 memcpy(w_buf, msgs->buf, msgs->len);
673
674 wpaddr = dma_map_single(i2c->dev, w_buf,
675 msgs->len, DMA_TO_DEVICE);
676 if (dma_mapping_error(i2c->dev, wpaddr)) {
677 kfree(w_buf);
678 return -ENOMEM;
679 }
680
681 if (i2c->dev_comp->support_33bits) {
682 reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
683 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
684 }
685
686 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
687 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
688 } else {
689 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
690 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON);
691
692 w_buf = kzalloc(msgs->len, GFP_KERNEL);
693 if (w_buf == NULL)
694 return -ENOMEM;
695 r_buf = kzalloc((msgs + 1)->len, GFP_KERNEL);
696 if (r_buf == NULL) {
697 kfree(w_buf);
698 return -ENOMEM;
699 }
700
701 memcpy(w_buf, msgs->buf, msgs->len);
702
703 wpaddr = dma_map_single(i2c->dev, w_buf,
704 msgs->len, DMA_TO_DEVICE);
705 if (dma_mapping_error(i2c->dev, wpaddr)) {
706 kfree(w_buf);
707 kfree(r_buf);
708 return -ENOMEM;
709 }
710 rpaddr = dma_map_single(i2c->dev, r_buf,
711 (msgs + 1)->len,
712 DMA_FROM_DEVICE);
713 if (dma_mapping_error(i2c->dev, rpaddr)) {
714 dma_unmap_single(i2c->dev, wpaddr,
715 msgs->len, DMA_TO_DEVICE);
716 kfree(w_buf);
717 kfree(r_buf);
718 return -ENOMEM;
719 }
720
721 if (i2c->dev_comp->support_33bits) {
722 reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
723 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
724
725 reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
726 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
727 }
728
729 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
730 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
731 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
732 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN);
733 }
734
735 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN);
736
737 if (!i2c->auto_restart) {
738 start_reg = I2C_TRANSAC_START;
739 } else {
740 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
741 if (left_num >= 1)
742 start_reg |= I2C_RS_MUL_CNFG;
743 }
744 mtk_i2c_writew(i2c, start_reg, OFFSET_START);
745
746 ret = wait_for_completion_timeout(&i2c->msg_complete,
747 i2c->adap.timeout);
748
749 /* Clear interrupt mask */
750 mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
751 I2C_TRANSAC_COMP), OFFSET_INTR_MASK);
752
753 if (i2c->op == I2C_MASTER_WR) {
754 dma_unmap_single(i2c->dev, wpaddr,
755 msgs->len, DMA_TO_DEVICE);
756 kfree(w_buf);
757 } else if (i2c->op == I2C_MASTER_RD) {
758 dma_unmap_single(i2c->dev, rpaddr,
759 msgs->len, DMA_FROM_DEVICE);
760 memcpy(msgs->buf, r_buf, msgs->len);
761 kfree(r_buf);
762 } else {
763 dma_unmap_single(i2c->dev, wpaddr, msgs->len,
764 DMA_TO_DEVICE);
765 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len,
766 DMA_FROM_DEVICE);
767 memcpy((msgs + 1)->buf, r_buf, (msgs + 1)->len);
768 kfree(w_buf);
769 kfree(r_buf);
770 }
771
772 if (ret == 0) {
773 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
774 mtk_i2c_init_hw(i2c);
775 return -ETIMEDOUT;
776 }
777
778 completion_done(&i2c->msg_complete);
779
780 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
781 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
782 mtk_i2c_init_hw(i2c);
783 return -ENXIO;
784 }
785
786 return 0;
787}
788
789static int mtk_i2c_transfer(struct i2c_adapter *adap,
790 struct i2c_msg msgs[], int num)
791{
792 int ret;
793 int left_num = num;
794 struct mtk_i2c *i2c = i2c_get_adapdata(adap);
795
796 ret = mtk_i2c_clock_enable(i2c);
797 if (ret)
798 return ret;
799
800 i2c->auto_restart = i2c->dev_comp->auto_restart;
801
802 /* checking if we can skip restart and optimize using WRRD mode */
803 if (i2c->auto_restart && num == 2) {
804 if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) &&
805 msgs[0].addr == msgs[1].addr) {
806 i2c->auto_restart = 0;
807 }
808 }
809
810 if (i2c->auto_restart && num >= 2 && i2c->speed_hz > MAX_FS_MODE_SPEED)
811 /* ignore the first restart irq after the master code,
812 * otherwise the first transfer will be discarded.
813 */
814 i2c->ignore_restart_irq = true;
815 else
816 i2c->ignore_restart_irq = false;
817
818 while (left_num--) {
819 if (!msgs->buf) {
820 dev_dbg(i2c->dev, "data buffer is NULL.\n");
821 ret = -EINVAL;
822 goto err_exit;
823 }
824
825 if (msgs->flags & I2C_M_RD)
826 i2c->op = I2C_MASTER_RD;
827 else
828 i2c->op = I2C_MASTER_WR;
829
830 if (!i2c->auto_restart) {
831 if (num > 1) {
832 /* combined two messages into one transaction */
833 i2c->op = I2C_MASTER_WRRD;
834 left_num--;
835 }
836 }
837
838 /* always use DMA mode. */
839 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
840 if (ret < 0)
841 goto err_exit;
842
843 msgs++;
844 }
845 /* the return value is number of executed messages */
846 ret = num;
847
848err_exit:
849 mtk_i2c_clock_disable(i2c);
850 return ret;
851}
852
853static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
854{
855 struct mtk_i2c *i2c = dev_id;
856 u16 restart_flag = 0;
857 u16 intr_stat;
858
859 if (i2c->auto_restart)
860 restart_flag = I2C_RS_TRANSFER;
861
862 intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
863 mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT);
864
865 /*
866 * when occurs ack error, i2c controller generate two interrupts
867 * first is the ack error interrupt, then the complete interrupt
868 * i2c->irq_stat need keep the two interrupt value.
869 */
870 i2c->irq_stat |= intr_stat;
871
872 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) {
873 i2c->ignore_restart_irq = false;
874 i2c->irq_stat = 0;
875 mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG |
876 I2C_TRANSAC_START, OFFSET_START);
877 } else {
878 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
879 complete(&i2c->msg_complete);
880 }
881
882 return IRQ_HANDLED;
883}
884
885static u32 mtk_i2c_functionality(struct i2c_adapter *adap)
886{
887 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
888}
889
890static const struct i2c_algorithm mtk_i2c_algorithm = {
891 .master_xfer = mtk_i2c_transfer,
892 .functionality = mtk_i2c_functionality,
893};
894
895static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c)
896{
897 int ret;
898
899 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz);
900 if (ret < 0)
901 i2c->speed_hz = I2C_DEFAULT_SPEED;
902
903 ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div);
904 if (ret < 0)
905 return ret;
906
907 if (i2c->clk_src_div == 0)
908 return -EINVAL;
909
910 ret = of_property_read_u32(np, "ch_offset", &i2c->ch_offset);
911 if (ret < 0)
912 i2c->ch_offset = 0;
913
914 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
915 i2c->use_push_pull =
916 of_property_read_bool(np, "mediatek,use-push-pull");
917
918 return 0;
919}
920
921static int mtk_i2c_probe(struct platform_device *pdev)
922{
923 const struct of_device_id *of_id;
924 int ret = 0;
925 struct mtk_i2c *i2c;
926 struct clk *clk;
927 struct resource *res;
928 int irq;
929
930 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
931 if (!i2c)
932 return -ENOMEM;
933
934 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
935 i2c->base = devm_ioremap_resource(&pdev->dev, res);
936 if (IS_ERR(i2c->base))
937 return PTR_ERR(i2c->base);
938
939 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
940 i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
941 if (IS_ERR(i2c->pdmabase))
942 return PTR_ERR(i2c->pdmabase);
943
944 irq = platform_get_irq(pdev, 0);
945 if (irq <= 0)
946 return irq;
947
948 init_completion(&i2c->msg_complete);
949
950 of_id = of_match_node(mtk_i2c_of_match, pdev->dev.of_node);
951 if (!of_id)
952 return -EINVAL;
953
954 i2c->dev_comp = of_id->data;
955 i2c->adap.dev.of_node = pdev->dev.of_node;
956 i2c->dev = &pdev->dev;
957 i2c->adap.dev.parent = &pdev->dev;
958 i2c->adap.owner = THIS_MODULE;
959 i2c->adap.algo = &mtk_i2c_algorithm;
960 i2c->adap.quirks = i2c->dev_comp->quirks;
961 i2c->adap.timeout = 2 * HZ;
962 i2c->adap.retries = 1;
963
964 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c);
965 if (ret)
966 return -EINVAL;
967
968 if (i2c->dev_comp->timing_adjust)
969 i2c->clk_src_div *= I2C_DEFAULT_CLK_DIV;
970
971 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
972 return -EINVAL;
973
974 i2c->clk_main = devm_clk_get(&pdev->dev, "main");
975 if (IS_ERR(i2c->clk_main)) {
976 dev_err(&pdev->dev, "cannot get main clock\n");
977 return PTR_ERR(i2c->clk_main);
978 }
979
980 i2c->clk_dma = devm_clk_get(&pdev->dev, "dma");
981 if (IS_ERR(i2c->clk_dma)) {
982 dev_err(&pdev->dev, "cannot get dma clock\n");
983 return PTR_ERR(i2c->clk_dma);
984 }
985
986 i2c->clk_arb = devm_clk_get(&pdev->dev, "arb");
987 if (IS_ERR(i2c->clk_arb))
988 i2c->clk_arb = NULL;
989
990 clk = i2c->clk_main;
991 if (i2c->have_pmic) {
992 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
993 if (IS_ERR(i2c->clk_pmic)) {
994 dev_err(&pdev->dev, "cannot get pmic clock\n");
995 return PTR_ERR(i2c->clk_pmic);
996 }
997 clk = i2c->clk_pmic;
998 }
999
1000 strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
1001
1002 ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk));
1003 if (ret) {
1004 dev_err(&pdev->dev, "Failed to set the speed.\n");
1005 return -EINVAL;
1006 }
1007
1008 if (i2c->dev_comp->support_33bits) {
1009 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(33));
1010 if (ret) {
1011 dev_err(&pdev->dev, "dma_set_mask return error.\n");
1012 return ret;
1013 }
1014 }
1015
1016 ret = mtk_i2c_clock_enable(i2c);
1017 if (ret) {
1018 dev_err(&pdev->dev, "clock enable failed!\n");
1019 return ret;
1020 }
1021 mtk_i2c_init_hw(i2c);
1022 mtk_i2c_clock_disable(i2c);
1023
1024 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
1025 IRQF_TRIGGER_NONE, I2C_DRV_NAME, i2c);
1026 if (ret < 0) {
1027 dev_err(&pdev->dev,
1028 "Request I2C IRQ %d fail\n", irq);
1029 return ret;
1030 }
1031
1032 i2c_set_adapdata(&i2c->adap, i2c);
1033 ret = i2c_add_adapter(&i2c->adap);
1034 if (ret)
1035 return ret;
1036
1037 platform_set_drvdata(pdev, i2c);
1038
1039 return 0;
1040}
1041
1042static int mtk_i2c_remove(struct platform_device *pdev)
1043{
1044 struct mtk_i2c *i2c = platform_get_drvdata(pdev);
1045
1046 i2c_del_adapter(&i2c->adap);
1047
1048 return 0;
1049}
1050
1051#ifdef CONFIG_PM_SLEEP
1052static int mtk_i2c_resume(struct device *dev)
1053{
1054 int ret;
1055 struct mtk_i2c *i2c = dev_get_drvdata(dev);
1056
1057 ret = mtk_i2c_clock_enable(i2c);
1058 if (ret) {
1059 dev_dbg(dev, "clock enable failed!\n");
1060 return ret;
1061 }
1062
1063 mtk_i2c_init_hw(i2c);
1064
1065 mtk_i2c_clock_disable(i2c);
1066
1067 return 0;
1068}
1069#endif
1070
1071static const struct dev_pm_ops mtk_i2c_pm = {
1072 SET_SYSTEM_SLEEP_PM_OPS(NULL, mtk_i2c_resume)
1073};
1074
1075static struct platform_driver mtk_i2c_driver = {
1076 .probe = mtk_i2c_probe,
1077 .remove = mtk_i2c_remove,
1078 .driver = {
1079 .name = I2C_DRV_NAME,
1080 .pm = &mtk_i2c_pm,
1081 .of_match_table = of_match_ptr(mtk_i2c_of_match),
1082 },
1083};
1084
1085module_platform_driver(mtk_i2c_driver);
1086
1087MODULE_LICENSE("GPL v2");
1088MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
1089MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>");