blob: 58f63bc1d20cd47bbd8952b7ceb14da26ffcce52 [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +08001/*
2 * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 *
16 * Copyright (C) 2013 ARM Limited
17 * Copyright (C) 2017 Red Hat
18 */
19
20#include <linux/atomic.h>
21#include <linux/clk.h>
22#include <linux/delay.h>
23#include <linux/dma-iommu.h>
24#include <linux/dma-mapping.h>
25#include <linux/err.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/io-64-nonatomic-hi-lo.h>
29#include <linux/iommu.h>
30#include <linux/iopoll.h>
31#include <linux/kconfig.h>
32#include <linux/module.h>
33#include <linux/mutex.h>
34#include <linux/of.h>
35#include <linux/of_address.h>
36#include <linux/of_device.h>
37#include <linux/of_iommu.h>
38#include <linux/platform_device.h>
39#include <linux/pm.h>
40#include <linux/pm_runtime.h>
41#include <linux/qcom_scm.h>
42#include <linux/slab.h>
43#include <linux/spinlock.h>
44
45#include "io-pgtable.h"
46#include "arm-smmu-regs.h"
47
48#define SMMU_INTR_SEL_NS 0x2000
49
50struct qcom_iommu_ctx;
51
52struct qcom_iommu_dev {
53 /* IOMMU core code handle */
54 struct iommu_device iommu;
55 struct device *dev;
56 struct clk *iface_clk;
57 struct clk *bus_clk;
58 void __iomem *local_base;
59 u32 sec_id;
60 u8 num_ctxs;
61 struct qcom_iommu_ctx *ctxs[0]; /* indexed by asid-1 */
62};
63
64struct qcom_iommu_ctx {
65 struct device *dev;
66 void __iomem *base;
67 bool secure_init;
68 u8 asid; /* asid and ctx bank # are 1:1 */
69};
70
71struct qcom_iommu_domain {
72 struct io_pgtable_ops *pgtbl_ops;
73 spinlock_t pgtbl_lock;
74 struct mutex init_mutex; /* Protects iommu pointer */
75 struct iommu_domain domain;
76 struct qcom_iommu_dev *iommu;
77};
78
79static struct qcom_iommu_domain *to_qcom_iommu_domain(struct iommu_domain *dom)
80{
81 return container_of(dom, struct qcom_iommu_domain, domain);
82}
83
84static const struct iommu_ops qcom_iommu_ops;
85
86static struct qcom_iommu_dev * to_iommu(struct iommu_fwspec *fwspec)
87{
88 if (!fwspec || fwspec->ops != &qcom_iommu_ops)
89 return NULL;
90 return fwspec->iommu_priv;
91}
92
93static struct qcom_iommu_ctx * to_ctx(struct iommu_fwspec *fwspec, unsigned asid)
94{
95 struct qcom_iommu_dev *qcom_iommu = to_iommu(fwspec);
96 if (!qcom_iommu)
97 return NULL;
98 return qcom_iommu->ctxs[asid - 1];
99}
100
101static inline void
102iommu_writel(struct qcom_iommu_ctx *ctx, unsigned reg, u32 val)
103{
104 writel_relaxed(val, ctx->base + reg);
105}
106
107static inline void
108iommu_writeq(struct qcom_iommu_ctx *ctx, unsigned reg, u64 val)
109{
110 writeq_relaxed(val, ctx->base + reg);
111}
112
113static inline u32
114iommu_readl(struct qcom_iommu_ctx *ctx, unsigned reg)
115{
116 return readl_relaxed(ctx->base + reg);
117}
118
119static inline u64
120iommu_readq(struct qcom_iommu_ctx *ctx, unsigned reg)
121{
122 return readq_relaxed(ctx->base + reg);
123}
124
125static void qcom_iommu_tlb_sync(void *cookie)
126{
127 struct iommu_fwspec *fwspec = cookie;
128 unsigned i;
129
130 for (i = 0; i < fwspec->num_ids; i++) {
131 struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
132 unsigned int val, ret;
133
134 iommu_writel(ctx, ARM_SMMU_CB_TLBSYNC, 0);
135
136 ret = readl_poll_timeout(ctx->base + ARM_SMMU_CB_TLBSTATUS, val,
137 (val & 0x1) == 0, 0, 5000000);
138 if (ret)
139 dev_err(ctx->dev, "timeout waiting for TLB SYNC\n");
140 }
141}
142
143static void qcom_iommu_tlb_inv_context(void *cookie)
144{
145 struct iommu_fwspec *fwspec = cookie;
146 unsigned i;
147
148 for (i = 0; i < fwspec->num_ids; i++) {
149 struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
150 iommu_writel(ctx, ARM_SMMU_CB_S1_TLBIASID, ctx->asid);
151 }
152
153 qcom_iommu_tlb_sync(cookie);
154}
155
156static void qcom_iommu_tlb_inv_range_nosync(unsigned long iova, size_t size,
157 size_t granule, bool leaf, void *cookie)
158{
159 struct iommu_fwspec *fwspec = cookie;
160 unsigned i, reg;
161
162 reg = leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;
163
164 for (i = 0; i < fwspec->num_ids; i++) {
165 struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
166 size_t s = size;
167
168 iova &= ~12UL;
169 iova |= ctx->asid;
170 do {
171 iommu_writel(ctx, reg, iova);
172 iova += granule;
173 } while (s -= granule);
174 }
175}
176
177static const struct iommu_gather_ops qcom_gather_ops = {
178 .tlb_flush_all = qcom_iommu_tlb_inv_context,
179 .tlb_add_flush = qcom_iommu_tlb_inv_range_nosync,
180 .tlb_sync = qcom_iommu_tlb_sync,
181};
182
183static irqreturn_t qcom_iommu_fault(int irq, void *dev)
184{
185 struct qcom_iommu_ctx *ctx = dev;
186 u32 fsr, fsynr;
187 u64 iova;
188
189 fsr = iommu_readl(ctx, ARM_SMMU_CB_FSR);
190
191 if (!(fsr & FSR_FAULT))
192 return IRQ_NONE;
193
194 fsynr = iommu_readl(ctx, ARM_SMMU_CB_FSYNR0);
195 iova = iommu_readq(ctx, ARM_SMMU_CB_FAR);
196
197 dev_err_ratelimited(ctx->dev,
198 "Unhandled context fault: fsr=0x%x, "
199 "iova=0x%016llx, fsynr=0x%x, cb=%d\n",
200 fsr, iova, fsynr, ctx->asid);
201
202 iommu_writel(ctx, ARM_SMMU_CB_FSR, fsr);
203
204 return IRQ_HANDLED;
205}
206
207static int qcom_iommu_init_domain(struct iommu_domain *domain,
208 struct qcom_iommu_dev *qcom_iommu,
209 struct iommu_fwspec *fwspec)
210{
211 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
212 struct io_pgtable_ops *pgtbl_ops;
213 struct io_pgtable_cfg pgtbl_cfg;
214 int i, ret = 0;
215 u32 reg;
216
217 mutex_lock(&qcom_domain->init_mutex);
218 if (qcom_domain->iommu)
219 goto out_unlock;
220
221 pgtbl_cfg = (struct io_pgtable_cfg) {
222 .pgsize_bitmap = qcom_iommu_ops.pgsize_bitmap,
223 .ias = 32,
224 .oas = 40,
225 .tlb = &qcom_gather_ops,
226 .iommu_dev = qcom_iommu->dev,
227 };
228
229 qcom_domain->iommu = qcom_iommu;
230 pgtbl_ops = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &pgtbl_cfg, fwspec);
231 if (!pgtbl_ops) {
232 dev_err(qcom_iommu->dev, "failed to allocate pagetable ops\n");
233 ret = -ENOMEM;
234 goto out_clear_iommu;
235 }
236
237 /* Update the domain's page sizes to reflect the page table format */
238 domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
239 domain->geometry.aperture_end = (1ULL << pgtbl_cfg.ias) - 1;
240 domain->geometry.force_aperture = true;
241
242 for (i = 0; i < fwspec->num_ids; i++) {
243 struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
244
245 if (!ctx->secure_init) {
246 ret = qcom_scm_restore_sec_cfg(qcom_iommu->sec_id, ctx->asid);
247 if (ret) {
248 dev_err(qcom_iommu->dev, "secure init failed: %d\n", ret);
249 goto out_clear_iommu;
250 }
251 ctx->secure_init = true;
252 }
253
254 /* TTBRs */
255 iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
256 pgtbl_cfg.arm_lpae_s1_cfg.ttbr[0] |
257 ((u64)ctx->asid << TTBRn_ASID_SHIFT));
258 iommu_writeq(ctx, ARM_SMMU_CB_TTBR1,
259 pgtbl_cfg.arm_lpae_s1_cfg.ttbr[1] |
260 ((u64)ctx->asid << TTBRn_ASID_SHIFT));
261
262 /* TTBCR */
263 iommu_writel(ctx, ARM_SMMU_CB_TTBCR2,
264 (pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) |
265 TTBCR2_SEP_UPSTREAM);
266 iommu_writel(ctx, ARM_SMMU_CB_TTBCR,
267 pgtbl_cfg.arm_lpae_s1_cfg.tcr);
268
269 /* MAIRs (stage-1 only) */
270 iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0,
271 pgtbl_cfg.arm_lpae_s1_cfg.mair[0]);
272 iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1,
273 pgtbl_cfg.arm_lpae_s1_cfg.mair[1]);
274
275 /* SCTLR */
276 reg = SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE |
277 SCTLR_M | SCTLR_S1_ASIDPNE;
278
279 if (IS_ENABLED(CONFIG_BIG_ENDIAN))
280 reg |= SCTLR_E;
281
282 iommu_writel(ctx, ARM_SMMU_CB_SCTLR, reg);
283 }
284
285 mutex_unlock(&qcom_domain->init_mutex);
286
287 /* Publish page table ops for map/unmap */
288 qcom_domain->pgtbl_ops = pgtbl_ops;
289
290 return 0;
291
292out_clear_iommu:
293 qcom_domain->iommu = NULL;
294out_unlock:
295 mutex_unlock(&qcom_domain->init_mutex);
296 return ret;
297}
298
299static struct iommu_domain *qcom_iommu_domain_alloc(unsigned type)
300{
301 struct qcom_iommu_domain *qcom_domain;
302
303 if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
304 return NULL;
305 /*
306 * Allocate the domain and initialise some of its data structures.
307 * We can't really do anything meaningful until we've added a
308 * master.
309 */
310 qcom_domain = kzalloc(sizeof(*qcom_domain), GFP_KERNEL);
311 if (!qcom_domain)
312 return NULL;
313
314 if (type == IOMMU_DOMAIN_DMA &&
315 iommu_get_dma_cookie(&qcom_domain->domain)) {
316 kfree(qcom_domain);
317 return NULL;
318 }
319
320 mutex_init(&qcom_domain->init_mutex);
321 spin_lock_init(&qcom_domain->pgtbl_lock);
322
323 return &qcom_domain->domain;
324}
325
326static void qcom_iommu_domain_free(struct iommu_domain *domain)
327{
328 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
329
330 iommu_put_dma_cookie(domain);
331
332 if (qcom_domain->iommu) {
333 /*
334 * NOTE: unmap can be called after client device is powered
335 * off, for example, with GPUs or anything involving dma-buf.
336 * So we cannot rely on the device_link. Make sure the IOMMU
337 * is on to avoid unclocked accesses in the TLB inv path:
338 */
339 pm_runtime_get_sync(qcom_domain->iommu->dev);
340 free_io_pgtable_ops(qcom_domain->pgtbl_ops);
341 pm_runtime_put_sync(qcom_domain->iommu->dev);
342 }
343
344 kfree(qcom_domain);
345}
346
347static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
348{
349 struct qcom_iommu_dev *qcom_iommu = to_iommu(dev->iommu_fwspec);
350 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
351 int ret;
352
353 if (!qcom_iommu) {
354 dev_err(dev, "cannot attach to IOMMU, is it on the same bus?\n");
355 return -ENXIO;
356 }
357
358 /* Ensure that the domain is finalized */
359 pm_runtime_get_sync(qcom_iommu->dev);
360 ret = qcom_iommu_init_domain(domain, qcom_iommu, dev->iommu_fwspec);
361 pm_runtime_put_sync(qcom_iommu->dev);
362 if (ret < 0)
363 return ret;
364
365 /*
366 * Sanity check the domain. We don't support domains across
367 * different IOMMUs.
368 */
369 if (qcom_domain->iommu != qcom_iommu) {
370 dev_err(dev, "cannot attach to IOMMU %s while already "
371 "attached to domain on IOMMU %s\n",
372 dev_name(qcom_domain->iommu->dev),
373 dev_name(qcom_iommu->dev));
374 return -EINVAL;
375 }
376
377 return 0;
378}
379
380static void qcom_iommu_detach_dev(struct iommu_domain *domain, struct device *dev)
381{
382 struct iommu_fwspec *fwspec = dev->iommu_fwspec;
383 struct qcom_iommu_dev *qcom_iommu = to_iommu(fwspec);
384 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
385 unsigned i;
386
387 if (WARN_ON(!qcom_domain->iommu))
388 return;
389
390 pm_runtime_get_sync(qcom_iommu->dev);
391 for (i = 0; i < fwspec->num_ids; i++) {
392 struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
393
394 /* Disable the context bank: */
395 iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
396 }
397 pm_runtime_put_sync(qcom_iommu->dev);
398}
399
400static int qcom_iommu_map(struct iommu_domain *domain, unsigned long iova,
401 phys_addr_t paddr, size_t size, int prot)
402{
403 int ret;
404 unsigned long flags;
405 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
406 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
407
408 if (!ops)
409 return -ENODEV;
410
411 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
412 ret = ops->map(ops, iova, paddr, size, prot);
413 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
414 return ret;
415}
416
417static size_t qcom_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
418 size_t size)
419{
420 size_t ret;
421 unsigned long flags;
422 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
423 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
424
425 if (!ops)
426 return 0;
427
428 /* NOTE: unmap can be called after client device is powered off,
429 * for example, with GPUs or anything involving dma-buf. So we
430 * cannot rely on the device_link. Make sure the IOMMU is on to
431 * avoid unclocked accesses in the TLB inv path:
432 */
433 pm_runtime_get_sync(qcom_domain->iommu->dev);
434 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
435 ret = ops->unmap(ops, iova, size);
436 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
437 pm_runtime_put_sync(qcom_domain->iommu->dev);
438
439 return ret;
440}
441
442static void qcom_iommu_iotlb_sync(struct iommu_domain *domain)
443{
444 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
445 struct io_pgtable *pgtable = container_of(qcom_domain->pgtbl_ops,
446 struct io_pgtable, ops);
447 if (!qcom_domain->pgtbl_ops)
448 return;
449
450 pm_runtime_get_sync(qcom_domain->iommu->dev);
451 qcom_iommu_tlb_sync(pgtable->cookie);
452 pm_runtime_put_sync(qcom_domain->iommu->dev);
453}
454
455static phys_addr_t qcom_iommu_iova_to_phys(struct iommu_domain *domain,
456 dma_addr_t iova)
457{
458 phys_addr_t ret;
459 unsigned long flags;
460 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
461 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
462
463 if (!ops)
464 return 0;
465
466 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
467 ret = ops->iova_to_phys(ops, iova);
468 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
469
470 return ret;
471}
472
473static bool qcom_iommu_capable(enum iommu_cap cap)
474{
475 switch (cap) {
476 case IOMMU_CAP_CACHE_COHERENCY:
477 /*
478 * Return true here as the SMMU can always send out coherent
479 * requests.
480 */
481 return true;
482 case IOMMU_CAP_NOEXEC:
483 return true;
484 default:
485 return false;
486 }
487}
488
489static int qcom_iommu_add_device(struct device *dev)
490{
491 struct qcom_iommu_dev *qcom_iommu = to_iommu(dev->iommu_fwspec);
492 struct iommu_group *group;
493 struct device_link *link;
494
495 if (!qcom_iommu)
496 return -ENODEV;
497
498 /*
499 * Establish the link between iommu and master, so that the
500 * iommu gets runtime enabled/disabled as per the master's
501 * needs.
502 */
503 link = device_link_add(dev, qcom_iommu->dev, DL_FLAG_PM_RUNTIME);
504 if (!link) {
505 dev_err(qcom_iommu->dev, "Unable to create device link between %s and %s\n",
506 dev_name(qcom_iommu->dev), dev_name(dev));
507 return -ENODEV;
508 }
509
510 group = iommu_group_get_for_dev(dev);
511 if (IS_ERR_OR_NULL(group))
512 return PTR_ERR_OR_ZERO(group);
513
514 iommu_group_put(group);
515 iommu_device_link(&qcom_iommu->iommu, dev);
516
517 return 0;
518}
519
520static void qcom_iommu_remove_device(struct device *dev)
521{
522 struct qcom_iommu_dev *qcom_iommu = to_iommu(dev->iommu_fwspec);
523
524 if (!qcom_iommu)
525 return;
526
527 iommu_device_unlink(&qcom_iommu->iommu, dev);
528 iommu_group_remove_device(dev);
529 iommu_fwspec_free(dev);
530}
531
532static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
533{
534 struct qcom_iommu_dev *qcom_iommu;
535 struct platform_device *iommu_pdev;
536 unsigned asid = args->args[0];
537
538 if (args->args_count != 1) {
539 dev_err(dev, "incorrect number of iommu params found for %s "
540 "(found %d, expected 1)\n",
541 args->np->full_name, args->args_count);
542 return -EINVAL;
543 }
544
545 iommu_pdev = of_find_device_by_node(args->np);
546 if (WARN_ON(!iommu_pdev))
547 return -EINVAL;
548
549 qcom_iommu = platform_get_drvdata(iommu_pdev);
550
551 /* make sure the asid specified in dt is valid, so we don't have
552 * to sanity check this elsewhere, since 'asid - 1' is used to
553 * index into qcom_iommu->ctxs:
554 */
555 if (WARN_ON(asid < 1) ||
556 WARN_ON(asid > qcom_iommu->num_ctxs))
557 return -EINVAL;
558
559 if (!dev->iommu_fwspec->iommu_priv) {
560 dev->iommu_fwspec->iommu_priv = qcom_iommu;
561 } else {
562 /* make sure devices iommus dt node isn't referring to
563 * multiple different iommu devices. Multiple context
564 * banks are ok, but multiple devices are not:
565 */
566 if (WARN_ON(qcom_iommu != dev->iommu_fwspec->iommu_priv))
567 return -EINVAL;
568 }
569
570 return iommu_fwspec_add_ids(dev, &asid, 1);
571}
572
573static const struct iommu_ops qcom_iommu_ops = {
574 .capable = qcom_iommu_capable,
575 .domain_alloc = qcom_iommu_domain_alloc,
576 .domain_free = qcom_iommu_domain_free,
577 .attach_dev = qcom_iommu_attach_dev,
578 .detach_dev = qcom_iommu_detach_dev,
579 .map = qcom_iommu_map,
580 .unmap = qcom_iommu_unmap,
581 .map_sg = default_iommu_map_sg,
582 .flush_iotlb_all = qcom_iommu_iotlb_sync,
583 .iotlb_sync = qcom_iommu_iotlb_sync,
584 .iova_to_phys = qcom_iommu_iova_to_phys,
585 .add_device = qcom_iommu_add_device,
586 .remove_device = qcom_iommu_remove_device,
587 .device_group = generic_device_group,
588 .of_xlate = qcom_iommu_of_xlate,
589 .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
590};
591
592static int qcom_iommu_enable_clocks(struct qcom_iommu_dev *qcom_iommu)
593{
594 int ret;
595
596 ret = clk_prepare_enable(qcom_iommu->iface_clk);
597 if (ret) {
598 dev_err(qcom_iommu->dev, "Couldn't enable iface_clk\n");
599 return ret;
600 }
601
602 ret = clk_prepare_enable(qcom_iommu->bus_clk);
603 if (ret) {
604 dev_err(qcom_iommu->dev, "Couldn't enable bus_clk\n");
605 clk_disable_unprepare(qcom_iommu->iface_clk);
606 return ret;
607 }
608
609 return 0;
610}
611
612static void qcom_iommu_disable_clocks(struct qcom_iommu_dev *qcom_iommu)
613{
614 clk_disable_unprepare(qcom_iommu->bus_clk);
615 clk_disable_unprepare(qcom_iommu->iface_clk);
616}
617
618static int qcom_iommu_sec_ptbl_init(struct device *dev)
619{
620 size_t psize = 0;
621 unsigned int spare = 0;
622 void *cpu_addr;
623 dma_addr_t paddr;
624 unsigned long attrs;
625 static bool allocated = false;
626 int ret;
627
628 if (allocated)
629 return 0;
630
631 ret = qcom_scm_iommu_secure_ptbl_size(spare, &psize);
632 if (ret) {
633 dev_err(dev, "failed to get iommu secure pgtable size (%d)\n",
634 ret);
635 return ret;
636 }
637
638 dev_info(dev, "iommu sec: pgtable size: %zu\n", psize);
639
640 attrs = DMA_ATTR_NO_KERNEL_MAPPING;
641
642 cpu_addr = dma_alloc_attrs(dev, psize, &paddr, GFP_KERNEL, attrs);
643 if (!cpu_addr) {
644 dev_err(dev, "failed to allocate %zu bytes for pgtable\n",
645 psize);
646 return -ENOMEM;
647 }
648
649 ret = qcom_scm_iommu_secure_ptbl_init(paddr, psize, spare);
650 if (ret) {
651 dev_err(dev, "failed to init iommu pgtable (%d)\n", ret);
652 goto free_mem;
653 }
654
655 allocated = true;
656 return 0;
657
658free_mem:
659 dma_free_attrs(dev, psize, cpu_addr, paddr, attrs);
660 return ret;
661}
662
663static int get_asid(const struct device_node *np)
664{
665 u32 reg;
666
667 /* read the "reg" property directly to get the relative address
668 * of the context bank, and calculate the asid from that:
669 */
670 if (of_property_read_u32_index(np, "reg", 0, &reg))
671 return -ENODEV;
672
673 return reg / 0x1000; /* context banks are 0x1000 apart */
674}
675
676static int qcom_iommu_ctx_probe(struct platform_device *pdev)
677{
678 struct qcom_iommu_ctx *ctx;
679 struct device *dev = &pdev->dev;
680 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev->parent);
681 struct resource *res;
682 int ret, irq;
683
684 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
685 if (!ctx)
686 return -ENOMEM;
687
688 ctx->dev = dev;
689 platform_set_drvdata(pdev, ctx);
690
691 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
692 ctx->base = devm_ioremap_resource(dev, res);
693 if (IS_ERR(ctx->base))
694 return PTR_ERR(ctx->base);
695
696 irq = platform_get_irq(pdev, 0);
697 if (irq < 0) {
698 dev_err(dev, "failed to get irq\n");
699 return -ENODEV;
700 }
701
702 /* clear IRQs before registering fault handler, just in case the
703 * boot-loader left us a surprise:
704 */
705 iommu_writel(ctx, ARM_SMMU_CB_FSR, iommu_readl(ctx, ARM_SMMU_CB_FSR));
706
707 ret = devm_request_irq(dev, irq,
708 qcom_iommu_fault,
709 IRQF_SHARED,
710 "qcom-iommu-fault",
711 ctx);
712 if (ret) {
713 dev_err(dev, "failed to request IRQ %u\n", irq);
714 return ret;
715 }
716
717 ret = get_asid(dev->of_node);
718 if (ret < 0) {
719 dev_err(dev, "missing reg property\n");
720 return ret;
721 }
722
723 ctx->asid = ret;
724
725 dev_dbg(dev, "found asid %u\n", ctx->asid);
726
727 qcom_iommu->ctxs[ctx->asid - 1] = ctx;
728
729 return 0;
730}
731
732static int qcom_iommu_ctx_remove(struct platform_device *pdev)
733{
734 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(pdev->dev.parent);
735 struct qcom_iommu_ctx *ctx = platform_get_drvdata(pdev);
736
737 platform_set_drvdata(pdev, NULL);
738
739 qcom_iommu->ctxs[ctx->asid - 1] = NULL;
740
741 return 0;
742}
743
744static const struct of_device_id ctx_of_match[] = {
745 { .compatible = "qcom,msm-iommu-v1-ns" },
746 { .compatible = "qcom,msm-iommu-v1-sec" },
747 { /* sentinel */ }
748};
749
750static struct platform_driver qcom_iommu_ctx_driver = {
751 .driver = {
752 .name = "qcom-iommu-ctx",
753 .of_match_table = of_match_ptr(ctx_of_match),
754 },
755 .probe = qcom_iommu_ctx_probe,
756 .remove = qcom_iommu_ctx_remove,
757};
758
759static bool qcom_iommu_has_secure_context(struct qcom_iommu_dev *qcom_iommu)
760{
761 struct device_node *child;
762
763 for_each_child_of_node(qcom_iommu->dev->of_node, child)
764 if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec"))
765 return true;
766
767 return false;
768}
769
770static int qcom_iommu_device_probe(struct platform_device *pdev)
771{
772 struct device_node *child;
773 struct qcom_iommu_dev *qcom_iommu;
774 struct device *dev = &pdev->dev;
775 struct resource *res;
776 int ret, sz, max_asid = 0;
777
778 /* find the max asid (which is 1:1 to ctx bank idx), so we know how
779 * many child ctx devices we have:
780 */
781 for_each_child_of_node(dev->of_node, child)
782 max_asid = max(max_asid, get_asid(child));
783
784 sz = sizeof(*qcom_iommu) + (max_asid * sizeof(qcom_iommu->ctxs[0]));
785
786 qcom_iommu = devm_kzalloc(dev, sz, GFP_KERNEL);
787 if (!qcom_iommu)
788 return -ENOMEM;
789 qcom_iommu->num_ctxs = max_asid;
790 qcom_iommu->dev = dev;
791
792 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
793 if (res) {
794 qcom_iommu->local_base = devm_ioremap_resource(dev, res);
795 if (IS_ERR(qcom_iommu->local_base))
796 return PTR_ERR(qcom_iommu->local_base);
797 }
798
799 qcom_iommu->iface_clk = devm_clk_get(dev, "iface");
800 if (IS_ERR(qcom_iommu->iface_clk)) {
801 dev_err(dev, "failed to get iface clock\n");
802 return PTR_ERR(qcom_iommu->iface_clk);
803 }
804
805 qcom_iommu->bus_clk = devm_clk_get(dev, "bus");
806 if (IS_ERR(qcom_iommu->bus_clk)) {
807 dev_err(dev, "failed to get bus clock\n");
808 return PTR_ERR(qcom_iommu->bus_clk);
809 }
810
811 if (of_property_read_u32(dev->of_node, "qcom,iommu-secure-id",
812 &qcom_iommu->sec_id)) {
813 dev_err(dev, "missing qcom,iommu-secure-id property\n");
814 return -ENODEV;
815 }
816
817 if (qcom_iommu_has_secure_context(qcom_iommu)) {
818 ret = qcom_iommu_sec_ptbl_init(dev);
819 if (ret) {
820 dev_err(dev, "cannot init secure pg table(%d)\n", ret);
821 return ret;
822 }
823 }
824
825 platform_set_drvdata(pdev, qcom_iommu);
826
827 pm_runtime_enable(dev);
828
829 /* register context bank devices, which are child nodes: */
830 ret = devm_of_platform_populate(dev);
831 if (ret) {
832 dev_err(dev, "Failed to populate iommu contexts\n");
833 return ret;
834 }
835
836 ret = iommu_device_sysfs_add(&qcom_iommu->iommu, dev, NULL,
837 dev_name(dev));
838 if (ret) {
839 dev_err(dev, "Failed to register iommu in sysfs\n");
840 return ret;
841 }
842
843 iommu_device_set_ops(&qcom_iommu->iommu, &qcom_iommu_ops);
844 iommu_device_set_fwnode(&qcom_iommu->iommu, dev->fwnode);
845
846 ret = iommu_device_register(&qcom_iommu->iommu);
847 if (ret) {
848 dev_err(dev, "Failed to register iommu\n");
849 return ret;
850 }
851
852 bus_set_iommu(&platform_bus_type, &qcom_iommu_ops);
853
854 if (qcom_iommu->local_base) {
855 pm_runtime_get_sync(dev);
856 writel_relaxed(0xffffffff, qcom_iommu->local_base + SMMU_INTR_SEL_NS);
857 pm_runtime_put_sync(dev);
858 }
859
860 return 0;
861}
862
863static int qcom_iommu_device_remove(struct platform_device *pdev)
864{
865 struct qcom_iommu_dev *qcom_iommu = platform_get_drvdata(pdev);
866
867 bus_set_iommu(&platform_bus_type, NULL);
868
869 pm_runtime_force_suspend(&pdev->dev);
870 platform_set_drvdata(pdev, NULL);
871 iommu_device_sysfs_remove(&qcom_iommu->iommu);
872 iommu_device_unregister(&qcom_iommu->iommu);
873
874 return 0;
875}
876
877static int __maybe_unused qcom_iommu_resume(struct device *dev)
878{
879 struct platform_device *pdev = to_platform_device(dev);
880 struct qcom_iommu_dev *qcom_iommu = platform_get_drvdata(pdev);
881
882 return qcom_iommu_enable_clocks(qcom_iommu);
883}
884
885static int __maybe_unused qcom_iommu_suspend(struct device *dev)
886{
887 struct platform_device *pdev = to_platform_device(dev);
888 struct qcom_iommu_dev *qcom_iommu = platform_get_drvdata(pdev);
889
890 qcom_iommu_disable_clocks(qcom_iommu);
891
892 return 0;
893}
894
895static const struct dev_pm_ops qcom_iommu_pm_ops = {
896 SET_RUNTIME_PM_OPS(qcom_iommu_suspend, qcom_iommu_resume, NULL)
897 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
898 pm_runtime_force_resume)
899};
900
901static const struct of_device_id qcom_iommu_of_match[] = {
902 { .compatible = "qcom,msm-iommu-v1" },
903 { /* sentinel */ }
904};
905MODULE_DEVICE_TABLE(of, qcom_iommu_of_match);
906
907static struct platform_driver qcom_iommu_driver = {
908 .driver = {
909 .name = "qcom-iommu",
910 .of_match_table = of_match_ptr(qcom_iommu_of_match),
911 .pm = &qcom_iommu_pm_ops,
912 },
913 .probe = qcom_iommu_device_probe,
914 .remove = qcom_iommu_device_remove,
915};
916
917static int __init qcom_iommu_init(void)
918{
919 int ret;
920
921 ret = platform_driver_register(&qcom_iommu_ctx_driver);
922 if (ret)
923 return ret;
924
925 ret = platform_driver_register(&qcom_iommu_driver);
926 if (ret)
927 platform_driver_unregister(&qcom_iommu_ctx_driver);
928
929 return ret;
930}
931
932static void __exit qcom_iommu_exit(void)
933{
934 platform_driver_unregister(&qcom_iommu_driver);
935 platform_driver_unregister(&qcom_iommu_ctx_driver);
936}
937
938module_init(qcom_iommu_init);
939module_exit(qcom_iommu_exit);
940
941IOMMU_OF_DECLARE(qcom_iommu_dev, "qcom,msm-iommu-v1", NULL);
942
943MODULE_DESCRIPTION("IOMMU API for QCOM IOMMU v1 implementations");
944MODULE_LICENSE("GPL v2");