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192.168.1.100 / T103 / 1f884588077ad3476b9c91cbb0ee9ee0332bbb68 / . / src / kernel / linux / v4.14 / drivers / media / dvb-frontends / stv090x.c
blob: 2695e1eb6d9c4a81807ef71b86b578392e91944a [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +0800[diff] [blame^]1/*
2 STV0900/0903 Multistandard Broadcast Frontend driver
3 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include <linux/init.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/string.h>
26#include <linux/slab.h>
27#include <linux/mutex.h>
28
29#include <linux/dvb/frontend.h>
30#include "dvb_frontend.h"
31
32#include "stv6110x.h" /* for demodulator internal modes */
33
34#include "stv090x_reg.h"
35#include "stv090x.h"
36#include "stv090x_priv.h"
37
38/* Max transfer size done by I2C transfer functions */
39#define MAX_XFER_SIZE 64
40
41static unsigned int verbose;
42module_param(verbose, int, 0644);
43
44/* internal params node */
45struct stv090x_dev {
46 /* pointer for internal params, one for each pair of demods */
47 struct stv090x_internal *internal;
48 struct stv090x_dev *next_dev;
49};
50
51/* first internal params */
52static struct stv090x_dev *stv090x_first_dev;
53
54/* find chip by i2c adapter and i2c address */
55static struct stv090x_dev *find_dev(struct i2c_adapter *i2c_adap,
56 u8 i2c_addr)
57{
58 struct stv090x_dev *temp_dev = stv090x_first_dev;
59
60 /*
61 Search of the last stv0900 chip or
62 find it by i2c adapter and i2c address */
63 while ((temp_dev != NULL) &&
64 ((temp_dev->internal->i2c_adap != i2c_adap) ||
65 (temp_dev->internal->i2c_addr != i2c_addr))) {
66
67 temp_dev = temp_dev->next_dev;
68 }
69
70 return temp_dev;
71}
72
73/* deallocating chip */
74static void remove_dev(struct stv090x_internal *internal)
75{
76 struct stv090x_dev *prev_dev = stv090x_first_dev;
77 struct stv090x_dev *del_dev = find_dev(internal->i2c_adap,
78 internal->i2c_addr);
79
80 if (del_dev != NULL) {
81 if (del_dev == stv090x_first_dev) {
82 stv090x_first_dev = del_dev->next_dev;
83 } else {
84 while (prev_dev->next_dev != del_dev)
85 prev_dev = prev_dev->next_dev;
86
87 prev_dev->next_dev = del_dev->next_dev;
88 }
89
90 kfree(del_dev);
91 }
92}
93
94/* allocating new chip */
95static struct stv090x_dev *append_internal(struct stv090x_internal *internal)
96{
97 struct stv090x_dev *new_dev;
98 struct stv090x_dev *temp_dev;
99
100 new_dev = kmalloc(sizeof(struct stv090x_dev), GFP_KERNEL);
101 if (new_dev != NULL) {
102 new_dev->internal = internal;
103 new_dev->next_dev = NULL;
104
105 /* append to list */
106 if (stv090x_first_dev == NULL) {
107 stv090x_first_dev = new_dev;
108 } else {
109 temp_dev = stv090x_first_dev;
110 while (temp_dev->next_dev != NULL)
111 temp_dev = temp_dev->next_dev;
112
113 temp_dev->next_dev = new_dev;
114 }
115 }
116
117 return new_dev;
118}
119
120
121/* DVBS1 and DSS C/N Lookup table */
122static const struct stv090x_tab stv090x_s1cn_tab[] = {
123 { 0, 8917 }, /* 0.0dB */
124 { 5, 8801 }, /* 0.5dB */
125 { 10, 8667 }, /* 1.0dB */
126 { 15, 8522 }, /* 1.5dB */
127 { 20, 8355 }, /* 2.0dB */
128 { 25, 8175 }, /* 2.5dB */
129 { 30, 7979 }, /* 3.0dB */
130 { 35, 7763 }, /* 3.5dB */
131 { 40, 7530 }, /* 4.0dB */
132 { 45, 7282 }, /* 4.5dB */
133 { 50, 7026 }, /* 5.0dB */
134 { 55, 6781 }, /* 5.5dB */
135 { 60, 6514 }, /* 6.0dB */
136 { 65, 6241 }, /* 6.5dB */
137 { 70, 5965 }, /* 7.0dB */
138 { 75, 5690 }, /* 7.5dB */
139 { 80, 5424 }, /* 8.0dB */
140 { 85, 5161 }, /* 8.5dB */
141 { 90, 4902 }, /* 9.0dB */
142 { 95, 4654 }, /* 9.5dB */
143 { 100, 4417 }, /* 10.0dB */
144 { 105, 4186 }, /* 10.5dB */
145 { 110, 3968 }, /* 11.0dB */
146 { 115, 3757 }, /* 11.5dB */
147 { 120, 3558 }, /* 12.0dB */
148 { 125, 3366 }, /* 12.5dB */
149 { 130, 3185 }, /* 13.0dB */
150 { 135, 3012 }, /* 13.5dB */
151 { 140, 2850 }, /* 14.0dB */
152 { 145, 2698 }, /* 14.5dB */
153 { 150, 2550 }, /* 15.0dB */
154 { 160, 2283 }, /* 16.0dB */
155 { 170, 2042 }, /* 17.0dB */
156 { 180, 1827 }, /* 18.0dB */
157 { 190, 1636 }, /* 19.0dB */
158 { 200, 1466 }, /* 20.0dB */
159 { 210, 1315 }, /* 21.0dB */
160 { 220, 1181 }, /* 22.0dB */
161 { 230, 1064 }, /* 23.0dB */
162 { 240, 960 }, /* 24.0dB */
163 { 250, 869 }, /* 25.0dB */
164 { 260, 792 }, /* 26.0dB */
165 { 270, 724 }, /* 27.0dB */
166 { 280, 665 }, /* 28.0dB */
167 { 290, 616 }, /* 29.0dB */
168 { 300, 573 }, /* 30.0dB */
169 { 310, 537 }, /* 31.0dB */
170 { 320, 507 }, /* 32.0dB */
171 { 330, 483 }, /* 33.0dB */
172 { 400, 398 }, /* 40.0dB */
173 { 450, 381 }, /* 45.0dB */
174 { 500, 377 } /* 50.0dB */
175};
176
177/* DVBS2 C/N Lookup table */
178static const struct stv090x_tab stv090x_s2cn_tab[] = {
179 { -30, 13348 }, /* -3.0dB */
180 { -20, 12640 }, /* -2d.0B */
181 { -10, 11883 }, /* -1.0dB */
182 { 0, 11101 }, /* -0.0dB */
183 { 5, 10718 }, /* 0.5dB */
184 { 10, 10339 }, /* 1.0dB */
185 { 15, 9947 }, /* 1.5dB */
186 { 20, 9552 }, /* 2.0dB */
187 { 25, 9183 }, /* 2.5dB */
188 { 30, 8799 }, /* 3.0dB */
189 { 35, 8422 }, /* 3.5dB */
190 { 40, 8062 }, /* 4.0dB */
191 { 45, 7707 }, /* 4.5dB */
192 { 50, 7353 }, /* 5.0dB */
193 { 55, 7025 }, /* 5.5dB */
194 { 60, 6684 }, /* 6.0dB */
195 { 65, 6331 }, /* 6.5dB */
196 { 70, 6036 }, /* 7.0dB */
197 { 75, 5727 }, /* 7.5dB */
198 { 80, 5437 }, /* 8.0dB */
199 { 85, 5164 }, /* 8.5dB */
200 { 90, 4902 }, /* 9.0dB */
201 { 95, 4653 }, /* 9.5dB */
202 { 100, 4408 }, /* 10.0dB */
203 { 105, 4187 }, /* 10.5dB */
204 { 110, 3961 }, /* 11.0dB */
205 { 115, 3751 }, /* 11.5dB */
206 { 120, 3558 }, /* 12.0dB */
207 { 125, 3368 }, /* 12.5dB */
208 { 130, 3191 }, /* 13.0dB */
209 { 135, 3017 }, /* 13.5dB */
210 { 140, 2862 }, /* 14.0dB */
211 { 145, 2710 }, /* 14.5dB */
212 { 150, 2565 }, /* 15.0dB */
213 { 160, 2300 }, /* 16.0dB */
214 { 170, 2058 }, /* 17.0dB */
215 { 180, 1849 }, /* 18.0dB */
216 { 190, 1663 }, /* 19.0dB */
217 { 200, 1495 }, /* 20.0dB */
218 { 210, 1349 }, /* 21.0dB */
219 { 220, 1222 }, /* 22.0dB */
220 { 230, 1110 }, /* 23.0dB */
221 { 240, 1011 }, /* 24.0dB */
222 { 250, 925 }, /* 25.0dB */
223 { 260, 853 }, /* 26.0dB */
224 { 270, 789 }, /* 27.0dB */
225 { 280, 734 }, /* 28.0dB */
226 { 290, 690 }, /* 29.0dB */
227 { 300, 650 }, /* 30.0dB */
228 { 310, 619 }, /* 31.0dB */
229 { 320, 593 }, /* 32.0dB */
230 { 330, 571 }, /* 33.0dB */
231 { 400, 498 }, /* 40.0dB */
232 { 450, 484 }, /* 45.0dB */
233 { 500, 481 } /* 50.0dB */
234};
235
236/* RF level C/N lookup table */
237static const struct stv090x_tab stv090x_rf_tab[] = {
238 { -5, 0xcaa1 }, /* -5dBm */
239 { -10, 0xc229 }, /* -10dBm */
240 { -15, 0xbb08 }, /* -15dBm */
241 { -20, 0xb4bc }, /* -20dBm */
242 { -25, 0xad5a }, /* -25dBm */
243 { -30, 0xa298 }, /* -30dBm */
244 { -35, 0x98a8 }, /* -35dBm */
245 { -40, 0x8389 }, /* -40dBm */
246 { -45, 0x59be }, /* -45dBm */
247 { -50, 0x3a14 }, /* -50dBm */
248 { -55, 0x2d11 }, /* -55dBm */
249 { -60, 0x210d }, /* -60dBm */
250 { -65, 0xa14f }, /* -65dBm */
251 { -70, 0x07aa } /* -70dBm */
252};
253
254
255static struct stv090x_reg stv0900_initval[] = {
256
257 { STV090x_OUTCFG, 0x00 },
258 { STV090x_MODECFG, 0xff },
259 { STV090x_AGCRF1CFG, 0x11 },
260 { STV090x_AGCRF2CFG, 0x13 },
261 { STV090x_TSGENERAL1X, 0x14 },
262 { STV090x_TSTTNR2, 0x21 },
263 { STV090x_TSTTNR4, 0x21 },
264 { STV090x_P2_DISTXCTL, 0x22 },
265 { STV090x_P2_F22TX, 0xc0 },
266 { STV090x_P2_F22RX, 0xc0 },
267 { STV090x_P2_DISRXCTL, 0x00 },
268 { STV090x_P2_DMDCFGMD, 0xF9 },
269 { STV090x_P2_DEMOD, 0x08 },
270 { STV090x_P2_DMDCFG3, 0xc4 },
271 { STV090x_P2_CARFREQ, 0xed },
272 { STV090x_P2_LDT, 0xd0 },
273 { STV090x_P2_LDT2, 0xb8 },
274 { STV090x_P2_TMGCFG, 0xd2 },
275 { STV090x_P2_TMGTHRISE, 0x20 },
276 { STV090x_P1_TMGCFG, 0xd2 },
277
278 { STV090x_P2_TMGTHFALL, 0x00 },
279 { STV090x_P2_FECSPY, 0x88 },
280 { STV090x_P2_FSPYDATA, 0x3a },
281 { STV090x_P2_FBERCPT4, 0x00 },
282 { STV090x_P2_FSPYBER, 0x10 },
283 { STV090x_P2_ERRCTRL1, 0x35 },
284 { STV090x_P2_ERRCTRL2, 0xc1 },
285 { STV090x_P2_CFRICFG, 0xf8 },
286 { STV090x_P2_NOSCFG, 0x1c },
287 { STV090x_P2_DMDTOM, 0x20 },
288 { STV090x_P2_CORRELMANT, 0x70 },
289 { STV090x_P2_CORRELABS, 0x88 },
290 { STV090x_P2_AGC2O, 0x5b },
291 { STV090x_P2_AGC2REF, 0x38 },
292 { STV090x_P2_CARCFG, 0xe4 },
293 { STV090x_P2_ACLC, 0x1A },
294 { STV090x_P2_BCLC, 0x09 },
295 { STV090x_P2_CARHDR, 0x08 },
296 { STV090x_P2_KREFTMG, 0xc1 },
297 { STV090x_P2_SFRUPRATIO, 0xf0 },
298 { STV090x_P2_SFRLOWRATIO, 0x70 },
299 { STV090x_P2_SFRSTEP, 0x58 },
300 { STV090x_P2_TMGCFG2, 0x01 },
301 { STV090x_P2_CAR2CFG, 0x26 },
302 { STV090x_P2_BCLC2S2Q, 0x86 },
303 { STV090x_P2_BCLC2S28, 0x86 },
304 { STV090x_P2_SMAPCOEF7, 0x77 },
305 { STV090x_P2_SMAPCOEF6, 0x85 },
306 { STV090x_P2_SMAPCOEF5, 0x77 },
307 { STV090x_P2_TSCFGL, 0x20 },
308 { STV090x_P2_DMDCFG2, 0x3b },
309 { STV090x_P2_MODCODLST0, 0xff },
310 { STV090x_P2_MODCODLST1, 0xff },
311 { STV090x_P2_MODCODLST2, 0xff },
312 { STV090x_P2_MODCODLST3, 0xff },
313 { STV090x_P2_MODCODLST4, 0xff },
314 { STV090x_P2_MODCODLST5, 0xff },
315 { STV090x_P2_MODCODLST6, 0xff },
316 { STV090x_P2_MODCODLST7, 0xcc },
317 { STV090x_P2_MODCODLST8, 0xcc },
318 { STV090x_P2_MODCODLST9, 0xcc },
319 { STV090x_P2_MODCODLSTA, 0xcc },
320 { STV090x_P2_MODCODLSTB, 0xcc },
321 { STV090x_P2_MODCODLSTC, 0xcc },
322 { STV090x_P2_MODCODLSTD, 0xcc },
323 { STV090x_P2_MODCODLSTE, 0xcc },
324 { STV090x_P2_MODCODLSTF, 0xcf },
325 { STV090x_P1_DISTXCTL, 0x22 },
326 { STV090x_P1_F22TX, 0xc0 },
327 { STV090x_P1_F22RX, 0xc0 },
328 { STV090x_P1_DISRXCTL, 0x00 },
329 { STV090x_P1_DMDCFGMD, 0xf9 },
330 { STV090x_P1_DEMOD, 0x08 },
331 { STV090x_P1_DMDCFG3, 0xc4 },
332 { STV090x_P1_DMDTOM, 0x20 },
333 { STV090x_P1_CARFREQ, 0xed },
334 { STV090x_P1_LDT, 0xd0 },
335 { STV090x_P1_LDT2, 0xb8 },
336 { STV090x_P1_TMGCFG, 0xd2 },
337 { STV090x_P1_TMGTHRISE, 0x20 },
338 { STV090x_P1_TMGTHFALL, 0x00 },
339 { STV090x_P1_SFRUPRATIO, 0xf0 },
340 { STV090x_P1_SFRLOWRATIO, 0x70 },
341 { STV090x_P1_TSCFGL, 0x20 },
342 { STV090x_P1_FECSPY, 0x88 },
343 { STV090x_P1_FSPYDATA, 0x3a },
344 { STV090x_P1_FBERCPT4, 0x00 },
345 { STV090x_P1_FSPYBER, 0x10 },
346 { STV090x_P1_ERRCTRL1, 0x35 },
347 { STV090x_P1_ERRCTRL2, 0xc1 },
348 { STV090x_P1_CFRICFG, 0xf8 },
349 { STV090x_P1_NOSCFG, 0x1c },
350 { STV090x_P1_CORRELMANT, 0x70 },
351 { STV090x_P1_CORRELABS, 0x88 },
352 { STV090x_P1_AGC2O, 0x5b },
353 { STV090x_P1_AGC2REF, 0x38 },
354 { STV090x_P1_CARCFG, 0xe4 },
355 { STV090x_P1_ACLC, 0x1A },
356 { STV090x_P1_BCLC, 0x09 },
357 { STV090x_P1_CARHDR, 0x08 },
358 { STV090x_P1_KREFTMG, 0xc1 },
359 { STV090x_P1_SFRSTEP, 0x58 },
360 { STV090x_P1_TMGCFG2, 0x01 },
361 { STV090x_P1_CAR2CFG, 0x26 },
362 { STV090x_P1_BCLC2S2Q, 0x86 },
363 { STV090x_P1_BCLC2S28, 0x86 },
364 { STV090x_P1_SMAPCOEF7, 0x77 },
365 { STV090x_P1_SMAPCOEF6, 0x85 },
366 { STV090x_P1_SMAPCOEF5, 0x77 },
367 { STV090x_P1_DMDCFG2, 0x3b },
368 { STV090x_P1_MODCODLST0, 0xff },
369 { STV090x_P1_MODCODLST1, 0xff },
370 { STV090x_P1_MODCODLST2, 0xff },
371 { STV090x_P1_MODCODLST3, 0xff },
372 { STV090x_P1_MODCODLST4, 0xff },
373 { STV090x_P1_MODCODLST5, 0xff },
374 { STV090x_P1_MODCODLST6, 0xff },
375 { STV090x_P1_MODCODLST7, 0xcc },
376 { STV090x_P1_MODCODLST8, 0xcc },
377 { STV090x_P1_MODCODLST9, 0xcc },
378 { STV090x_P1_MODCODLSTA, 0xcc },
379 { STV090x_P1_MODCODLSTB, 0xcc },
380 { STV090x_P1_MODCODLSTC, 0xcc },
381 { STV090x_P1_MODCODLSTD, 0xcc },
382 { STV090x_P1_MODCODLSTE, 0xcc },
383 { STV090x_P1_MODCODLSTF, 0xcf },
384 { STV090x_GENCFG, 0x1d },
385 { STV090x_NBITER_NF4, 0x37 },
386 { STV090x_NBITER_NF5, 0x29 },
387 { STV090x_NBITER_NF6, 0x37 },
388 { STV090x_NBITER_NF7, 0x33 },
389 { STV090x_NBITER_NF8, 0x31 },
390 { STV090x_NBITER_NF9, 0x2f },
391 { STV090x_NBITER_NF10, 0x39 },
392 { STV090x_NBITER_NF11, 0x3a },
393 { STV090x_NBITER_NF12, 0x29 },
394 { STV090x_NBITER_NF13, 0x37 },
395 { STV090x_NBITER_NF14, 0x33 },
396 { STV090x_NBITER_NF15, 0x2f },
397 { STV090x_NBITER_NF16, 0x39 },
398 { STV090x_NBITER_NF17, 0x3a },
399 { STV090x_NBITERNOERR, 0x04 },
400 { STV090x_GAINLLR_NF4, 0x0C },
401 { STV090x_GAINLLR_NF5, 0x0F },
402 { STV090x_GAINLLR_NF6, 0x11 },
403 { STV090x_GAINLLR_NF7, 0x14 },
404 { STV090x_GAINLLR_NF8, 0x17 },
405 { STV090x_GAINLLR_NF9, 0x19 },
406 { STV090x_GAINLLR_NF10, 0x20 },
407 { STV090x_GAINLLR_NF11, 0x21 },
408 { STV090x_GAINLLR_NF12, 0x0D },
409 { STV090x_GAINLLR_NF13, 0x0F },
410 { STV090x_GAINLLR_NF14, 0x13 },
411 { STV090x_GAINLLR_NF15, 0x1A },
412 { STV090x_GAINLLR_NF16, 0x1F },
413 { STV090x_GAINLLR_NF17, 0x21 },
414 { STV090x_RCCFGH, 0x20 },
415 { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
416 { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
417 { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
418 { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
419};
420
421static struct stv090x_reg stv0903_initval[] = {
422 { STV090x_OUTCFG, 0x00 },
423 { STV090x_AGCRF1CFG, 0x11 },
424 { STV090x_STOPCLK1, 0x48 },
425 { STV090x_STOPCLK2, 0x14 },
426 { STV090x_TSTTNR1, 0x27 },
427 { STV090x_TSTTNR2, 0x21 },
428 { STV090x_P1_DISTXCTL, 0x22 },
429 { STV090x_P1_F22TX, 0xc0 },
430 { STV090x_P1_F22RX, 0xc0 },
431 { STV090x_P1_DISRXCTL, 0x00 },
432 { STV090x_P1_DMDCFGMD, 0xF9 },
433 { STV090x_P1_DEMOD, 0x08 },
434 { STV090x_P1_DMDCFG3, 0xc4 },
435 { STV090x_P1_CARFREQ, 0xed },
436 { STV090x_P1_TNRCFG2, 0x82 },
437 { STV090x_P1_LDT, 0xd0 },
438 { STV090x_P1_LDT2, 0xb8 },
439 { STV090x_P1_TMGCFG, 0xd2 },
440 { STV090x_P1_TMGTHRISE, 0x20 },
441 { STV090x_P1_TMGTHFALL, 0x00 },
442 { STV090x_P1_SFRUPRATIO, 0xf0 },
443 { STV090x_P1_SFRLOWRATIO, 0x70 },
444 { STV090x_P1_TSCFGL, 0x20 },
445 { STV090x_P1_FECSPY, 0x88 },
446 { STV090x_P1_FSPYDATA, 0x3a },
447 { STV090x_P1_FBERCPT4, 0x00 },
448 { STV090x_P1_FSPYBER, 0x10 },
449 { STV090x_P1_ERRCTRL1, 0x35 },
450 { STV090x_P1_ERRCTRL2, 0xc1 },
451 { STV090x_P1_CFRICFG, 0xf8 },
452 { STV090x_P1_NOSCFG, 0x1c },
453 { STV090x_P1_DMDTOM, 0x20 },
454 { STV090x_P1_CORRELMANT, 0x70 },
455 { STV090x_P1_CORRELABS, 0x88 },
456 { STV090x_P1_AGC2O, 0x5b },
457 { STV090x_P1_AGC2REF, 0x38 },
458 { STV090x_P1_CARCFG, 0xe4 },
459 { STV090x_P1_ACLC, 0x1A },
460 { STV090x_P1_BCLC, 0x09 },
461 { STV090x_P1_CARHDR, 0x08 },
462 { STV090x_P1_KREFTMG, 0xc1 },
463 { STV090x_P1_SFRSTEP, 0x58 },
464 { STV090x_P1_TMGCFG2, 0x01 },
465 { STV090x_P1_CAR2CFG, 0x26 },
466 { STV090x_P1_BCLC2S2Q, 0x86 },
467 { STV090x_P1_BCLC2S28, 0x86 },
468 { STV090x_P1_SMAPCOEF7, 0x77 },
469 { STV090x_P1_SMAPCOEF6, 0x85 },
470 { STV090x_P1_SMAPCOEF5, 0x77 },
471 { STV090x_P1_DMDCFG2, 0x3b },
472 { STV090x_P1_MODCODLST0, 0xff },
473 { STV090x_P1_MODCODLST1, 0xff },
474 { STV090x_P1_MODCODLST2, 0xff },
475 { STV090x_P1_MODCODLST3, 0xff },
476 { STV090x_P1_MODCODLST4, 0xff },
477 { STV090x_P1_MODCODLST5, 0xff },
478 { STV090x_P1_MODCODLST6, 0xff },
479 { STV090x_P1_MODCODLST7, 0xcc },
480 { STV090x_P1_MODCODLST8, 0xcc },
481 { STV090x_P1_MODCODLST9, 0xcc },
482 { STV090x_P1_MODCODLSTA, 0xcc },
483 { STV090x_P1_MODCODLSTB, 0xcc },
484 { STV090x_P1_MODCODLSTC, 0xcc },
485 { STV090x_P1_MODCODLSTD, 0xcc },
486 { STV090x_P1_MODCODLSTE, 0xcc },
487 { STV090x_P1_MODCODLSTF, 0xcf },
488 { STV090x_GENCFG, 0x1c },
489 { STV090x_NBITER_NF4, 0x37 },
490 { STV090x_NBITER_NF5, 0x29 },
491 { STV090x_NBITER_NF6, 0x37 },
492 { STV090x_NBITER_NF7, 0x33 },
493 { STV090x_NBITER_NF8, 0x31 },
494 { STV090x_NBITER_NF9, 0x2f },
495 { STV090x_NBITER_NF10, 0x39 },
496 { STV090x_NBITER_NF11, 0x3a },
497 { STV090x_NBITER_NF12, 0x29 },
498 { STV090x_NBITER_NF13, 0x37 },
499 { STV090x_NBITER_NF14, 0x33 },
500 { STV090x_NBITER_NF15, 0x2f },
501 { STV090x_NBITER_NF16, 0x39 },
502 { STV090x_NBITER_NF17, 0x3a },
503 { STV090x_NBITERNOERR, 0x04 },
504 { STV090x_GAINLLR_NF4, 0x0C },
505 { STV090x_GAINLLR_NF5, 0x0F },
506 { STV090x_GAINLLR_NF6, 0x11 },
507 { STV090x_GAINLLR_NF7, 0x14 },
508 { STV090x_GAINLLR_NF8, 0x17 },
509 { STV090x_GAINLLR_NF9, 0x19 },
510 { STV090x_GAINLLR_NF10, 0x20 },
511 { STV090x_GAINLLR_NF11, 0x21 },
512 { STV090x_GAINLLR_NF12, 0x0D },
513 { STV090x_GAINLLR_NF13, 0x0F },
514 { STV090x_GAINLLR_NF14, 0x13 },
515 { STV090x_GAINLLR_NF15, 0x1A },
516 { STV090x_GAINLLR_NF16, 0x1F },
517 { STV090x_GAINLLR_NF17, 0x21 },
518 { STV090x_RCCFGH, 0x20 },
519 { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
520 { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
521};
522
523static struct stv090x_reg stv0900_cut20_val[] = {
524
525 { STV090x_P2_DMDCFG3, 0xe8 },
526 { STV090x_P2_DMDCFG4, 0x10 },
527 { STV090x_P2_CARFREQ, 0x38 },
528 { STV090x_P2_CARHDR, 0x20 },
529 { STV090x_P2_KREFTMG, 0x5a },
530 { STV090x_P2_SMAPCOEF7, 0x06 },
531 { STV090x_P2_SMAPCOEF6, 0x00 },
532 { STV090x_P2_SMAPCOEF5, 0x04 },
533 { STV090x_P2_NOSCFG, 0x0c },
534 { STV090x_P1_DMDCFG3, 0xe8 },
535 { STV090x_P1_DMDCFG4, 0x10 },
536 { STV090x_P1_CARFREQ, 0x38 },
537 { STV090x_P1_CARHDR, 0x20 },
538 { STV090x_P1_KREFTMG, 0x5a },
539 { STV090x_P1_SMAPCOEF7, 0x06 },
540 { STV090x_P1_SMAPCOEF6, 0x00 },
541 { STV090x_P1_SMAPCOEF5, 0x04 },
542 { STV090x_P1_NOSCFG, 0x0c },
543 { STV090x_GAINLLR_NF4, 0x21 },
544 { STV090x_GAINLLR_NF5, 0x21 },
545 { STV090x_GAINLLR_NF6, 0x20 },
546 { STV090x_GAINLLR_NF7, 0x1F },
547 { STV090x_GAINLLR_NF8, 0x1E },
548 { STV090x_GAINLLR_NF9, 0x1E },
549 { STV090x_GAINLLR_NF10, 0x1D },
550 { STV090x_GAINLLR_NF11, 0x1B },
551 { STV090x_GAINLLR_NF12, 0x20 },
552 { STV090x_GAINLLR_NF13, 0x20 },
553 { STV090x_GAINLLR_NF14, 0x20 },
554 { STV090x_GAINLLR_NF15, 0x20 },
555 { STV090x_GAINLLR_NF16, 0x20 },
556 { STV090x_GAINLLR_NF17, 0x21 },
557};
558
559static struct stv090x_reg stv0903_cut20_val[] = {
560 { STV090x_P1_DMDCFG3, 0xe8 },
561 { STV090x_P1_DMDCFG4, 0x10 },
562 { STV090x_P1_CARFREQ, 0x38 },
563 { STV090x_P1_CARHDR, 0x20 },
564 { STV090x_P1_KREFTMG, 0x5a },
565 { STV090x_P1_SMAPCOEF7, 0x06 },
566 { STV090x_P1_SMAPCOEF6, 0x00 },
567 { STV090x_P1_SMAPCOEF5, 0x04 },
568 { STV090x_P1_NOSCFG, 0x0c },
569 { STV090x_GAINLLR_NF4, 0x21 },
570 { STV090x_GAINLLR_NF5, 0x21 },
571 { STV090x_GAINLLR_NF6, 0x20 },
572 { STV090x_GAINLLR_NF7, 0x1F },
573 { STV090x_GAINLLR_NF8, 0x1E },
574 { STV090x_GAINLLR_NF9, 0x1E },
575 { STV090x_GAINLLR_NF10, 0x1D },
576 { STV090x_GAINLLR_NF11, 0x1B },
577 { STV090x_GAINLLR_NF12, 0x20 },
578 { STV090x_GAINLLR_NF13, 0x20 },
579 { STV090x_GAINLLR_NF14, 0x20 },
580 { STV090x_GAINLLR_NF15, 0x20 },
581 { STV090x_GAINLLR_NF16, 0x20 },
582 { STV090x_GAINLLR_NF17, 0x21 }
583};
584
585/* Cut 2.0 Long Frame Tracking CR loop */
586static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
587 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
588 { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
589 { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
590 { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
591 { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
592 { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
593 { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
594 { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
595 { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
596 { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
597 { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
598 { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
599 { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
600 { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
601 { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
602};
603
604/* Cut 3.0 Long Frame Tracking CR loop */
605static struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = {
606 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
607 { STV090x_QPSK_12, 0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b },
608 { STV090x_QPSK_35, 0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
609 { STV090x_QPSK_23, 0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
610 { STV090x_QPSK_34, 0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
611 { STV090x_QPSK_45, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
612 { STV090x_QPSK_56, 0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
613 { STV090x_QPSK_89, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
614 { STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
615 { STV090x_8PSK_35, 0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 },
616 { STV090x_8PSK_23, 0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a },
617 { STV090x_8PSK_34, 0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a },
618 { STV090x_8PSK_56, 0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b },
619 { STV090x_8PSK_89, 0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b },
620 { STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b }
621};
622
623/* Cut 2.0 Long Frame Tracking CR Loop */
624static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
625 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
626 { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
627 { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
628 { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
629 { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
630 { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
631 { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
632 { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
633 { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
634 { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
635 { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
636 { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
637};
638
639/* Cut 3.0 Long Frame Tracking CR Loop */
640static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = {
641 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
642 { STV090x_16APSK_23, 0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a },
643 { STV090x_16APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a },
644 { STV090x_16APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
645 { STV090x_16APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
646 { STV090x_16APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
647 { STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
648 { STV090x_32APSK_34, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
649 { STV090x_32APSK_45, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
650 { STV090x_32APSK_56, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
651 { STV090x_32APSK_89, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
652 { STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }
653};
654
655static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
656 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
657 { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
658 { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
659 { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
660};
661
662static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = {
663 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
664 { STV090x_QPSK_14, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b },
665 { STV090x_QPSK_13, 0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b },
666 { STV090x_QPSK_25, 0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b }
667};
668
669/* Cut 2.0 Short Frame Tracking CR Loop */
670static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = {
671 /* MODCOD 2M 5M 10M 20M 30M */
672 { STV090x_QPSK, 0x2f, 0x2e, 0x0e, 0x0e, 0x3d },
673 { STV090x_8PSK, 0x3e, 0x0e, 0x2d, 0x0d, 0x3c },
674 { STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d },
675 { STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }
676};
677
678/* Cut 3.0 Short Frame Tracking CR Loop */
679static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = {
680 /* MODCOD 2M 5M 10M 20M 30M */
681 { STV090x_QPSK, 0x2C, 0x2B, 0x0B, 0x0B, 0x3A },
682 { STV090x_8PSK, 0x3B, 0x0B, 0x2A, 0x0A, 0x39 },
683 { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A },
684 { STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }
685};
686
687static inline s32 comp2(s32 __x, s32 __width)
688{
689 if (__width == 32)
690 return __x;
691 else
692 return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
693}
694
695static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
696{
697 const struct stv090x_config *config = state->config;
698 int ret;
699
700 u8 b0[] = { reg >> 8, reg & 0xff };
701 u8 buf;
702
703 struct i2c_msg msg[] = {
704 { .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
705 { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
706 };
707
708 ret = i2c_transfer(state->i2c, msg, 2);
709 if (ret != 2) {
710 if (ret != -ERESTARTSYS)
711 dprintk(FE_ERROR, 1,
712 "Read error, Reg=[0x%02x], Status=%d",
713 reg, ret);
714
715 return ret < 0 ? ret : -EREMOTEIO;
716 }
717 if (unlikely(*state->verbose >= FE_DEBUGREG))
718 dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
719 reg, buf);
720
721 return (unsigned int) buf;
722}
723
724static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
725{
726 const struct stv090x_config *config = state->config;
727 int ret;
728 u8 buf[MAX_XFER_SIZE];
729 struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
730
731 if (2 + count > sizeof(buf)) {
732 printk(KERN_WARNING
733 "%s: i2c wr reg=%04x: len=%d is too big!\n",
734 KBUILD_MODNAME, reg, count);
735 return -EINVAL;
736 }
737
738 buf[0] = reg >> 8;
739 buf[1] = reg & 0xff;
740 memcpy(&buf[2], data, count);
741
742 dprintk(FE_DEBUGREG, 1, "%s [0x%04x]: %*ph",
743 __func__, reg, count, data);
744
745 ret = i2c_transfer(state->i2c, &i2c_msg, 1);
746 if (ret != 1) {
747 if (ret != -ERESTARTSYS)
748 dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
749 reg, data[0], count, ret);
750 return ret < 0 ? ret : -EREMOTEIO;
751 }
752
753 return 0;
754}
755
756static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
757{
758 u8 tmp = data; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
759
760 return stv090x_write_regs(state, reg, &tmp, 1);
761}
762
763static int stv090x_i2c_gate_ctrl(struct stv090x_state *state, int enable)
764{
765 u32 reg;
766
767 /*
768 * NOTE! A lock is used as a FSM to control the state in which
769 * access is serialized between two tuners on the same demod.
770 * This has nothing to do with a lock to protect a critical section
771 * which may in some other cases be confused with protecting I/O
772 * access to the demodulator gate.
773 * In case of any error, the lock is unlocked and exit within the
774 * relevant operations themselves.
775 */
776 if (enable) {
777 if (state->config->tuner_i2c_lock)
778 state->config->tuner_i2c_lock(&state->frontend, 1);
779 else
780 mutex_lock(&state->internal->tuner_lock);
781 }
782
783 reg = STV090x_READ_DEMOD(state, I2CRPT);
784 if (enable) {
785 dprintk(FE_DEBUG, 1, "Enable Gate");
786 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
787 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
788 goto err;
789
790 } else {
791 dprintk(FE_DEBUG, 1, "Disable Gate");
792 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
793 if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
794 goto err;
795 }
796
797 if (!enable) {
798 if (state->config->tuner_i2c_lock)
799 state->config->tuner_i2c_lock(&state->frontend, 0);
800 else
801 mutex_unlock(&state->internal->tuner_lock);
802 }
803
804 return 0;
805err:
806 dprintk(FE_ERROR, 1, "I/O error");
807 if (state->config->tuner_i2c_lock)
808 state->config->tuner_i2c_lock(&state->frontend, 0);
809 else
810 mutex_unlock(&state->internal->tuner_lock);
811 return -1;
812}
813
814static void stv090x_get_lock_tmg(struct stv090x_state *state)
815{
816 switch (state->algo) {
817 case STV090x_BLIND_SEARCH:
818 dprintk(FE_DEBUG, 1, "Blind Search");
819 if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
820 state->DemodTimeout = 1500;
821 state->FecTimeout = 400;
822 } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
823 state->DemodTimeout = 1000;
824 state->FecTimeout = 300;
825 } else { /*SR >20Msps*/
826 state->DemodTimeout = 700;
827 state->FecTimeout = 100;
828 }
829 break;
830
831 case STV090x_COLD_SEARCH:
832 case STV090x_WARM_SEARCH:
833 default:
834 dprintk(FE_DEBUG, 1, "Normal Search");
835 if (state->srate <= 1000000) { /*SR <=1Msps*/
836 state->DemodTimeout = 4500;
837 state->FecTimeout = 1700;
838 } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
839 state->DemodTimeout = 2500;
840 state->FecTimeout = 1100;
841 } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
842 state->DemodTimeout = 1000;
843 state->FecTimeout = 550;
844 } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
845 state->DemodTimeout = 700;
846 state->FecTimeout = 250;
847 } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
848 state->DemodTimeout = 400;
849 state->FecTimeout = 130;
850 } else { /*SR >20Msps*/
851 state->DemodTimeout = 300;
852 state->FecTimeout = 100;
853 }
854 break;
855 }
856
857 if (state->algo == STV090x_WARM_SEARCH)
858 state->DemodTimeout /= 2;
859}
860
861static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
862{
863 u32 sym;
864
865 if (srate > 60000000) {
866 sym = (srate << 4); /* SR * 2^16 / master_clk */
867 sym /= (state->internal->mclk >> 12);
868 } else if (srate > 6000000) {
869 sym = (srate << 6);
870 sym /= (state->internal->mclk >> 10);
871 } else {
872 sym = (srate << 9);
873 sym /= (state->internal->mclk >> 7);
874 }
875
876 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */
877 goto err;
878 if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
879 goto err;
880
881 return 0;
882err:
883 dprintk(FE_ERROR, 1, "I/O error");
884 return -1;
885}
886
887static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
888{
889 u32 sym;
890
891 srate = 105 * (srate / 100);
892 if (srate > 60000000) {
893 sym = (srate << 4); /* SR * 2^16 / master_clk */
894 sym /= (state->internal->mclk >> 12);
895 } else if (srate > 6000000) {
896 sym = (srate << 6);
897 sym /= (state->internal->mclk >> 10);
898 } else {
899 sym = (srate << 9);
900 sym /= (state->internal->mclk >> 7);
901 }
902
903 if (sym < 0x7fff) {
904 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
905 goto err;
906 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
907 goto err;
908 } else {
909 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */
910 goto err;
911 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */
912 goto err;
913 }
914
915 return 0;
916err:
917 dprintk(FE_ERROR, 1, "I/O error");
918 return -1;
919}
920
921static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
922{
923 u32 sym;
924
925 srate = 95 * (srate / 100);
926 if (srate > 60000000) {
927 sym = (srate << 4); /* SR * 2^16 / master_clk */
928 sym /= (state->internal->mclk >> 12);
929 } else if (srate > 6000000) {
930 sym = (srate << 6);
931 sym /= (state->internal->mclk >> 10);
932 } else {
933 sym = (srate << 9);
934 sym /= (state->internal->mclk >> 7);
935 }
936
937 if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */
938 goto err;
939 if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
940 goto err;
941 return 0;
942err:
943 dprintk(FE_ERROR, 1, "I/O error");
944 return -1;
945}
946
947static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff)
948{
949 u32 ro;
950
951 switch (rolloff) {
952 case STV090x_RO_20:
953 ro = 20;
954 break;
955 case STV090x_RO_25:
956 ro = 25;
957 break;
958 case STV090x_RO_35:
959 default:
960 ro = 35;
961 break;
962 }
963
964 return srate + (srate * ro) / 100;
965}
966
967static int stv090x_set_vit_thacq(struct stv090x_state *state)
968{
969 if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
970 goto err;
971 if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
972 goto err;
973 if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
974 goto err;
975 if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
976 goto err;
977 if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
978 goto err;
979 if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
980 goto err;
981 return 0;
982err:
983 dprintk(FE_ERROR, 1, "I/O error");
984 return -1;
985}
986
987static int stv090x_set_vit_thtracq(struct stv090x_state *state)
988{
989 if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
990 goto err;
991 if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
992 goto err;
993 if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
994 goto err;
995 if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
996 goto err;
997 if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
998 goto err;
999 if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
1000 goto err;
1001 return 0;
1002err:
1003 dprintk(FE_ERROR, 1, "I/O error");
1004 return -1;
1005}
1006
1007static int stv090x_set_viterbi(struct stv090x_state *state)
1008{
1009 switch (state->search_mode) {
1010 case STV090x_SEARCH_AUTO:
1011 if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
1012 goto err;
1013 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
1014 goto err;
1015 break;
1016 case STV090x_SEARCH_DVBS1:
1017 if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
1018 goto err;
1019 switch (state->fec) {
1020 case STV090x_PR12:
1021 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
1022 goto err;
1023 break;
1024
1025 case STV090x_PR23:
1026 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
1027 goto err;
1028 break;
1029
1030 case STV090x_PR34:
1031 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
1032 goto err;
1033 break;
1034
1035 case STV090x_PR56:
1036 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
1037 goto err;
1038 break;
1039
1040 case STV090x_PR78:
1041 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
1042 goto err;
1043 break;
1044
1045 default:
1046 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
1047 goto err;
1048 break;
1049 }
1050 break;
1051 case STV090x_SEARCH_DSS:
1052 if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
1053 goto err;
1054 switch (state->fec) {
1055 case STV090x_PR12:
1056 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
1057 goto err;
1058 break;
1059
1060 case STV090x_PR23:
1061 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
1062 goto err;
1063 break;
1064
1065 case STV090x_PR67:
1066 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
1067 goto err;
1068 break;
1069
1070 default:
1071 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
1072 goto err;
1073 break;
1074 }
1075 break;
1076 default:
1077 break;
1078 }
1079 return 0;
1080err:
1081 dprintk(FE_ERROR, 1, "I/O error");
1082 return -1;
1083}
1084
1085static int stv090x_stop_modcod(struct stv090x_state *state)
1086{
1087 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1088 goto err;
1089 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
1090 goto err;
1091 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
1092 goto err;
1093 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
1094 goto err;
1095 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
1096 goto err;
1097 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
1098 goto err;
1099 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
1100 goto err;
1101 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
1102 goto err;
1103 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
1104 goto err;
1105 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
1106 goto err;
1107 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
1108 goto err;
1109 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
1110 goto err;
1111 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
1112 goto err;
1113 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
1114 goto err;
1115 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
1116 goto err;
1117 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
1118 goto err;
1119 return 0;
1120err:
1121 dprintk(FE_ERROR, 1, "I/O error");
1122 return -1;
1123}
1124
1125static int stv090x_activate_modcod(struct stv090x_state *state)
1126{
1127 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1128 goto err;
1129 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
1130 goto err;
1131 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
1132 goto err;
1133 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
1134 goto err;
1135 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
1136 goto err;
1137 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
1138 goto err;
1139 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
1140 goto err;
1141 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
1142 goto err;
1143 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
1144 goto err;
1145 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
1146 goto err;
1147 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
1148 goto err;
1149 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
1150 goto err;
1151 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
1152 goto err;
1153 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
1154 goto err;
1155 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
1156 goto err;
1157 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
1158 goto err;
1159
1160 return 0;
1161err:
1162 dprintk(FE_ERROR, 1, "I/O error");
1163 return -1;
1164}
1165
1166static int stv090x_activate_modcod_single(struct stv090x_state *state)
1167{
1168
1169 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1170 goto err;
1171 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0)
1172 goto err;
1173 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0)
1174 goto err;
1175 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0)
1176 goto err;
1177 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0)
1178 goto err;
1179 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0)
1180 goto err;
1181 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0)
1182 goto err;
1183 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0)
1184 goto err;
1185 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0)
1186 goto err;
1187 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0)
1188 goto err;
1189 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0)
1190 goto err;
1191 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0)
1192 goto err;
1193 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0)
1194 goto err;
1195 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0)
1196 goto err;
1197 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0)
1198 goto err;
1199 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0)
1200 goto err;
1201
1202 return 0;
1203
1204err:
1205 dprintk(FE_ERROR, 1, "I/O error");
1206 return -1;
1207}
1208
1209static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
1210{
1211 u32 reg;
1212
1213 switch (state->demod) {
1214 case STV090x_DEMODULATOR_0:
1215 mutex_lock(&state->internal->demod_lock);
1216 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1217 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
1218 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1219 goto err;
1220 mutex_unlock(&state->internal->demod_lock);
1221 break;
1222
1223 case STV090x_DEMODULATOR_1:
1224 mutex_lock(&state->internal->demod_lock);
1225 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1226 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
1227 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1228 goto err;
1229 mutex_unlock(&state->internal->demod_lock);
1230 break;
1231
1232 default:
1233 dprintk(FE_ERROR, 1, "Wrong demodulator!");
1234 break;
1235 }
1236 return 0;
1237err:
1238 mutex_unlock(&state->internal->demod_lock);
1239 dprintk(FE_ERROR, 1, "I/O error");
1240 return -1;
1241}
1242
1243static int stv090x_dvbs_track_crl(struct stv090x_state *state)
1244{
1245 if (state->internal->dev_ver >= 0x30) {
1246 /* Set ACLC BCLC optimised value vs SR */
1247 if (state->srate >= 15000000) {
1248 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0)
1249 goto err;
1250 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0)
1251 goto err;
1252 } else if ((state->srate >= 7000000) && (15000000 > state->srate)) {
1253 if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0)
1254 goto err;
1255 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0)
1256 goto err;
1257 } else if (state->srate < 7000000) {
1258 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0)
1259 goto err;
1260 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0)
1261 goto err;
1262 }
1263
1264 } else {
1265 /* Cut 2.0 */
1266 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
1267 goto err;
1268 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1269 goto err;
1270 }
1271 return 0;
1272err:
1273 dprintk(FE_ERROR, 1, "I/O error");
1274 return -1;
1275}
1276
1277static int stv090x_delivery_search(struct stv090x_state *state)
1278{
1279 u32 reg;
1280
1281 switch (state->search_mode) {
1282 case STV090x_SEARCH_DVBS1:
1283 case STV090x_SEARCH_DSS:
1284 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1285 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1286 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1287 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1288 goto err;
1289
1290 /* Activate Viterbi decoder in legacy search,
1291 * do not use FRESVIT1, might impact VITERBI2
1292 */
1293 if (stv090x_vitclk_ctl(state, 0) < 0)
1294 goto err;
1295
1296 if (stv090x_dvbs_track_crl(state) < 0)
1297 goto err;
1298
1299 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
1300 goto err;
1301
1302 if (stv090x_set_vit_thacq(state) < 0)
1303 goto err;
1304 if (stv090x_set_viterbi(state) < 0)
1305 goto err;
1306 break;
1307
1308 case STV090x_SEARCH_DVBS2:
1309 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1310 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1311 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1312 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1313 goto err;
1314 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1315 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1316 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1317 goto err;
1318
1319 if (stv090x_vitclk_ctl(state, 1) < 0)
1320 goto err;
1321
1322 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
1323 goto err;
1324 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1325 goto err;
1326
1327 if (state->internal->dev_ver <= 0x20) {
1328 /* enable S2 carrier loop */
1329 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1330 goto err;
1331 } else {
1332 /* > Cut 3: Stop carrier 3 */
1333 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
1334 goto err;
1335 }
1336
1337 if (state->demod_mode != STV090x_SINGLE) {
1338 /* Cut 2: enable link during search */
1339 if (stv090x_activate_modcod(state) < 0)
1340 goto err;
1341 } else {
1342 /* Single demodulator
1343 * Authorize SHORT and LONG frames,
1344 * QPSK, 8PSK, 16APSK and 32APSK
1345 */
1346 if (stv090x_activate_modcod_single(state) < 0)
1347 goto err;
1348 }
1349
1350 if (stv090x_set_vit_thtracq(state) < 0)
1351 goto err;
1352 break;
1353
1354 case STV090x_SEARCH_AUTO:
1355 default:
1356 /* enable DVB-S2 and DVB-S2 in Auto MODE */
1357 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1358 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1359 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1360 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1361 goto err;
1362 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1363 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1364 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1365 goto err;
1366
1367 if (stv090x_vitclk_ctl(state, 0) < 0)
1368 goto err;
1369
1370 if (stv090x_dvbs_track_crl(state) < 0)
1371 goto err;
1372
1373 if (state->internal->dev_ver <= 0x20) {
1374 /* enable S2 carrier loop */
1375 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1376 goto err;
1377 } else {
1378 /* > Cut 3: Stop carrier 3 */
1379 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
1380 goto err;
1381 }
1382
1383 if (state->demod_mode != STV090x_SINGLE) {
1384 /* Cut 2: enable link during search */
1385 if (stv090x_activate_modcod(state) < 0)
1386 goto err;
1387 } else {
1388 /* Single demodulator
1389 * Authorize SHORT and LONG frames,
1390 * QPSK, 8PSK, 16APSK and 32APSK
1391 */
1392 if (stv090x_activate_modcod_single(state) < 0)
1393 goto err;
1394 }
1395
1396 if (stv090x_set_vit_thacq(state) < 0)
1397 goto err;
1398
1399 if (stv090x_set_viterbi(state) < 0)
1400 goto err;
1401 break;
1402 }
1403 return 0;
1404err:
1405 dprintk(FE_ERROR, 1, "I/O error");
1406 return -1;
1407}
1408
1409static int stv090x_start_search(struct stv090x_state *state)
1410{
1411 u32 reg, freq_abs;
1412 s16 freq;
1413
1414 /* Reset demodulator */
1415 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1416 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
1417 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1418 goto err;
1419
1420 if (state->internal->dev_ver <= 0x20) {
1421 if (state->srate <= 5000000) {
1422 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
1423 goto err;
1424 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
1425 goto err;
1426 if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0)
1427 goto err;
1428 if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
1429 goto err;
1430 if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
1431 goto err;
1432
1433 /*enlarge the timing bandwidth for Low SR*/
1434 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
1435 goto err;
1436 } else {
1437 /* If the symbol rate is >5 Msps
1438 Set The carrier search up and low to auto mode */
1439 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1440 goto err;
1441 /*reduce the timing bandwidth for high SR*/
1442 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1443 goto err;
1444 }
1445 } else {
1446 /* >= Cut 3 */
1447 if (state->srate <= 5000000) {
1448 /* enlarge the timing bandwidth for Low SR */
1449 STV090x_WRITE_DEMOD(state, RTCS2, 0x68);
1450 } else {
1451 /* reduce timing bandwidth for high SR */
1452 STV090x_WRITE_DEMOD(state, RTCS2, 0x44);
1453 }
1454
1455 /* Set CFR min and max to manual mode */
1456 STV090x_WRITE_DEMOD(state, CARCFG, 0x46);
1457
1458 if (state->algo == STV090x_WARM_SEARCH) {
1459 /* WARM Start
1460 * CFR min = -1MHz,
1461 * CFR max = +1MHz
1462 */
1463 freq_abs = 1000 << 16;
1464 freq_abs /= (state->internal->mclk / 1000);
1465 freq = (s16) freq_abs;
1466 } else {
1467 /* COLD Start
1468 * CFR min =- (SearchRange / 2 + 600KHz)
1469 * CFR max = +(SearchRange / 2 + 600KHz)
1470 * (600KHz for the tuner step size)
1471 */
1472 freq_abs = (state->search_range / 2000) + 600;
1473 freq_abs = freq_abs << 16;
1474 freq_abs /= (state->internal->mclk / 1000);
1475 freq = (s16) freq_abs;
1476 }
1477
1478 if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0)
1479 goto err;
1480 if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0)
1481 goto err;
1482
1483 freq *= -1;
1484
1485 if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0)
1486 goto err;
1487 if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0)
1488 goto err;
1489
1490 }
1491
1492 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
1493 goto err;
1494 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
1495 goto err;
1496
1497 if (state->internal->dev_ver >= 0x20) {
1498 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1499 goto err;
1500 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1501 goto err;
1502
1503 if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
1504 (state->search_mode == STV090x_SEARCH_DSS) ||
1505 (state->search_mode == STV090x_SEARCH_AUTO)) {
1506
1507 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1508 goto err;
1509 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
1510 goto err;
1511 }
1512 }
1513
1514 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
1515 goto err;
1516 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
1517 goto err;
1518 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
1519 goto err;
1520
1521 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1522 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1523 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1524 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1525 goto err;
1526 reg = STV090x_READ_DEMOD(state, DMDCFG2);
1527 STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
1528 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
1529 goto err;
1530
1531 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0)
1532 goto err;
1533
1534 if (state->internal->dev_ver >= 0x20) {
1535 /*Frequency offset detector setting*/
1536 if (state->srate < 2000000) {
1537 if (state->internal->dev_ver <= 0x20) {
1538 /* Cut 2 */
1539 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0)
1540 goto err;
1541 } else {
1542 /* Cut 3 */
1543 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0)
1544 goto err;
1545 }
1546 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0)
1547 goto err;
1548 } else if (state->srate < 10000000) {
1549 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
1550 goto err;
1551 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
1552 goto err;
1553 } else {
1554 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
1555 goto err;
1556 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
1557 goto err;
1558 }
1559 } else {
1560 if (state->srate < 10000000) {
1561 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
1562 goto err;
1563 } else {
1564 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1565 goto err;
1566 }
1567 }
1568
1569 switch (state->algo) {
1570 case STV090x_WARM_SEARCH:
1571 /* The symbol rate and the exact
1572 * carrier Frequency are known
1573 */
1574 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1575 goto err;
1576 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
1577 goto err;
1578 break;
1579
1580 case STV090x_COLD_SEARCH:
1581 /* The symbol rate is known */
1582 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1583 goto err;
1584 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1585 goto err;
1586 break;
1587
1588 default:
1589 break;
1590 }
1591 return 0;
1592err:
1593 dprintk(FE_ERROR, 1, "I/O error");
1594 return -1;
1595}
1596
1597static int stv090x_get_agc2_min_level(struct stv090x_state *state)
1598{
1599 u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg;
1600 s32 i, j, steps, dir;
1601
1602 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1603 goto err;
1604 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1605 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1606 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1607 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1608 goto err;
1609
1610 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
1611 goto err;
1612 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1613 goto err;
1614 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
1615 goto err;
1616 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1617 goto err;
1618 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
1619 goto err;
1620 if (stv090x_set_srate(state, 1000000) < 0)
1621 goto err;
1622
1623 steps = state->search_range / 1000000;
1624 if (steps <= 0)
1625 steps = 1;
1626
1627 dir = 1;
1628 freq_step = (1000000 * 256) / (state->internal->mclk / 256);
1629 freq_init = 0;
1630
1631 for (i = 0; i < steps; i++) {
1632 if (dir > 0)
1633 freq_init = freq_init + (freq_step * i);
1634 else
1635 freq_init = freq_init - (freq_step * i);
1636
1637 dir *= -1;
1638
1639 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
1640 goto err;
1641 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
1642 goto err;
1643 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
1644 goto err;
1645 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
1646 goto err;
1647 msleep(10);
1648
1649 agc2 = 0;
1650 for (j = 0; j < 10; j++) {
1651 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1652 STV090x_READ_DEMOD(state, AGC2I0);
1653 }
1654 agc2 /= 10;
1655 if (agc2 < agc2_min)
1656 agc2_min = agc2;
1657 }
1658
1659 return agc2_min;
1660err:
1661 dprintk(FE_ERROR, 1, "I/O error");
1662 return -1;
1663}
1664
1665static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
1666{
1667 u8 r3, r2, r1, r0;
1668 s32 srate, int_1, int_2, tmp_1, tmp_2;
1669
1670 r3 = STV090x_READ_DEMOD(state, SFR3);
1671 r2 = STV090x_READ_DEMOD(state, SFR2);
1672 r1 = STV090x_READ_DEMOD(state, SFR1);
1673 r0 = STV090x_READ_DEMOD(state, SFR0);
1674
1675 srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
1676
1677 int_1 = clk >> 16;
1678 int_2 = srate >> 16;
1679
1680 tmp_1 = clk % 0x10000;
1681 tmp_2 = srate % 0x10000;
1682
1683 srate = (int_1 * int_2) +
1684 ((int_1 * tmp_2) >> 16) +
1685 ((int_2 * tmp_1) >> 16);
1686
1687 return srate;
1688}
1689
1690static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
1691{
1692 struct dvb_frontend *fe = &state->frontend;
1693
1694 int tmg_lock = 0, i;
1695 s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
1696 u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
1697 u32 agc2th;
1698
1699 if (state->internal->dev_ver >= 0x30)
1700 agc2th = 0x2e00;
1701 else
1702 agc2th = 0x1f00;
1703
1704 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1705 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
1706 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1707 goto err;
1708 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
1709 goto err;
1710 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0)
1711 goto err;
1712 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
1713 goto err;
1714 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
1715 goto err;
1716 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1717 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
1718 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1719 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1720 goto err;
1721
1722 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
1723 goto err;
1724 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1725 goto err;
1726 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
1727 goto err;
1728 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1729 goto err;
1730 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
1731 goto err;
1732 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0)
1733 goto err;
1734
1735 if (state->internal->dev_ver >= 0x30) {
1736 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0)
1737 goto err;
1738 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0)
1739 goto err;
1740
1741 } else if (state->internal->dev_ver >= 0x20) {
1742 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
1743 goto err;
1744 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
1745 goto err;
1746 }
1747
1748 if (state->srate <= 2000000)
1749 car_step = 1000;
1750 else if (state->srate <= 5000000)
1751 car_step = 2000;
1752 else if (state->srate <= 12000000)
1753 car_step = 3000;
1754 else
1755 car_step = 5000;
1756
1757 steps = -1 + ((state->search_range / 1000) / car_step);
1758 steps /= 2;
1759 steps = (2 * steps) + 1;
1760 if (steps < 0)
1761 steps = 1;
1762 else if (steps > 10) {
1763 steps = 11;
1764 car_step = (state->search_range / 1000) / 10;
1765 }
1766 cur_step = 0;
1767 dir = 1;
1768 freq = state->frequency;
1769
1770 while ((!tmg_lock) && (cur_step < steps)) {
1771 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
1772 goto err;
1773 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
1774 goto err;
1775 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1776 goto err;
1777 if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0)
1778 goto err;
1779 if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0)
1780 goto err;
1781 /* trigger acquisition */
1782 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0)
1783 goto err;
1784 msleep(50);
1785 for (i = 0; i < 10; i++) {
1786 reg = STV090x_READ_DEMOD(state, DSTATUS);
1787 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1788 tmg_cpt++;
1789 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1790 STV090x_READ_DEMOD(state, AGC2I0);
1791 }
1792 agc2 /= 10;
1793 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
1794 cur_step++;
1795 dir *= -1;
1796 if ((tmg_cpt >= 5) && (agc2 < agc2th) &&
1797 (srate_coarse < 50000000) && (srate_coarse > 850000))
1798 tmg_lock = 1;
1799 else if (cur_step < steps) {
1800 if (dir > 0)
1801 freq += cur_step * car_step;
1802 else
1803 freq -= cur_step * car_step;
1804
1805 /* Setup tuner */
1806 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
1807 goto err;
1808
1809 if (state->config->tuner_set_frequency) {
1810 if (state->config->tuner_set_frequency(fe, freq) < 0)
1811 goto err_gateoff;
1812 }
1813
1814 if (state->config->tuner_set_bandwidth) {
1815 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
1816 goto err_gateoff;
1817 }
1818
1819 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
1820 goto err;
1821
1822 msleep(50);
1823
1824 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
1825 goto err;
1826
1827 if (state->config->tuner_get_status) {
1828 if (state->config->tuner_get_status(fe, &reg) < 0)
1829 goto err_gateoff;
1830 }
1831
1832 if (reg)
1833 dprintk(FE_DEBUG, 1, "Tuner phase locked");
1834 else
1835 dprintk(FE_DEBUG, 1, "Tuner unlocked");
1836
1837 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
1838 goto err;
1839
1840 }
1841 }
1842 if (!tmg_lock)
1843 srate_coarse = 0;
1844 else
1845 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
1846
1847 return srate_coarse;
1848
1849err_gateoff:
1850 stv090x_i2c_gate_ctrl(state, 0);
1851err:
1852 dprintk(FE_ERROR, 1, "I/O error");
1853 return -1;
1854}
1855
1856static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
1857{
1858 u32 srate_coarse, freq_coarse, sym, reg;
1859
1860 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
1861 freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
1862 freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
1863 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1864
1865 if (sym < state->srate)
1866 srate_coarse = 0;
1867 else {
1868 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
1869 goto err;
1870 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
1871 goto err;
1872 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1873 goto err;
1874 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1875 goto err;
1876 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
1877 goto err;
1878 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1879 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
1880 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1881 goto err;
1882
1883 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1884 goto err;
1885
1886 if (state->internal->dev_ver >= 0x30) {
1887 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0)
1888 goto err;
1889 } else if (state->internal->dev_ver >= 0x20) {
1890 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
1891 goto err;
1892 }
1893
1894 if (srate_coarse > 3000000) {
1895 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1896 sym = (sym / 1000) * 65536;
1897 sym /= (state->internal->mclk / 1000);
1898 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1899 goto err;
1900 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1901 goto err;
1902 sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
1903 sym = (sym / 1000) * 65536;
1904 sym /= (state->internal->mclk / 1000);
1905 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1906 goto err;
1907 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1908 goto err;
1909 sym = (srate_coarse / 1000) * 65536;
1910 sym /= (state->internal->mclk / 1000);
1911 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1912 goto err;
1913 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1914 goto err;
1915 } else {
1916 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1917 sym = (sym / 100) * 65536;
1918 sym /= (state->internal->mclk / 100);
1919 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1920 goto err;
1921 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1922 goto err;
1923 sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
1924 sym = (sym / 100) * 65536;
1925 sym /= (state->internal->mclk / 100);
1926 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1927 goto err;
1928 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1929 goto err;
1930 sym = (srate_coarse / 100) * 65536;
1931 sym /= (state->internal->mclk / 100);
1932 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1933 goto err;
1934 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1935 goto err;
1936 }
1937 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
1938 goto err;
1939 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
1940 goto err;
1941 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
1942 goto err;
1943 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
1944 goto err;
1945 }
1946
1947 return srate_coarse;
1948
1949err:
1950 dprintk(FE_ERROR, 1, "I/O error");
1951 return -1;
1952}
1953
1954static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
1955{
1956 s32 timer = 0, lock = 0;
1957 u32 reg;
1958 u8 stat;
1959
1960 while ((timer < timeout) && (!lock)) {
1961 reg = STV090x_READ_DEMOD(state, DMDSTATE);
1962 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
1963
1964 switch (stat) {
1965 case 0: /* searching */
1966 case 1: /* first PLH detected */
1967 default:
1968 dprintk(FE_DEBUG, 1, "Demodulator searching ..");
1969 lock = 0;
1970 break;
1971 case 2: /* DVB-S2 mode */
1972 case 3: /* DVB-S1/legacy mode */
1973 reg = STV090x_READ_DEMOD(state, DSTATUS);
1974 lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
1975 break;
1976 }
1977
1978 if (!lock)
1979 msleep(10);
1980 else
1981 dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
1982
1983 timer += 10;
1984 }
1985 return lock;
1986}
1987
1988static int stv090x_blind_search(struct stv090x_state *state)
1989{
1990 u32 agc2, reg, srate_coarse;
1991 s32 cpt_fail, agc2_ovflw, i;
1992 u8 k_ref, k_max, k_min;
1993 int coarse_fail = 0;
1994 int lock;
1995
1996 k_max = 110;
1997 k_min = 10;
1998
1999 agc2 = stv090x_get_agc2_min_level(state);
2000
2001 if (agc2 > STV090x_SEARCH_AGC2_TH(state->internal->dev_ver)) {
2002 lock = 0;
2003 } else {
2004
2005 if (state->internal->dev_ver <= 0x20) {
2006 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
2007 goto err;
2008 } else {
2009 /* > Cut 3 */
2010 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0)
2011 goto err;
2012 }
2013
2014 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
2015 goto err;
2016
2017 if (state->internal->dev_ver >= 0x20) {
2018 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
2019 goto err;
2020 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
2021 goto err;
2022 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
2023 goto err;
2024 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
2025 goto err;
2026 }
2027
2028 k_ref = k_max;
2029 do {
2030 if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
2031 goto err;
2032 if (stv090x_srate_srch_coarse(state) != 0) {
2033 srate_coarse = stv090x_srate_srch_fine(state);
2034 if (srate_coarse != 0) {
2035 stv090x_get_lock_tmg(state);
2036 lock = stv090x_get_dmdlock(state,
2037 state->DemodTimeout);
2038 } else {
2039 lock = 0;
2040 }
2041 } else {
2042 cpt_fail = 0;
2043 agc2_ovflw = 0;
2044 for (i = 0; i < 10; i++) {
2045 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
2046 STV090x_READ_DEMOD(state, AGC2I0);
2047 if (agc2 >= 0xff00)
2048 agc2_ovflw++;
2049 reg = STV090x_READ_DEMOD(state, DSTATUS2);
2050 if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
2051 (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
2052
2053 cpt_fail++;
2054 }
2055 if ((cpt_fail > 7) || (agc2_ovflw > 7))
2056 coarse_fail = 1;
2057
2058 lock = 0;
2059 }
2060 k_ref -= 20;
2061 } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
2062 }
2063
2064 return lock;
2065
2066err:
2067 dprintk(FE_ERROR, 1, "I/O error");
2068 return -1;
2069}
2070
2071static int stv090x_chk_tmg(struct stv090x_state *state)
2072{
2073 u32 reg;
2074 s32 tmg_cpt = 0, i;
2075 u8 freq, tmg_thh, tmg_thl;
2076 int tmg_lock = 0;
2077
2078 freq = STV090x_READ_DEMOD(state, CARFREQ);
2079 tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
2080 tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
2081 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
2082 goto err;
2083 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
2084 goto err;
2085
2086 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2087 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
2088 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2089 goto err;
2090 if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
2091 goto err;
2092
2093 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
2094 goto err;
2095 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
2096 goto err;
2097
2098 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
2099 goto err;
2100 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
2101 goto err;
2102 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
2103 goto err;
2104
2105 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
2106 goto err;
2107 msleep(10);
2108
2109 for (i = 0; i < 10; i++) {
2110 reg = STV090x_READ_DEMOD(state, DSTATUS);
2111 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
2112 tmg_cpt++;
2113 msleep(1);
2114 }
2115 if (tmg_cpt >= 3)
2116 tmg_lock = 1;
2117
2118 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2119 goto err;
2120 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
2121 goto err;
2122 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
2123 goto err;
2124
2125 if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
2126 goto err;
2127 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
2128 goto err;
2129 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
2130 goto err;
2131
2132 return tmg_lock;
2133
2134err:
2135 dprintk(FE_ERROR, 1, "I/O error");
2136 return -1;
2137}
2138
2139static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
2140{
2141 struct dvb_frontend *fe = &state->frontend;
2142
2143 u32 reg;
2144 s32 car_step, steps, cur_step, dir, freq, timeout_lock;
2145 int lock;
2146
2147 if (state->srate >= 10000000)
2148 timeout_lock = timeout_dmd / 3;
2149 else
2150 timeout_lock = timeout_dmd / 2;
2151
2152 lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
2153 if (lock)
2154 return lock;
2155
2156 if (state->srate >= 10000000) {
2157 if (stv090x_chk_tmg(state)) {
2158 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2159 goto err;
2160 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
2161 goto err;
2162 return stv090x_get_dmdlock(state, timeout_dmd);
2163 }
2164 return 0;
2165 }
2166
2167 if (state->srate <= 4000000)
2168 car_step = 1000;
2169 else if (state->srate <= 7000000)
2170 car_step = 2000;
2171 else if (state->srate <= 10000000)
2172 car_step = 3000;
2173 else
2174 car_step = 5000;
2175
2176 steps = (state->search_range / 1000) / car_step;
2177 steps /= 2;
2178 steps = 2 * (steps + 1);
2179 if (steps < 0)
2180 steps = 2;
2181 else if (steps > 12)
2182 steps = 12;
2183
2184 cur_step = 1;
2185 dir = 1;
2186
2187 freq = state->frequency;
2188 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
2189 while ((cur_step <= steps) && (!lock)) {
2190 if (dir > 0)
2191 freq += cur_step * car_step;
2192 else
2193 freq -= cur_step * car_step;
2194
2195 /* Setup tuner */
2196 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
2197 goto err;
2198
2199 if (state->config->tuner_set_frequency) {
2200 if (state->config->tuner_set_frequency(fe, freq) < 0)
2201 goto err_gateoff;
2202 }
2203
2204 if (state->config->tuner_set_bandwidth) {
2205 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
2206 goto err_gateoff;
2207 }
2208
2209 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
2210 goto err;
2211
2212 msleep(50);
2213
2214 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
2215 goto err;
2216
2217 if (state->config->tuner_get_status) {
2218 if (state->config->tuner_get_status(fe, &reg) < 0)
2219 goto err_gateoff;
2220 }
2221
2222 if (reg)
2223 dprintk(FE_DEBUG, 1, "Tuner phase locked");
2224 else
2225 dprintk(FE_DEBUG, 1, "Tuner unlocked");
2226
2227 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
2228 goto err;
2229
2230 STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
2231 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
2232 goto err;
2233 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
2234 goto err;
2235 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2236 goto err;
2237 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
2238 goto err;
2239 lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
2240
2241 dir *= -1;
2242 cur_step++;
2243 }
2244
2245 return lock;
2246
2247err_gateoff:
2248 stv090x_i2c_gate_ctrl(state, 0);
2249err:
2250 dprintk(FE_ERROR, 1, "I/O error");
2251 return -1;
2252}
2253
2254static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
2255{
2256 s32 timeout, inc, steps_max, srate, car_max;
2257
2258 srate = state->srate;
2259 car_max = state->search_range / 1000;
2260 car_max += car_max / 10;
2261 car_max = 65536 * (car_max / 2);
2262 car_max /= (state->internal->mclk / 1000);
2263
2264 if (car_max > 0x4000)
2265 car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
2266
2267 inc = srate;
2268 inc /= state->internal->mclk / 1000;
2269 inc *= 256;
2270 inc *= 256;
2271 inc /= 1000;
2272
2273 switch (state->search_mode) {
2274 case STV090x_SEARCH_DVBS1:
2275 case STV090x_SEARCH_DSS:
2276 inc *= 3; /* freq step = 3% of srate */
2277 timeout = 20;
2278 break;
2279
2280 case STV090x_SEARCH_DVBS2:
2281 inc *= 4;
2282 timeout = 25;
2283 break;
2284
2285 case STV090x_SEARCH_AUTO:
2286 default:
2287 inc *= 3;
2288 timeout = 25;
2289 break;
2290 }
2291 inc /= 100;
2292 if ((inc > car_max) || (inc < 0))
2293 inc = car_max / 2; /* increment <= 1/8 Mclk */
2294
2295 timeout *= 27500; /* 27.5 Msps reference */
2296 if (srate > 0)
2297 timeout /= (srate / 1000);
2298
2299 if ((timeout > 100) || (timeout < 0))
2300 timeout = 100;
2301
2302 steps_max = (car_max / inc) + 1; /* min steps = 3 */
2303 if ((steps_max > 100) || (steps_max < 0)) {
2304 steps_max = 100; /* max steps <= 100 */
2305 inc = car_max / steps_max;
2306 }
2307 *freq_inc = inc;
2308 *timeout_sw = timeout;
2309 *steps = steps_max;
2310
2311 return 0;
2312}
2313
2314static int stv090x_chk_signal(struct stv090x_state *state)
2315{
2316 s32 offst_car, agc2, car_max;
2317 int no_signal;
2318
2319 offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
2320 offst_car |= STV090x_READ_DEMOD(state, CFR1);
2321 offst_car = comp2(offst_car, 16);
2322
2323 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
2324 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
2325 car_max = state->search_range / 1000;
2326
2327 car_max += (car_max / 10); /* 10% margin */
2328 car_max = (65536 * car_max / 2);
2329 car_max /= state->internal->mclk / 1000;
2330
2331 if (car_max > 0x4000)
2332 car_max = 0x4000;
2333
2334 if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
2335 no_signal = 1;
2336 dprintk(FE_DEBUG, 1, "No Signal");
2337 } else {
2338 no_signal = 0;
2339 dprintk(FE_DEBUG, 1, "Found Signal");
2340 }
2341
2342 return no_signal;
2343}
2344
2345static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
2346{
2347 int no_signal, lock = 0;
2348 s32 cpt_step = 0, offst_freq, car_max;
2349 u32 reg;
2350
2351 car_max = state->search_range / 1000;
2352 car_max += (car_max / 10);
2353 car_max = (65536 * car_max / 2);
2354 car_max /= (state->internal->mclk / 1000);
2355 if (car_max > 0x4000)
2356 car_max = 0x4000;
2357
2358 if (zigzag)
2359 offst_freq = 0;
2360 else
2361 offst_freq = -car_max + inc;
2362
2363 do {
2364 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
2365 goto err;
2366 if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
2367 goto err;
2368 if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
2369 goto err;
2370 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2371 goto err;
2372
2373 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2374 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
2375 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2376 goto err;
2377
2378 if (zigzag) {
2379 if (offst_freq >= 0)
2380 offst_freq = -offst_freq - 2 * inc;
2381 else
2382 offst_freq = -offst_freq;
2383 } else {
2384 offst_freq += 2 * inc;
2385 }
2386
2387 cpt_step++;
2388
2389 lock = stv090x_get_dmdlock(state, timeout);
2390 no_signal = stv090x_chk_signal(state);
2391
2392 } while ((!lock) &&
2393 (!no_signal) &&
2394 ((offst_freq - inc) < car_max) &&
2395 ((offst_freq + inc) > -car_max) &&
2396 (cpt_step < steps_max));
2397
2398 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2399 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
2400 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2401 goto err;
2402
2403 return lock;
2404err:
2405 dprintk(FE_ERROR, 1, "I/O error");
2406 return -1;
2407}
2408
2409static int stv090x_sw_algo(struct stv090x_state *state)
2410{
2411 int no_signal, zigzag, lock = 0;
2412 u32 reg;
2413
2414 s32 dvbs2_fly_wheel;
2415 s32 inc, timeout_step, trials, steps_max;
2416
2417 /* get params */
2418 stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max);
2419
2420 switch (state->search_mode) {
2421 case STV090x_SEARCH_DVBS1:
2422 case STV090x_SEARCH_DSS:
2423 /* accelerate the frequency detector */
2424 if (state->internal->dev_ver >= 0x20) {
2425 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
2426 goto err;
2427 }
2428
2429 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
2430 goto err;
2431 zigzag = 0;
2432 break;
2433
2434 case STV090x_SEARCH_DVBS2:
2435 if (state->internal->dev_ver >= 0x20) {
2436 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2437 goto err;
2438 }
2439
2440 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2441 goto err;
2442 zigzag = 1;
2443 break;
2444
2445 case STV090x_SEARCH_AUTO:
2446 default:
2447 /* accelerate the frequency detector */
2448 if (state->internal->dev_ver >= 0x20) {
2449 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
2450 goto err;
2451 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2452 goto err;
2453 }
2454
2455 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0)
2456 goto err;
2457 zigzag = 0;
2458 break;
2459 }
2460
2461 trials = 0;
2462 do {
2463 lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
2464 no_signal = stv090x_chk_signal(state);
2465 trials++;
2466
2467 /*run the SW search 2 times maximum*/
2468 if (lock || no_signal || (trials == 2)) {
2469 /*Check if the demod is not losing lock in DVBS2*/
2470 if (state->internal->dev_ver >= 0x20) {
2471 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2472 goto err;
2473 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
2474 goto err;
2475 }
2476
2477 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2478 if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
2479 /*Check if the demod is not losing lock in DVBS2*/
2480 msleep(timeout_step);
2481 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2482 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2483 if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
2484 msleep(timeout_step);
2485 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2486 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2487 }
2488 if (dvbs2_fly_wheel < 0xd) {
2489 /*FALSE lock, The demod is losing lock */
2490 lock = 0;
2491 if (trials < 2) {
2492 if (state->internal->dev_ver >= 0x20) {
2493 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2494 goto err;
2495 }
2496
2497 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2498 goto err;
2499 }
2500 }
2501 }
2502 }
2503 } while ((!lock) && (trials < 2) && (!no_signal));
2504
2505 return lock;
2506err:
2507 dprintk(FE_ERROR, 1, "I/O error");
2508 return -1;
2509}
2510
2511static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
2512{
2513 u32 reg;
2514 enum stv090x_delsys delsys;
2515
2516 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2517 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
2518 delsys = STV090x_DVBS2;
2519 else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
2520 reg = STV090x_READ_DEMOD(state, FECM);
2521 if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
2522 delsys = STV090x_DSS;
2523 else
2524 delsys = STV090x_DVBS1;
2525 } else {
2526 delsys = STV090x_ERROR;
2527 }
2528
2529 return delsys;
2530}
2531
2532/* in Hz */
2533static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
2534{
2535 s32 derot, int_1, int_2, tmp_1, tmp_2;
2536
2537 derot = STV090x_READ_DEMOD(state, CFR2) << 16;
2538 derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
2539 derot |= STV090x_READ_DEMOD(state, CFR0);
2540
2541 derot = comp2(derot, 24);
2542 int_1 = mclk >> 12;
2543 int_2 = derot >> 12;
2544
2545 /* carrier_frequency = MasterClock * Reg / 2^24 */
2546 tmp_1 = mclk % 0x1000;
2547 tmp_2 = derot % 0x1000;
2548
2549 derot = (int_1 * int_2) +
2550 ((int_1 * tmp_2) >> 12) +
2551 ((int_2 * tmp_1) >> 12);
2552
2553 return derot;
2554}
2555
2556static int stv090x_get_viterbi(struct stv090x_state *state)
2557{
2558 u32 reg, rate;
2559
2560 reg = STV090x_READ_DEMOD(state, VITCURPUN);
2561 rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
2562
2563 switch (rate) {
2564 case 13:
2565 state->fec = STV090x_PR12;
2566 break;
2567
2568 case 18:
2569 state->fec = STV090x_PR23;
2570 break;
2571
2572 case 21:
2573 state->fec = STV090x_PR34;
2574 break;
2575
2576 case 24:
2577 state->fec = STV090x_PR56;
2578 break;
2579
2580 case 25:
2581 state->fec = STV090x_PR67;
2582 break;
2583
2584 case 26:
2585 state->fec = STV090x_PR78;
2586 break;
2587
2588 default:
2589 state->fec = STV090x_PRERR;
2590 break;
2591 }
2592
2593 return 0;
2594}
2595
2596static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
2597{
2598 struct dvb_frontend *fe = &state->frontend;
2599
2600 u8 tmg;
2601 u32 reg;
2602 s32 i = 0, offst_freq;
2603
2604 msleep(5);
2605
2606 if (state->algo == STV090x_BLIND_SEARCH) {
2607 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2608 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
2609 while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) {
2610 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2611 msleep(5);
2612 i += 5;
2613 }
2614 }
2615 state->delsys = stv090x_get_std(state);
2616
2617 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
2618 goto err;
2619
2620 if (state->config->tuner_get_frequency) {
2621 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
2622 goto err_gateoff;
2623 }
2624
2625 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
2626 goto err;
2627
2628 offst_freq = stv090x_get_car_freq(state, state->internal->mclk) / 1000;
2629 state->frequency += offst_freq;
2630
2631 if (stv090x_get_viterbi(state) < 0)
2632 goto err;
2633
2634 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2635 state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2636 state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2637 state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
2638 reg = STV090x_READ_DEMOD(state, TMGOBS);
2639 state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2640 reg = STV090x_READ_DEMOD(state, FECM);
2641 state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
2642
2643 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
2644
2645 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
2646 goto err;
2647
2648 if (state->config->tuner_get_frequency) {
2649 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
2650 goto err_gateoff;
2651 }
2652
2653 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
2654 goto err;
2655
2656 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2657 return STV090x_RANGEOK;
2658 else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
2659 return STV090x_RANGEOK;
2660 } else {
2661 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2662 return STV090x_RANGEOK;
2663 }
2664
2665 return STV090x_OUTOFRANGE;
2666
2667err_gateoff:
2668 stv090x_i2c_gate_ctrl(state, 0);
2669err:
2670 dprintk(FE_ERROR, 1, "I/O error");
2671 return -1;
2672}
2673
2674static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
2675{
2676 s32 offst_tmg;
2677
2678 offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
2679 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
2680 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
2681
2682 offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
2683 if (!offst_tmg)
2684 offst_tmg = 1;
2685
2686 offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg);
2687 offst_tmg /= 320;
2688
2689 return offst_tmg;
2690}
2691
2692static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
2693{
2694 u8 aclc = 0x29;
2695 s32 i;
2696 struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low;
2697
2698 if (state->internal->dev_ver == 0x20) {
2699 car_loop = stv090x_s2_crl_cut20;
2700 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut20;
2701 car_loop_apsk_low = stv090x_s2_apsk_crl_cut20;
2702 } else {
2703 /* >= Cut 3 */
2704 car_loop = stv090x_s2_crl_cut30;
2705 car_loop_qpsk_low = stv090x_s2_lowqpsk_crl_cut30;
2706 car_loop_apsk_low = stv090x_s2_apsk_crl_cut30;
2707 }
2708
2709 if (modcod < STV090x_QPSK_12) {
2710 i = 0;
2711 while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod))
2712 i++;
2713
2714 if (i >= 3)
2715 i = 2;
2716
2717 } else {
2718 i = 0;
2719 while ((i < 14) && (modcod != car_loop[i].modcod))
2720 i++;
2721
2722 if (i >= 14) {
2723 i = 0;
2724 while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod))
2725 i++;
2726
2727 if (i >= 11)
2728 i = 10;
2729 }
2730 }
2731
2732 if (modcod <= STV090x_QPSK_25) {
2733 if (pilots) {
2734 if (state->srate <= 3000000)
2735 aclc = car_loop_qpsk_low[i].crl_pilots_on_2;
2736 else if (state->srate <= 7000000)
2737 aclc = car_loop_qpsk_low[i].crl_pilots_on_5;
2738 else if (state->srate <= 15000000)
2739 aclc = car_loop_qpsk_low[i].crl_pilots_on_10;
2740 else if (state->srate <= 25000000)
2741 aclc = car_loop_qpsk_low[i].crl_pilots_on_20;
2742 else
2743 aclc = car_loop_qpsk_low[i].crl_pilots_on_30;
2744 } else {
2745 if (state->srate <= 3000000)
2746 aclc = car_loop_qpsk_low[i].crl_pilots_off_2;
2747 else if (state->srate <= 7000000)
2748 aclc = car_loop_qpsk_low[i].crl_pilots_off_5;
2749 else if (state->srate <= 15000000)
2750 aclc = car_loop_qpsk_low[i].crl_pilots_off_10;
2751 else if (state->srate <= 25000000)
2752 aclc = car_loop_qpsk_low[i].crl_pilots_off_20;
2753 else
2754 aclc = car_loop_qpsk_low[i].crl_pilots_off_30;
2755 }
2756
2757 } else if (modcod <= STV090x_8PSK_910) {
2758 if (pilots) {
2759 if (state->srate <= 3000000)
2760 aclc = car_loop[i].crl_pilots_on_2;
2761 else if (state->srate <= 7000000)
2762 aclc = car_loop[i].crl_pilots_on_5;
2763 else if (state->srate <= 15000000)
2764 aclc = car_loop[i].crl_pilots_on_10;
2765 else if (state->srate <= 25000000)
2766 aclc = car_loop[i].crl_pilots_on_20;
2767 else
2768 aclc = car_loop[i].crl_pilots_on_30;
2769 } else {
2770 if (state->srate <= 3000000)
2771 aclc = car_loop[i].crl_pilots_off_2;
2772 else if (state->srate <= 7000000)
2773 aclc = car_loop[i].crl_pilots_off_5;
2774 else if (state->srate <= 15000000)
2775 aclc = car_loop[i].crl_pilots_off_10;
2776 else if (state->srate <= 25000000)
2777 aclc = car_loop[i].crl_pilots_off_20;
2778 else
2779 aclc = car_loop[i].crl_pilots_off_30;
2780 }
2781 } else { /* 16APSK and 32APSK */
2782 /*
2783 * This should never happen in practice, except if
2784 * something is really wrong at the car_loop table.
2785 */
2786 if (i >= 11)
2787 i = 10;
2788 if (state->srate <= 3000000)
2789 aclc = car_loop_apsk_low[i].crl_pilots_on_2;
2790 else if (state->srate <= 7000000)
2791 aclc = car_loop_apsk_low[i].crl_pilots_on_5;
2792 else if (state->srate <= 15000000)
2793 aclc = car_loop_apsk_low[i].crl_pilots_on_10;
2794 else if (state->srate <= 25000000)
2795 aclc = car_loop_apsk_low[i].crl_pilots_on_20;
2796 else
2797 aclc = car_loop_apsk_low[i].crl_pilots_on_30;
2798 }
2799
2800 return aclc;
2801}
2802
2803static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
2804{
2805 struct stv090x_short_frame_crloop *short_crl = NULL;
2806 s32 index = 0;
2807 u8 aclc = 0x0b;
2808
2809 switch (state->modulation) {
2810 case STV090x_QPSK:
2811 default:
2812 index = 0;
2813 break;
2814 case STV090x_8PSK:
2815 index = 1;
2816 break;
2817 case STV090x_16APSK:
2818 index = 2;
2819 break;
2820 case STV090x_32APSK:
2821 index = 3;
2822 break;
2823 }
2824
2825 if (state->internal->dev_ver >= 0x30) {
2826 /* Cut 3.0 and up */
2827 short_crl = stv090x_s2_short_crl_cut30;
2828 } else {
2829 /* Cut 2.0 and up: we don't support cuts older than 2.0 */
2830 short_crl = stv090x_s2_short_crl_cut20;
2831 }
2832
2833 if (state->srate <= 3000000)
2834 aclc = short_crl[index].crl_2;
2835 else if (state->srate <= 7000000)
2836 aclc = short_crl[index].crl_5;
2837 else if (state->srate <= 15000000)
2838 aclc = short_crl[index].crl_10;
2839 else if (state->srate <= 25000000)
2840 aclc = short_crl[index].crl_20;
2841 else
2842 aclc = short_crl[index].crl_30;
2843
2844 return aclc;
2845}
2846
2847static int stv090x_optimize_track(struct stv090x_state *state)
2848{
2849 struct dvb_frontend *fe = &state->frontend;
2850
2851 enum stv090x_modcod modcod;
2852
2853 s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
2854 u32 reg;
2855
2856 srate = stv090x_get_srate(state, state->internal->mclk);
2857 srate += stv090x_get_tmgoffst(state, srate);
2858
2859 switch (state->delsys) {
2860 case STV090x_DVBS1:
2861 case STV090x_DSS:
2862 if (state->search_mode == STV090x_SEARCH_AUTO) {
2863 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2864 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2865 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2866 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2867 goto err;
2868 }
2869 reg = STV090x_READ_DEMOD(state, DEMOD);
2870 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
2871 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01);
2872 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2873 goto err;
2874
2875 if (state->internal->dev_ver >= 0x30) {
2876 if (stv090x_get_viterbi(state) < 0)
2877 goto err;
2878
2879 if (state->fec == STV090x_PR12) {
2880 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0)
2881 goto err;
2882 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
2883 goto err;
2884 } else {
2885 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0)
2886 goto err;
2887 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
2888 goto err;
2889 }
2890 }
2891
2892 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
2893 goto err;
2894 break;
2895
2896 case STV090x_DVBS2:
2897 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2898 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
2899 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2900 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2901 goto err;
2902 if (state->internal->dev_ver >= 0x30) {
2903 if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
2904 goto err;
2905 if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
2906 goto err;
2907 }
2908 if (state->frame_len == STV090x_LONG_FRAME) {
2909 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2910 modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2911 pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2912 aclc = stv090x_optimize_carloop(state, modcod, pilots);
2913 if (modcod <= STV090x_QPSK_910) {
2914 STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
2915 } else if (modcod <= STV090x_8PSK_910) {
2916 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2917 goto err;
2918 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2919 goto err;
2920 }
2921 if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
2922 if (modcod <= STV090x_16APSK_910) {
2923 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2924 goto err;
2925 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2926 goto err;
2927 } else {
2928 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2929 goto err;
2930 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2931 goto err;
2932 }
2933 }
2934 } else {
2935 /*Carrier loop setting for short frame*/
2936 aclc = stv090x_optimize_carloop_short(state);
2937 if (state->modulation == STV090x_QPSK) {
2938 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
2939 goto err;
2940 } else if (state->modulation == STV090x_8PSK) {
2941 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2942 goto err;
2943 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2944 goto err;
2945 } else if (state->modulation == STV090x_16APSK) {
2946 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2947 goto err;
2948 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2949 goto err;
2950 } else if (state->modulation == STV090x_32APSK) {
2951 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2952 goto err;
2953 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2954 goto err;
2955 }
2956 }
2957
2958 STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
2959 break;
2960
2961 case STV090x_ERROR:
2962 default:
2963 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2964 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2965 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2966 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2967 goto err;
2968 break;
2969 }
2970
2971 f_1 = STV090x_READ_DEMOD(state, CFR2);
2972 f_0 = STV090x_READ_DEMOD(state, CFR1);
2973 reg = STV090x_READ_DEMOD(state, TMGOBS);
2974
2975 if (state->algo == STV090x_BLIND_SEARCH) {
2976 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
2977 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2978 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
2979 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
2980 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2981 goto err;
2982 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
2983 goto err;
2984
2985 if (stv090x_set_srate(state, srate) < 0)
2986 goto err;
2987 blind_tune = 1;
2988
2989 if (stv090x_dvbs_track_crl(state) < 0)
2990 goto err;
2991 }
2992
2993 if (state->internal->dev_ver >= 0x20) {
2994 if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
2995 (state->search_mode == STV090x_SEARCH_DSS) ||
2996 (state->search_mode == STV090x_SEARCH_AUTO)) {
2997
2998 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
2999 goto err;
3000 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
3001 goto err;
3002 }
3003 }
3004
3005 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
3006 goto err;
3007
3008 /* AUTO tracking MODE */
3009 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0)
3010 goto err;
3011 /* AUTO tracking MODE */
3012 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0)
3013 goto err;
3014
3015 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1) ||
3016 (state->srate < 10000000)) {
3017 /* update initial carrier freq with the found freq offset */
3018 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
3019 goto err;
3020 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
3021 goto err;
3022 state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
3023
3024 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1)) {
3025
3026 if (state->algo != STV090x_WARM_SEARCH) {
3027
3028 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
3029 goto err;
3030
3031 if (state->config->tuner_set_bandwidth) {
3032 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
3033 goto err_gateoff;
3034 }
3035
3036 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
3037 goto err;
3038
3039 }
3040 }
3041 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
3042 msleep(50); /* blind search: wait 50ms for SR stabilization */
3043 else
3044 msleep(5);
3045
3046 stv090x_get_lock_tmg(state);
3047
3048 if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
3049 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
3050 goto err;
3051 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
3052 goto err;
3053 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
3054 goto err;
3055 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
3056 goto err;
3057
3058 i = 0;
3059
3060 while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
3061
3062 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
3063 goto err;
3064 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
3065 goto err;
3066 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
3067 goto err;
3068 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
3069 goto err;
3070 i++;
3071 }
3072 }
3073
3074 }
3075
3076 if (state->internal->dev_ver >= 0x20) {
3077 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
3078 goto err;
3079 }
3080
3081 if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
3082 stv090x_set_vit_thtracq(state);
3083
3084 return 0;
3085
3086err_gateoff:
3087 stv090x_i2c_gate_ctrl(state, 0);
3088err:
3089 dprintk(FE_ERROR, 1, "I/O error");
3090 return -1;
3091}
3092
3093static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
3094{
3095 s32 timer = 0, lock = 0, stat;
3096 u32 reg;
3097
3098 while ((timer < timeout) && (!lock)) {
3099 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3100 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3101
3102 switch (stat) {
3103 case 0: /* searching */
3104 case 1: /* first PLH detected */
3105 default:
3106 lock = 0;
3107 break;
3108
3109 case 2: /* DVB-S2 mode */
3110 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
3111 lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
3112 break;
3113
3114 case 3: /* DVB-S1/legacy mode */
3115 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3116 lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
3117 break;
3118 }
3119 if (!lock) {
3120 msleep(10);
3121 timer += 10;
3122 }
3123 }
3124 return lock;
3125}
3126
3127static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
3128{
3129 u32 reg;
3130 s32 timer = 0;
3131 int lock;
3132
3133 lock = stv090x_get_dmdlock(state, timeout_dmd);
3134 if (lock)
3135 lock = stv090x_get_feclock(state, timeout_fec);
3136
3137 if (lock) {
3138 lock = 0;
3139
3140 while ((timer < timeout_fec) && (!lock)) {
3141 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3142 lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
3143 msleep(1);
3144 timer++;
3145 }
3146 }
3147
3148 return lock;
3149}
3150
3151static int stv090x_set_s2rolloff(struct stv090x_state *state)
3152{
3153 u32 reg;
3154
3155 if (state->internal->dev_ver <= 0x20) {
3156 /* rolloff to auto mode if DVBS2 */
3157 reg = STV090x_READ_DEMOD(state, DEMOD);
3158 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00);
3159 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3160 goto err;
3161 } else {
3162 /* DVB-S2 rolloff to auto mode if DVBS2 */
3163 reg = STV090x_READ_DEMOD(state, DEMOD);
3164 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00);
3165 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3166 goto err;
3167 }
3168 return 0;
3169err:
3170 dprintk(FE_ERROR, 1, "I/O error");
3171 return -1;
3172}
3173
3174
3175static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
3176{
3177 struct dvb_frontend *fe = &state->frontend;
3178 enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
3179 u32 reg;
3180 s32 agc1_power, power_iq = 0, i;
3181 int lock = 0, low_sr = 0;
3182
3183 reg = STV090x_READ_DEMOD(state, TSCFGH);
3184 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
3185 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3186 goto err;
3187
3188 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
3189 goto err;
3190
3191 if (state->internal->dev_ver >= 0x20) {
3192 if (state->srate > 5000000) {
3193 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
3194 goto err;
3195 } else {
3196 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0)
3197 goto err;
3198 }
3199 }
3200
3201 stv090x_get_lock_tmg(state);
3202
3203 if (state->algo == STV090x_BLIND_SEARCH) {
3204 state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
3205 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */
3206 goto err;
3207 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
3208 goto err;
3209 if (stv090x_set_srate(state, 1000000) < 0) /* initial srate = 1Msps */
3210 goto err;
3211 } else {
3212 /* known srate */
3213 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
3214 goto err;
3215 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
3216 goto err;
3217
3218 if (state->srate < 2000000) {
3219 /* SR < 2MSPS */
3220 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0)
3221 goto err;
3222 } else {
3223 /* SR >= 2Msps */
3224 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
3225 goto err;
3226 }
3227
3228 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
3229 goto err;
3230
3231 if (state->internal->dev_ver >= 0x20) {
3232 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
3233 goto err;
3234 if (state->algo == STV090x_COLD_SEARCH)
3235 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
3236 else if (state->algo == STV090x_WARM_SEARCH)
3237 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
3238 }
3239
3240 /* if cold start or warm (Symbolrate is known)
3241 * use a Narrow symbol rate scan range
3242 */
3243 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */
3244 goto err;
3245
3246 if (stv090x_set_srate(state, state->srate) < 0)
3247 goto err;
3248
3249 if (stv090x_set_max_srate(state, state->internal->mclk,
3250 state->srate) < 0)
3251 goto err;
3252 if (stv090x_set_min_srate(state, state->internal->mclk,
3253 state->srate) < 0)
3254 goto err;
3255
3256 if (state->srate >= 10000000)
3257 low_sr = 0;
3258 else
3259 low_sr = 1;
3260 }
3261
3262 /* Setup tuner */
3263 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
3264 goto err;
3265
3266 if (state->config->tuner_set_bbgain) {
3267 reg = state->config->tuner_bbgain;
3268 if (reg == 0)
3269 reg = 10; /* default: 10dB */
3270 if (state->config->tuner_set_bbgain(fe, reg) < 0)
3271 goto err_gateoff;
3272 }
3273
3274 if (state->config->tuner_set_frequency) {
3275 if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
3276 goto err_gateoff;
3277 }
3278
3279 if (state->config->tuner_set_bandwidth) {
3280 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
3281 goto err_gateoff;
3282 }
3283
3284 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
3285 goto err;
3286
3287 msleep(50);
3288
3289 if (state->config->tuner_get_status) {
3290 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
3291 goto err;
3292 if (state->config->tuner_get_status(fe, &reg) < 0)
3293 goto err_gateoff;
3294 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
3295 goto err;
3296
3297 if (reg)
3298 dprintk(FE_DEBUG, 1, "Tuner phase locked");
3299 else {
3300 dprintk(FE_DEBUG, 1, "Tuner unlocked");
3301 return STV090x_NOCARRIER;
3302 }
3303 }
3304
3305 msleep(10);
3306 agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1),
3307 STV090x_READ_DEMOD(state, AGCIQIN0));
3308
3309 if (agc1_power == 0) {
3310 /* If AGC1 integrator value is 0
3311 * then read POWERI, POWERQ
3312 */
3313 for (i = 0; i < 5; i++) {
3314 power_iq += (STV090x_READ_DEMOD(state, POWERI) +
3315 STV090x_READ_DEMOD(state, POWERQ)) >> 1;
3316 }
3317 power_iq /= 5;
3318 }
3319
3320 if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) {
3321 dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq);
3322 lock = 0;
3323 signal_state = STV090x_NOAGC1;
3324 } else {
3325 reg = STV090x_READ_DEMOD(state, DEMOD);
3326 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
3327
3328 if (state->internal->dev_ver <= 0x20) {
3329 /* rolloff to auto mode if DVBS2 */
3330 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1);
3331 } else {
3332 /* DVB-S2 rolloff to auto mode if DVBS2 */
3333 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1);
3334 }
3335 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3336 goto err;
3337
3338 if (stv090x_delivery_search(state) < 0)
3339 goto err;
3340
3341 if (state->algo != STV090x_BLIND_SEARCH) {
3342 if (stv090x_start_search(state) < 0)
3343 goto err;
3344 }
3345 }
3346
3347 if (signal_state == STV090x_NOAGC1)
3348 return signal_state;
3349
3350 if (state->algo == STV090x_BLIND_SEARCH)
3351 lock = stv090x_blind_search(state);
3352
3353 else if (state->algo == STV090x_COLD_SEARCH)
3354 lock = stv090x_get_coldlock(state, state->DemodTimeout);
3355
3356 else if (state->algo == STV090x_WARM_SEARCH)
3357 lock = stv090x_get_dmdlock(state, state->DemodTimeout);
3358
3359 if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
3360 if (!low_sr) {
3361 if (stv090x_chk_tmg(state))
3362 lock = stv090x_sw_algo(state);
3363 }
3364 }
3365
3366 if (lock)
3367 signal_state = stv090x_get_sig_params(state);
3368
3369 if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
3370 stv090x_optimize_track(state);
3371
3372 if (state->internal->dev_ver >= 0x20) {
3373 /* >= Cut 2.0 :release TS reset after
3374 * demod lock and optimized Tracking
3375 */
3376 reg = STV090x_READ_DEMOD(state, TSCFGH);
3377 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3378 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3379 goto err;
3380
3381 msleep(3);
3382
3383 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3384 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3385 goto err;
3386
3387 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3388 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3389 goto err;
3390 }
3391
3392 lock = stv090x_get_lock(state, state->FecTimeout,
3393 state->FecTimeout);
3394 if (lock) {
3395 if (state->delsys == STV090x_DVBS2) {
3396 stv090x_set_s2rolloff(state);
3397
3398 reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3399 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1);
3400 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
3401 goto err;
3402 /* Reset DVBS2 packet delinator error counter */
3403 reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3404 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0);
3405 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
3406 goto err;
3407
3408 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
3409 goto err;
3410 } else {
3411 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
3412 goto err;
3413 }
3414 /* Reset the Total packet counter */
3415 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
3416 goto err;
3417 /* Reset the packet Error counter2 */
3418 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3419 goto err;
3420 } else {
3421 signal_state = STV090x_NODATA;
3422 stv090x_chk_signal(state);
3423 }
3424 }
3425 return signal_state;
3426
3427err_gateoff:
3428 stv090x_i2c_gate_ctrl(state, 0);
3429err:
3430 dprintk(FE_ERROR, 1, "I/O error");
3431 return -1;
3432}
3433
3434static int stv090x_set_mis(struct stv090x_state *state, int mis)
3435{
3436 u32 reg;
3437
3438 if (mis < 0 || mis > 255) {
3439 dprintk(FE_DEBUG, 1, "Disable MIS filtering");
3440 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3441 STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x00);
3442 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3443 goto err;
3444 } else {
3445 dprintk(FE_DEBUG, 1, "Enable MIS filtering - %d", mis);
3446 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3447 STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x01);
3448 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3449 goto err;
3450 if (STV090x_WRITE_DEMOD(state, ISIENTRY, mis) < 0)
3451 goto err;
3452 if (STV090x_WRITE_DEMOD(state, ISIBITENA, 0xff) < 0)
3453 goto err;
3454 }
3455 return 0;
3456err:
3457 dprintk(FE_ERROR, 1, "I/O error");
3458 return -1;
3459}
3460
3461static enum dvbfe_search stv090x_search(struct dvb_frontend *fe)
3462{
3463 struct stv090x_state *state = fe->demodulator_priv;
3464 struct dtv_frontend_properties *props = &fe->dtv_property_cache;
3465
3466 if (props->frequency == 0)
3467 return DVBFE_ALGO_SEARCH_INVALID;
3468
3469 switch (props->delivery_system) {
3470 case SYS_DSS:
3471 state->delsys = STV090x_DSS;
3472 break;
3473 case SYS_DVBS:
3474 state->delsys = STV090x_DVBS1;
3475 break;
3476 case SYS_DVBS2:
3477 state->delsys = STV090x_DVBS2;
3478 break;
3479 default:
3480 return DVBFE_ALGO_SEARCH_INVALID;
3481 }
3482
3483 state->frequency = props->frequency;
3484 state->srate = props->symbol_rate;
3485 state->search_mode = STV090x_SEARCH_AUTO;
3486 state->algo = STV090x_COLD_SEARCH;
3487 state->fec = STV090x_PRERR;
3488 if (state->srate > 10000000) {
3489 dprintk(FE_DEBUG, 1, "Search range: 10 MHz");
3490 state->search_range = 10000000;
3491 } else {
3492 dprintk(FE_DEBUG, 1, "Search range: 5 MHz");
3493 state->search_range = 5000000;
3494 }
3495
3496 stv090x_set_mis(state, props->stream_id);
3497
3498 if (stv090x_algo(state) == STV090x_RANGEOK) {
3499 dprintk(FE_DEBUG, 1, "Search success!");
3500 return DVBFE_ALGO_SEARCH_SUCCESS;
3501 } else {
3502 dprintk(FE_DEBUG, 1, "Search failed!");
3503 return DVBFE_ALGO_SEARCH_FAILED;
3504 }
3505
3506 return DVBFE_ALGO_SEARCH_ERROR;
3507}
3508
3509static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
3510{
3511 struct stv090x_state *state = fe->demodulator_priv;
3512 u32 reg, dstatus;
3513 u8 search_state;
3514
3515 *status = 0;
3516
3517 dstatus = STV090x_READ_DEMOD(state, DSTATUS);
3518 if (STV090x_GETFIELD_Px(dstatus, CAR_LOCK_FIELD))
3519 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
3520
3521 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3522 search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3523
3524 switch (search_state) {
3525 case 0: /* searching */
3526 case 1: /* first PLH detected */
3527 default:
3528 dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
3529 break;
3530
3531 case 2: /* DVB-S2 mode */
3532 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
3533 if (STV090x_GETFIELD_Px(dstatus, LOCK_DEFINITIF_FIELD)) {
3534 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
3535 if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) {
3536 *status |= FE_HAS_VITERBI;
3537 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3538 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD))
3539 *status |= FE_HAS_SYNC | FE_HAS_LOCK;
3540 }
3541 }
3542 break;
3543
3544 case 3: /* DVB-S1/legacy mode */
3545 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
3546 if (STV090x_GETFIELD_Px(dstatus, LOCK_DEFINITIF_FIELD)) {
3547 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3548 if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
3549 *status |= FE_HAS_VITERBI;
3550 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3551 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD))
3552 *status |= FE_HAS_SYNC | FE_HAS_LOCK;
3553 }
3554 }
3555 break;
3556 }
3557
3558 return 0;
3559}
3560
3561static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
3562{
3563 struct stv090x_state *state = fe->demodulator_priv;
3564
3565 s32 count_4, count_3, count_2, count_1, count_0, count;
3566 u32 reg, h, m, l;
3567 enum fe_status status;
3568
3569 stv090x_read_status(fe, &status);
3570 if (!(status & FE_HAS_LOCK)) {
3571 *per = 1 << 23; /* Max PER */
3572 } else {
3573 /* Counter 2 */
3574 reg = STV090x_READ_DEMOD(state, ERRCNT22);
3575 h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
3576
3577 reg = STV090x_READ_DEMOD(state, ERRCNT21);
3578 m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
3579
3580 reg = STV090x_READ_DEMOD(state, ERRCNT20);
3581 l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
3582
3583 *per = ((h << 16) | (m << 8) | l);
3584
3585 count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
3586 count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
3587 count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
3588 count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
3589 count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
3590
3591 if ((!count_4) && (!count_3)) {
3592 count = (count_2 & 0xff) << 16;
3593 count |= (count_1 & 0xff) << 8;
3594 count |= count_0 & 0xff;
3595 } else {
3596 count = 1 << 24;
3597 }
3598 if (count == 0)
3599 *per = 1;
3600 }
3601 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
3602 goto err;
3603 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3604 goto err;
3605
3606 return 0;
3607err:
3608 dprintk(FE_ERROR, 1, "I/O error");
3609 return -1;
3610}
3611
3612static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
3613{
3614 int res = 0;
3615 int min = 0, med;
3616
3617 if ((val >= tab[min].read && val < tab[max].read) ||
3618 (val >= tab[max].read && val < tab[min].read)) {
3619 while ((max - min) > 1) {
3620 med = (max + min) / 2;
3621 if ((val >= tab[min].read && val < tab[med].read) ||
3622 (val >= tab[med].read && val < tab[min].read))
3623 max = med;
3624 else
3625 min = med;
3626 }
3627 res = ((val - tab[min].read) *
3628 (tab[max].real - tab[min].real) /
3629 (tab[max].read - tab[min].read)) +
3630 tab[min].real;
3631 } else {
3632 if (tab[min].read < tab[max].read) {
3633 if (val < tab[min].read)
3634 res = tab[min].real;
3635 else if (val >= tab[max].read)
3636 res = tab[max].real;
3637 } else {
3638 if (val >= tab[min].read)
3639 res = tab[min].real;
3640 else if (val < tab[max].read)
3641 res = tab[max].real;
3642 }
3643 }
3644
3645 return res;
3646}
3647
3648static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
3649{
3650 struct stv090x_state *state = fe->demodulator_priv;
3651 u32 reg;
3652 s32 agc_0, agc_1, agc;
3653 s32 str;
3654
3655 reg = STV090x_READ_DEMOD(state, AGCIQIN1);
3656 agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3657 reg = STV090x_READ_DEMOD(state, AGCIQIN0);
3658 agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3659 agc = MAKEWORD16(agc_1, agc_0);
3660
3661 str = stv090x_table_lookup(stv090x_rf_tab,
3662 ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
3663 if (agc > stv090x_rf_tab[0].read)
3664 str = 0;
3665 else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
3666 str = -100;
3667 *strength = (str + 100) * 0xFFFF / 100;
3668
3669 return 0;
3670}
3671
3672static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
3673{
3674 struct stv090x_state *state = fe->demodulator_priv;
3675 u32 reg_0, reg_1, reg, i;
3676 s32 val_0, val_1, val = 0;
3677 u8 lock_f;
3678 s32 div;
3679 u32 last;
3680
3681 switch (state->delsys) {
3682 case STV090x_DVBS2:
3683 reg = STV090x_READ_DEMOD(state, DSTATUS);
3684 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3685 if (lock_f) {
3686 msleep(5);
3687 for (i = 0; i < 16; i++) {
3688 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
3689 val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
3690 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
3691 val_0 = STV090x_GETFIELD_Px(reg_0, NOSPLHT_NORMED_FIELD);
3692 val += MAKEWORD16(val_1, val_0);
3693 msleep(1);
3694 }
3695 val /= 16;
3696 last = ARRAY_SIZE(stv090x_s2cn_tab) - 1;
3697 div = stv090x_s2cn_tab[last].real -
3698 stv090x_s2cn_tab[3].real;
3699 val = stv090x_table_lookup(stv090x_s2cn_tab, last, val);
3700 if (val < 0)
3701 val = 0;
3702 *cnr = val * 0xFFFF / div;
3703 }
3704 break;
3705
3706 case STV090x_DVBS1:
3707 case STV090x_DSS:
3708 reg = STV090x_READ_DEMOD(state, DSTATUS);
3709 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3710 if (lock_f) {
3711 msleep(5);
3712 for (i = 0; i < 16; i++) {
3713 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
3714 val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
3715 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
3716 val_0 = STV090x_GETFIELD_Px(reg_0, NOSDATAT_UNNORMED_FIELD);
3717 val += MAKEWORD16(val_1, val_0);
3718 msleep(1);
3719 }
3720 val /= 16;
3721 last = ARRAY_SIZE(stv090x_s1cn_tab) - 1;
3722 div = stv090x_s1cn_tab[last].real -
3723 stv090x_s1cn_tab[0].real;
3724 val = stv090x_table_lookup(stv090x_s1cn_tab, last, val);
3725 *cnr = val * 0xFFFF / div;
3726 }
3727 break;
3728 default:
3729 break;
3730 }
3731
3732 return 0;
3733}
3734
3735static int stv090x_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
3736{
3737 struct stv090x_state *state = fe->demodulator_priv;
3738 u32 reg;
3739
3740 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3741 switch (tone) {
3742 case SEC_TONE_ON:
3743 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3744 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3745 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3746 goto err;
3747 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3748 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3749 goto err;
3750 break;
3751
3752 case SEC_TONE_OFF:
3753 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3754 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3755 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3756 goto err;
3757 break;
3758 default:
3759 return -EINVAL;
3760 }
3761
3762 return 0;
3763err:
3764 dprintk(FE_ERROR, 1, "I/O error");
3765 return -1;
3766}
3767
3768
3769static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
3770{
3771 return DVBFE_ALGO_CUSTOM;
3772}
3773
3774static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
3775{
3776 struct stv090x_state *state = fe->demodulator_priv;
3777 u32 reg, idle = 0, fifo_full = 1;
3778 int i;
3779
3780 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3781
3782 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD,
3783 (state->config->diseqc_envelope_mode) ? 4 : 2);
3784 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3785 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3786 goto err;
3787 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3788 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3789 goto err;
3790
3791 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3792 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3793 goto err;
3794
3795 for (i = 0; i < cmd->msg_len; i++) {
3796
3797 while (fifo_full) {
3798 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3799 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3800 }
3801
3802 if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
3803 goto err;
3804 }
3805 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3806 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3807 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3808 goto err;
3809
3810 i = 0;
3811
3812 while ((!idle) && (i < 10)) {
3813 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3814 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3815 msleep(10);
3816 i++;
3817 }
3818
3819 return 0;
3820err:
3821 dprintk(FE_ERROR, 1, "I/O error");
3822 return -1;
3823}
3824
3825static int stv090x_send_diseqc_burst(struct dvb_frontend *fe,
3826 enum fe_sec_mini_cmd burst)
3827{
3828 struct stv090x_state *state = fe->demodulator_priv;
3829 u32 reg, idle = 0, fifo_full = 1;
3830 u8 mode, value;
3831 int i;
3832
3833 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3834
3835 if (burst == SEC_MINI_A) {
3836 mode = (state->config->diseqc_envelope_mode) ? 5 : 3;
3837 value = 0x00;
3838 } else {
3839 mode = (state->config->diseqc_envelope_mode) ? 4 : 2;
3840 value = 0xFF;
3841 }
3842
3843 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode);
3844 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3845 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3846 goto err;
3847 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3848 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3849 goto err;
3850
3851 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3852 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3853 goto err;
3854
3855 while (fifo_full) {
3856 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3857 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3858 }
3859
3860 if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0)
3861 goto err;
3862
3863 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3864 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3865 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3866 goto err;
3867
3868 i = 0;
3869
3870 while ((!idle) && (i < 10)) {
3871 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3872 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3873 msleep(10);
3874 i++;
3875 }
3876
3877 return 0;
3878err:
3879 dprintk(FE_ERROR, 1, "I/O error");
3880 return -1;
3881}
3882
3883static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
3884{
3885 struct stv090x_state *state = fe->demodulator_priv;
3886 u32 reg = 0, i = 0, rx_end = 0;
3887
3888 while ((rx_end != 1) && (i < 10)) {
3889 msleep(10);
3890 i++;
3891 reg = STV090x_READ_DEMOD(state, DISRX_ST0);
3892 rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
3893 }
3894
3895 if (rx_end) {
3896 reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
3897 for (i = 0; i < reply->msg_len; i++)
3898 reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
3899 }
3900
3901 return 0;
3902}
3903
3904static int stv090x_sleep(struct dvb_frontend *fe)
3905{
3906 struct stv090x_state *state = fe->demodulator_priv;
3907 u32 reg;
3908 u8 full_standby = 0;
3909
3910 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
3911 goto err;
3912
3913 if (state->config->tuner_sleep) {
3914 if (state->config->tuner_sleep(fe) < 0)
3915 goto err_gateoff;
3916 }
3917
3918 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
3919 goto err;
3920
3921 dprintk(FE_DEBUG, 1, "Set %s(%d) to sleep",
3922 state->device == STV0900 ? "STV0900" : "STV0903",
3923 state->demod);
3924
3925 mutex_lock(&state->internal->demod_lock);
3926
3927 switch (state->demod) {
3928 case STV090x_DEMODULATOR_0:
3929 /* power off ADC 1 */
3930 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3931 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
3932 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3933 goto err_unlock;
3934 /* power off DiSEqC 1 */
3935 reg = stv090x_read_reg(state, STV090x_TSTTNR2);
3936 STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 0);
3937 if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0)
3938 goto err_unlock;
3939
3940 /* check whether path 2 is already sleeping, that is when
3941 ADC2 is off */
3942 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
3943 if (STV090x_GETFIELD(reg, ADC2_PON_FIELD) == 0)
3944 full_standby = 1;
3945
3946 /* stop clocks */
3947 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
3948 /* packet delineator 1 clock */
3949 STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 1);
3950 /* ADC 1 clock */
3951 STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 1);
3952 /* FEC clock is shared between the two paths, only stop it
3953 when full standby is possible */
3954 if (full_standby)
3955 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1);
3956 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
3957 goto err_unlock;
3958 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
3959 /* sampling 1 clock */
3960 STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 1);
3961 /* viterbi 1 clock */
3962 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 1);
3963 /* TS clock is shared between the two paths, only stop it
3964 when full standby is possible */
3965 if (full_standby)
3966 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1);
3967 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
3968 goto err_unlock;
3969 break;
3970
3971 case STV090x_DEMODULATOR_1:
3972 /* power off ADC 2 */
3973 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
3974 STV090x_SETFIELD(reg, ADC2_PON_FIELD, 0);
3975 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
3976 goto err_unlock;
3977 /* power off DiSEqC 2 */
3978 reg = stv090x_read_reg(state, STV090x_TSTTNR4);
3979 STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 0);
3980 if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0)
3981 goto err_unlock;
3982
3983 /* check whether path 1 is already sleeping, that is when
3984 ADC1 is off */
3985 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3986 if (STV090x_GETFIELD(reg, ADC1_PON_FIELD) == 0)
3987 full_standby = 1;
3988
3989 /* stop clocks */
3990 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
3991 /* packet delineator 2 clock */
3992 STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 1);
3993 /* ADC 2 clock */
3994 STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 1);
3995 /* FEC clock is shared between the two paths, only stop it
3996 when full standby is possible */
3997 if (full_standby)
3998 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1);
3999 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
4000 goto err_unlock;
4001 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
4002 /* sampling 2 clock */
4003 STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 1);
4004 /* viterbi 2 clock */
4005 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 1);
4006 /* TS clock is shared between the two paths, only stop it
4007 when full standby is possible */
4008 if (full_standby)
4009 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1);
4010 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
4011 goto err_unlock;
4012 break;
4013
4014 default:
4015 dprintk(FE_ERROR, 1, "Wrong demodulator!");
4016 break;
4017 }
4018
4019 if (full_standby) {
4020 /* general power off */
4021 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4022 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
4023 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
4024 goto err_unlock;
4025 }
4026
4027 mutex_unlock(&state->internal->demod_lock);
4028 return 0;
4029
4030err_gateoff:
4031 stv090x_i2c_gate_ctrl(state, 0);
4032 goto err;
4033err_unlock:
4034 mutex_unlock(&state->internal->demod_lock);
4035err:
4036 dprintk(FE_ERROR, 1, "I/O error");
4037 return -1;
4038}
4039
4040static int stv090x_wakeup(struct dvb_frontend *fe)
4041{
4042 struct stv090x_state *state = fe->demodulator_priv;
4043 u32 reg;
4044
4045 dprintk(FE_DEBUG, 1, "Wake %s(%d) from standby",
4046 state->device == STV0900 ? "STV0900" : "STV0903",
4047 state->demod);
4048
4049 mutex_lock(&state->internal->demod_lock);
4050
4051 /* general power on */
4052 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4053 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
4054 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
4055 goto err;
4056
4057 switch (state->demod) {
4058 case STV090x_DEMODULATOR_0:
4059 /* power on ADC 1 */
4060 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
4061 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
4062 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
4063 goto err;
4064 /* power on DiSEqC 1 */
4065 reg = stv090x_read_reg(state, STV090x_TSTTNR2);
4066 STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 1);
4067 if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0)
4068 goto err;
4069
4070 /* activate clocks */
4071 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
4072 /* packet delineator 1 clock */
4073 STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 0);
4074 /* ADC 1 clock */
4075 STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 0);
4076 /* FEC clock */
4077 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0);
4078 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
4079 goto err;
4080 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
4081 /* sampling 1 clock */
4082 STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 0);
4083 /* viterbi 1 clock */
4084 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 0);
4085 /* TS clock */
4086 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0);
4087 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
4088 goto err;
4089 break;
4090
4091 case STV090x_DEMODULATOR_1:
4092 /* power on ADC 2 */
4093 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
4094 STV090x_SETFIELD(reg, ADC2_PON_FIELD, 1);
4095 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
4096 goto err;
4097 /* power on DiSEqC 2 */
4098 reg = stv090x_read_reg(state, STV090x_TSTTNR4);
4099 STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 1);
4100 if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0)
4101 goto err;
4102
4103 /* activate clocks */
4104 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
4105 /* packet delineator 2 clock */
4106 STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 0);
4107 /* ADC 2 clock */
4108 STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 0);
4109 /* FEC clock */
4110 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0);
4111 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
4112 goto err;
4113 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
4114 /* sampling 2 clock */
4115 STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 0);
4116 /* viterbi 2 clock */
4117 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 0);
4118 /* TS clock */
4119 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0);
4120 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
4121 goto err;
4122 break;
4123
4124 default:
4125 dprintk(FE_ERROR, 1, "Wrong demodulator!");
4126 break;
4127 }
4128
4129 mutex_unlock(&state->internal->demod_lock);
4130 return 0;
4131err:
4132 mutex_unlock(&state->internal->demod_lock);
4133 dprintk(FE_ERROR, 1, "I/O error");
4134 return -1;
4135}
4136
4137static void stv090x_release(struct dvb_frontend *fe)
4138{
4139 struct stv090x_state *state = fe->demodulator_priv;
4140
4141 state->internal->num_used--;
4142 if (state->internal->num_used <= 0) {
4143
4144 dprintk(FE_ERROR, 1, "Actually removing");
4145
4146 remove_dev(state->internal);
4147 kfree(state->internal);
4148 }
4149
4150 kfree(state);
4151}
4152
4153static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
4154{
4155 u32 reg = 0;
4156
4157 reg = stv090x_read_reg(state, STV090x_GENCFG);
4158
4159 switch (ldpc_mode) {
4160 case STV090x_DUAL:
4161 default:
4162 if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
4163 /* set LDPC to dual mode */
4164 if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0)
4165 goto err;
4166
4167 state->demod_mode = STV090x_DUAL;
4168
4169 reg = stv090x_read_reg(state, STV090x_TSTRES0);
4170 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
4171 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4172 goto err;
4173 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
4174 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4175 goto err;
4176
4177 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
4178 goto err;
4179 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
4180 goto err;
4181 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
4182 goto err;
4183 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
4184 goto err;
4185 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
4186 goto err;
4187 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
4188 goto err;
4189 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
4190 goto err;
4191
4192 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
4193 goto err;
4194 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
4195 goto err;
4196 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
4197 goto err;
4198 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
4199 goto err;
4200 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
4201 goto err;
4202 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
4203 goto err;
4204 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
4205 goto err;
4206
4207 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
4208 goto err;
4209 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
4210 goto err;
4211 }
4212 break;
4213
4214 case STV090x_SINGLE:
4215 if (stv090x_stop_modcod(state) < 0)
4216 goto err;
4217 if (stv090x_activate_modcod_single(state) < 0)
4218 goto err;
4219
4220 if (state->demod == STV090x_DEMODULATOR_1) {
4221 if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
4222 goto err;
4223 } else {
4224 if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
4225 goto err;
4226 }
4227
4228 reg = stv090x_read_reg(state, STV090x_TSTRES0);
4229 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
4230 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4231 goto err;
4232 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
4233 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4234 goto err;
4235
4236 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
4237 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
4238 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
4239 goto err;
4240 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
4241 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
4242 goto err;
4243 break;
4244 }
4245
4246 return 0;
4247err:
4248 dprintk(FE_ERROR, 1, "I/O error");
4249 return -1;
4250}
4251
4252/* return (Hz), clk in Hz*/
4253static u32 stv090x_get_mclk(struct stv090x_state *state)
4254{
4255 const struct stv090x_config *config = state->config;
4256 u32 div, reg;
4257 u8 ratio;
4258
4259 div = stv090x_read_reg(state, STV090x_NCOARSE);
4260 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4261 ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
4262
4263 return (div + 1) * config->xtal / ratio; /* kHz */
4264}
4265
4266static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
4267{
4268 const struct stv090x_config *config = state->config;
4269 u32 reg, div, clk_sel;
4270
4271 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4272 clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
4273
4274 div = ((clk_sel * mclk) / config->xtal) - 1;
4275
4276 reg = stv090x_read_reg(state, STV090x_NCOARSE);
4277 STV090x_SETFIELD(reg, M_DIV_FIELD, div);
4278 if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
4279 goto err;
4280
4281 state->internal->mclk = stv090x_get_mclk(state);
4282
4283 /*Set the DiseqC frequency to 22KHz */
4284 div = state->internal->mclk / 704000;
4285 if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0)
4286 goto err;
4287 if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0)
4288 goto err;
4289
4290 return 0;
4291err:
4292 dprintk(FE_ERROR, 1, "I/O error");
4293 return -1;
4294}
4295
4296static int stv0900_set_tspath(struct stv090x_state *state)
4297{
4298 u32 reg;
4299
4300 if (state->internal->dev_ver >= 0x20) {
4301 switch (state->config->ts1_mode) {
4302 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4303 case STV090x_TSMODE_DVBCI:
4304 switch (state->config->ts2_mode) {
4305 case STV090x_TSMODE_SERIAL_PUNCTURED:
4306 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4307 default:
4308 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
4309 break;
4310
4311 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4312 case STV090x_TSMODE_DVBCI:
4313 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
4314 goto err;
4315 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4316 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4317 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4318 goto err;
4319 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
4320 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4321 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
4322 goto err;
4323 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
4324 goto err;
4325 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
4326 goto err;
4327 break;
4328 }
4329 break;
4330
4331 case STV090x_TSMODE_SERIAL_PUNCTURED:
4332 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4333 default:
4334 switch (state->config->ts2_mode) {
4335 case STV090x_TSMODE_SERIAL_PUNCTURED:
4336 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4337 default:
4338 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
4339 goto err;
4340 break;
4341
4342 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4343 case STV090x_TSMODE_DVBCI:
4344 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
4345 goto err;
4346 break;
4347 }
4348 break;
4349 }
4350 } else {
4351 switch (state->config->ts1_mode) {
4352 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4353 case STV090x_TSMODE_DVBCI:
4354 switch (state->config->ts2_mode) {
4355 case STV090x_TSMODE_SERIAL_PUNCTURED:
4356 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4357 default:
4358 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
4359 break;
4360
4361 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4362 case STV090x_TSMODE_DVBCI:
4363 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16);
4364 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4365 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4366 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4367 goto err;
4368 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4369 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
4370 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4371 goto err;
4372 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
4373 goto err;
4374 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
4375 goto err;
4376 break;
4377 }
4378 break;
4379
4380 case STV090x_TSMODE_SERIAL_PUNCTURED:
4381 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4382 default:
4383 switch (state->config->ts2_mode) {
4384 case STV090x_TSMODE_SERIAL_PUNCTURED:
4385 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4386 default:
4387 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
4388 break;
4389
4390 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4391 case STV090x_TSMODE_DVBCI:
4392 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12);
4393 break;
4394 }
4395 break;
4396 }
4397 }
4398
4399 switch (state->config->ts1_mode) {
4400 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4401 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4402 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4403 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4404 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4405 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4406 goto err;
4407 break;
4408
4409 case STV090x_TSMODE_DVBCI:
4410 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4411 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4412 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4413 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4414 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4415 goto err;
4416 break;
4417
4418 case STV090x_TSMODE_SERIAL_PUNCTURED:
4419 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4420 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4421 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4422 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4423 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4424 goto err;
4425 break;
4426
4427 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4428 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4429 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4430 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4431 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4432 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4433 goto err;
4434 break;
4435
4436 default:
4437 break;
4438 }
4439
4440 switch (state->config->ts2_mode) {
4441 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4442 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4443 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4444 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4445 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4446 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4447 goto err;
4448 break;
4449
4450 case STV090x_TSMODE_DVBCI:
4451 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4452 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4453 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4454 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4455 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4456 goto err;
4457 break;
4458
4459 case STV090x_TSMODE_SERIAL_PUNCTURED:
4460 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4461 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4462 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4463 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4464 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4465 goto err;
4466 break;
4467
4468 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4469 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4470 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4471 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4472 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4473 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4474 goto err;
4475 break;
4476
4477 default:
4478 break;
4479 }
4480
4481 if (state->config->ts1_clk > 0) {
4482 u32 speed;
4483
4484 switch (state->config->ts1_mode) {
4485 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4486 case STV090x_TSMODE_DVBCI:
4487 default:
4488 speed = state->internal->mclk /
4489 (state->config->ts1_clk / 4);
4490 if (speed < 0x08)
4491 speed = 0x08;
4492 if (speed > 0xFF)
4493 speed = 0xFF;
4494 break;
4495 case STV090x_TSMODE_SERIAL_PUNCTURED:
4496 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4497 speed = state->internal->mclk /
4498 (state->config->ts1_clk / 32);
4499 if (speed < 0x20)
4500 speed = 0x20;
4501 if (speed > 0xFF)
4502 speed = 0xFF;
4503 break;
4504 }
4505 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4506 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4507 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4508 goto err;
4509 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
4510 goto err;
4511 }
4512
4513 if (state->config->ts2_clk > 0) {
4514 u32 speed;
4515
4516 switch (state->config->ts2_mode) {
4517 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4518 case STV090x_TSMODE_DVBCI:
4519 default:
4520 speed = state->internal->mclk /
4521 (state->config->ts2_clk / 4);
4522 if (speed < 0x08)
4523 speed = 0x08;
4524 if (speed > 0xFF)
4525 speed = 0xFF;
4526 break;
4527 case STV090x_TSMODE_SERIAL_PUNCTURED:
4528 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4529 speed = state->internal->mclk /
4530 (state->config->ts2_clk / 32);
4531 if (speed < 0x20)
4532 speed = 0x20;
4533 if (speed > 0xFF)
4534 speed = 0xFF;
4535 break;
4536 }
4537 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
4538 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4539 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
4540 goto err;
4541 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0)
4542 goto err;
4543 }
4544
4545 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4546 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4547 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4548 goto err;
4549 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4550 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4551 goto err;
4552
4553 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4554 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4555 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4556 goto err;
4557 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4558 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4559 goto err;
4560
4561 return 0;
4562err:
4563 dprintk(FE_ERROR, 1, "I/O error");
4564 return -1;
4565}
4566
4567static int stv0903_set_tspath(struct stv090x_state *state)
4568{
4569 u32 reg;
4570
4571 if (state->internal->dev_ver >= 0x20) {
4572 switch (state->config->ts1_mode) {
4573 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4574 case STV090x_TSMODE_DVBCI:
4575 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
4576 break;
4577
4578 case STV090x_TSMODE_SERIAL_PUNCTURED:
4579 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4580 default:
4581 stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c);
4582 break;
4583 }
4584 } else {
4585 switch (state->config->ts1_mode) {
4586 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4587 case STV090x_TSMODE_DVBCI:
4588 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
4589 break;
4590
4591 case STV090x_TSMODE_SERIAL_PUNCTURED:
4592 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4593 default:
4594 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
4595 break;
4596 }
4597 }
4598
4599 switch (state->config->ts1_mode) {
4600 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4601 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4602 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4603 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4604 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4605 goto err;
4606 break;
4607
4608 case STV090x_TSMODE_DVBCI:
4609 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4610 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4611 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4612 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4613 goto err;
4614 break;
4615
4616 case STV090x_TSMODE_SERIAL_PUNCTURED:
4617 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4618 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4619 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4620 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4621 goto err;
4622 break;
4623
4624 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4625 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4626 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4627 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4628 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4629 goto err;
4630 break;
4631
4632 default:
4633 break;
4634 }
4635
4636 if (state->config->ts1_clk > 0) {
4637 u32 speed;
4638
4639 switch (state->config->ts1_mode) {
4640 case STV090x_TSMODE_PARALLEL_PUNCTURED:
4641 case STV090x_TSMODE_DVBCI:
4642 default:
4643 speed = state->internal->mclk /
4644 (state->config->ts1_clk / 4);
4645 if (speed < 0x08)
4646 speed = 0x08;
4647 if (speed > 0xFF)
4648 speed = 0xFF;
4649 break;
4650 case STV090x_TSMODE_SERIAL_PUNCTURED:
4651 case STV090x_TSMODE_SERIAL_CONTINUOUS:
4652 speed = state->internal->mclk /
4653 (state->config->ts1_clk / 32);
4654 if (speed < 0x20)
4655 speed = 0x20;
4656 if (speed > 0xFF)
4657 speed = 0xFF;
4658 break;
4659 }
4660 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4661 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4662 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4663 goto err;
4664 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
4665 goto err;
4666 }
4667
4668 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4669 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4670 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4671 goto err;
4672 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4673 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4674 goto err;
4675
4676 return 0;
4677err:
4678 dprintk(FE_ERROR, 1, "I/O error");
4679 return -1;
4680}
4681
4682static int stv090x_init(struct dvb_frontend *fe)
4683{
4684 struct stv090x_state *state = fe->demodulator_priv;
4685 const struct stv090x_config *config = state->config;
4686 u32 reg;
4687
4688 if (state->internal->mclk == 0) {
4689 /* call tuner init to configure the tuner's clock output
4690 divider directly before setting up the master clock of
4691 the stv090x. */
4692 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
4693 goto err;
4694
4695 if (config->tuner_init) {
4696 if (config->tuner_init(fe) < 0)
4697 goto err_gateoff;
4698 }
4699
4700 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
4701 goto err;
4702
4703 stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
4704 msleep(5);
4705 if (stv090x_write_reg(state, STV090x_SYNTCTRL,
4706 0x20 | config->clk_mode) < 0)
4707 goto err;
4708 stv090x_get_mclk(state);
4709 }
4710
4711 if (stv090x_wakeup(fe) < 0) {
4712 dprintk(FE_ERROR, 1, "Error waking device");
4713 goto err;
4714 }
4715
4716 if (stv090x_ldpc_mode(state, state->demod_mode) < 0)
4717 goto err;
4718
4719 reg = STV090x_READ_DEMOD(state, TNRCFG2);
4720 STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
4721 if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
4722 goto err;
4723 reg = STV090x_READ_DEMOD(state, DEMOD);
4724 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
4725 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
4726 goto err;
4727
4728 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
4729 goto err;
4730
4731 if (config->tuner_set_mode) {
4732 if (config->tuner_set_mode(fe, TUNER_WAKE) < 0)
4733 goto err_gateoff;
4734 }
4735
4736 if (config->tuner_init) {
4737 if (config->tuner_init(fe) < 0)
4738 goto err_gateoff;
4739 }
4740
4741 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
4742 goto err;
4743
4744 if (state->device == STV0900) {
4745 if (stv0900_set_tspath(state) < 0)
4746 goto err;
4747 } else {
4748 if (stv0903_set_tspath(state) < 0)
4749 goto err;
4750 }
4751
4752 return 0;
4753
4754err_gateoff:
4755 stv090x_i2c_gate_ctrl(state, 0);
4756err:
4757 dprintk(FE_ERROR, 1, "I/O error");
4758 return -1;
4759}
4760
4761static int stv090x_setup(struct dvb_frontend *fe)
4762{
4763 struct stv090x_state *state = fe->demodulator_priv;
4764 const struct stv090x_config *config = state->config;
4765 const struct stv090x_reg *stv090x_initval = NULL;
4766 const struct stv090x_reg *stv090x_cut20_val = NULL;
4767 unsigned long t1_size = 0, t2_size = 0;
4768 u32 reg = 0;
4769
4770 int i;
4771
4772 if (state->device == STV0900) {
4773 dprintk(FE_DEBUG, 1, "Initializing STV0900");
4774 stv090x_initval = stv0900_initval;
4775 t1_size = ARRAY_SIZE(stv0900_initval);
4776 stv090x_cut20_val = stv0900_cut20_val;
4777 t2_size = ARRAY_SIZE(stv0900_cut20_val);
4778 } else if (state->device == STV0903) {
4779 dprintk(FE_DEBUG, 1, "Initializing STV0903");
4780 stv090x_initval = stv0903_initval;
4781 t1_size = ARRAY_SIZE(stv0903_initval);
4782 stv090x_cut20_val = stv0903_cut20_val;
4783 t2_size = ARRAY_SIZE(stv0903_cut20_val);
4784 }
4785
4786 /* STV090x init */
4787
4788 /* Stop Demod */
4789 if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0)
4790 goto err;
4791 if (state->device == STV0900)
4792 if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0)
4793 goto err;
4794
4795 msleep(5);
4796
4797 /* Set No Tuner Mode */
4798 if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0)
4799 goto err;
4800 if (state->device == STV0900)
4801 if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0)
4802 goto err;
4803
4804 /* I2C repeater OFF */
4805 STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
4806 if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0)
4807 goto err;
4808 if (state->device == STV0900)
4809 if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0)
4810 goto err;
4811
4812 if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
4813 goto err;
4814 msleep(5);
4815 if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
4816 goto err;
4817 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
4818 goto err;
4819 msleep(5);
4820
4821 /* write initval */
4822 dprintk(FE_DEBUG, 1, "Setting up initial values");
4823 for (i = 0; i < t1_size; i++) {
4824 if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
4825 goto err;
4826 }
4827
4828 state->internal->dev_ver = stv090x_read_reg(state, STV090x_MID);
4829 if (state->internal->dev_ver >= 0x20) {
4830 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
4831 goto err;
4832
4833 /* write cut20_val*/
4834 dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
4835 for (i = 0; i < t2_size; i++) {
4836 if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
4837 goto err;
4838 }
4839
4840 } else if (state->internal->dev_ver < 0x20) {
4841 dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!",
4842 state->internal->dev_ver);
4843
4844 goto err;
4845 } else if (state->internal->dev_ver > 0x30) {
4846 /* we shouldn't bail out from here */
4847 dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!",
4848 state->internal->dev_ver);
4849 }
4850
4851 /* ADC1 range */
4852 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
4853 STV090x_SETFIELD(reg, ADC1_INMODE_FIELD,
4854 (config->adc1_range == STV090x_ADC_1Vpp) ? 0 : 1);
4855 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
4856 goto err;
4857
4858 /* ADC2 range */
4859 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
4860 STV090x_SETFIELD(reg, ADC2_INMODE_FIELD,
4861 (config->adc2_range == STV090x_ADC_1Vpp) ? 0 : 1);
4862 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
4863 goto err;
4864
4865 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
4866 goto err;
4867 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
4868 goto err;
4869
4870 return 0;
4871err:
4872 dprintk(FE_ERROR, 1, "I/O error");
4873 return -1;
4874}
4875
4876static int stv090x_set_gpio(struct dvb_frontend *fe, u8 gpio, u8 dir,
4877 u8 value, u8 xor_value)
4878{
4879 struct stv090x_state *state = fe->demodulator_priv;
4880 u8 reg = 0;
4881
4882 STV090x_SETFIELD(reg, GPIOx_OPD_FIELD, dir);
4883 STV090x_SETFIELD(reg, GPIOx_CONFIG_FIELD, value);
4884 STV090x_SETFIELD(reg, GPIOx_XOR_FIELD, xor_value);
4885
4886 return stv090x_write_reg(state, STV090x_GPIOxCFG(gpio), reg);
4887}
4888
4889static const struct dvb_frontend_ops stv090x_ops = {
4890 .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
4891 .info = {
4892 .name = "STV090x Multistandard",
4893 .frequency_min = 950000,
4894 .frequency_max = 2150000,
4895 .frequency_stepsize = 0,
4896 .frequency_tolerance = 0,
4897 .symbol_rate_min = 1000000,
4898 .symbol_rate_max = 45000000,
4899 .caps = FE_CAN_INVERSION_AUTO |
4900 FE_CAN_FEC_AUTO |
4901 FE_CAN_QPSK |
4902 FE_CAN_2G_MODULATION
4903 },
4904
4905 .release = stv090x_release,
4906 .init = stv090x_init,
4907
4908 .sleep = stv090x_sleep,
4909 .get_frontend_algo = stv090x_frontend_algo,
4910
4911 .diseqc_send_master_cmd = stv090x_send_diseqc_msg,
4912 .diseqc_send_burst = stv090x_send_diseqc_burst,
4913 .diseqc_recv_slave_reply = stv090x_recv_slave_reply,
4914 .set_tone = stv090x_set_tone,
4915
4916 .search = stv090x_search,
4917 .read_status = stv090x_read_status,
4918 .read_ber = stv090x_read_per,
4919 .read_signal_strength = stv090x_read_signal_strength,
4920 .read_snr = stv090x_read_cnr,
4921};
4922
4923
4924struct dvb_frontend *stv090x_attach(struct stv090x_config *config,
4925 struct i2c_adapter *i2c,
4926 enum stv090x_demodulator demod)
4927{
4928 struct stv090x_state *state = NULL;
4929 struct stv090x_dev *temp_int;
4930
4931 state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL);
4932 if (state == NULL)
4933 goto error;
4934
4935 state->verbose = &verbose;
4936 state->config = config;
4937 state->i2c = i2c;
4938 state->frontend.ops = stv090x_ops;
4939 state->frontend.demodulator_priv = state;
4940 state->demod = demod;
4941 state->demod_mode = config->demod_mode; /* Single or Dual mode */
4942 state->device = config->device;
4943 state->rolloff = STV090x_RO_35; /* default */
4944
4945 temp_int = find_dev(state->i2c,
4946 state->config->address);
4947
4948 if ((temp_int != NULL) && (state->demod_mode == STV090x_DUAL)) {
4949 state->internal = temp_int->internal;
4950 state->internal->num_used++;
4951 dprintk(FE_INFO, 1, "Found Internal Structure!");
4952 } else {
4953 state->internal = kmalloc(sizeof(struct stv090x_internal),
4954 GFP_KERNEL);
4955 if (!state->internal)
4956 goto error;
4957 temp_int = append_internal(state->internal);
4958 if (!temp_int) {
4959 kfree(state->internal);
4960 goto error;
4961 }
4962 state->internal->num_used = 1;
4963 state->internal->mclk = 0;
4964 state->internal->dev_ver = 0;
4965 state->internal->i2c_adap = state->i2c;
4966 state->internal->i2c_addr = state->config->address;
4967 dprintk(FE_INFO, 1, "Create New Internal Structure!");
4968
4969 mutex_init(&state->internal->demod_lock);
4970 mutex_init(&state->internal->tuner_lock);
4971
4972 if (stv090x_setup(&state->frontend) < 0) {
4973 dprintk(FE_ERROR, 1, "Error setting up device");
4974 goto err_remove;
4975 }
4976 }
4977
4978 if (state->internal->dev_ver >= 0x30)
4979 state->frontend.ops.info.caps |= FE_CAN_MULTISTREAM;
4980
4981 /* workaround for stuck DiSEqC output */
4982 if (config->diseqc_envelope_mode)
4983 stv090x_send_diseqc_burst(&state->frontend, SEC_MINI_A);
4984
4985 config->set_gpio = stv090x_set_gpio;
4986
4987 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x",
4988 state->device == STV0900 ? "STV0900" : "STV0903",
4989 demod,
4990 state->internal->dev_ver);
4991
4992 return &state->frontend;
4993
4994err_remove:
4995 remove_dev(state->internal);
4996 kfree(state->internal);
4997error:
4998 kfree(state);
4999 return NULL;
5000}
5001EXPORT_SYMBOL(stv090x_attach);
5002MODULE_PARM_DESC(verbose, "Set Verbosity level");
5003MODULE_AUTHOR("Manu Abraham");
5004MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
5005MODULE_LICENSE("GPL");