rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * ov2640 Camera Driver |
| 3 | * |
| 4 | * Copyright (C) 2010 Alberto Panizzo <maramaopercheseimorto@gmail.com> |
| 5 | * |
| 6 | * Based on ov772x, ov9640 drivers and previous non merged implementations. |
| 7 | * |
| 8 | * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. |
| 9 | * Copyright (C) 2006, OmniVision |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License version 2 as |
| 13 | * published by the Free Software Foundation. |
| 14 | */ |
| 15 | |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/module.h> |
| 18 | #include <linux/i2c.h> |
| 19 | #include <linux/clk.h> |
| 20 | #include <linux/slab.h> |
| 21 | #include <linux/delay.h> |
| 22 | #include <linux/gpio.h> |
| 23 | #include <linux/gpio/consumer.h> |
| 24 | #include <linux/of_gpio.h> |
| 25 | #include <linux/v4l2-mediabus.h> |
| 26 | #include <linux/videodev2.h> |
| 27 | |
| 28 | #include <media/v4l2-device.h> |
| 29 | #include <media/v4l2-subdev.h> |
| 30 | #include <media/v4l2-ctrls.h> |
| 31 | #include <media/v4l2-image-sizes.h> |
| 32 | |
| 33 | #define VAL_SET(x, mask, rshift, lshift) \ |
| 34 | ((((x) >> rshift) & mask) << lshift) |
| 35 | /* |
| 36 | * DSP registers |
| 37 | * register offset for BANK_SEL == BANK_SEL_DSP |
| 38 | */ |
| 39 | #define R_BYPASS 0x05 /* Bypass DSP */ |
| 40 | #define R_BYPASS_DSP_BYPAS 0x01 /* Bypass DSP, sensor out directly */ |
| 41 | #define R_BYPASS_USE_DSP 0x00 /* Use the internal DSP */ |
| 42 | #define QS 0x44 /* Quantization Scale Factor */ |
| 43 | #define CTRLI 0x50 |
| 44 | #define CTRLI_LP_DP 0x80 |
| 45 | #define CTRLI_ROUND 0x40 |
| 46 | #define CTRLI_V_DIV_SET(x) VAL_SET(x, 0x3, 0, 3) |
| 47 | #define CTRLI_H_DIV_SET(x) VAL_SET(x, 0x3, 0, 0) |
| 48 | #define HSIZE 0x51 /* H_SIZE[7:0] (real/4) */ |
| 49 | #define HSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) |
| 50 | #define VSIZE 0x52 /* V_SIZE[7:0] (real/4) */ |
| 51 | #define VSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0) |
| 52 | #define XOFFL 0x53 /* OFFSET_X[7:0] */ |
| 53 | #define XOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) |
| 54 | #define YOFFL 0x54 /* OFFSET_Y[7:0] */ |
| 55 | #define YOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0) |
| 56 | #define VHYX 0x55 /* Offset and size completion */ |
| 57 | #define VHYX_VSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 7) |
| 58 | #define VHYX_HSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 3) |
| 59 | #define VHYX_YOFF_SET(x) VAL_SET(x, 0x3, 8, 4) |
| 60 | #define VHYX_XOFF_SET(x) VAL_SET(x, 0x3, 8, 0) |
| 61 | #define DPRP 0x56 |
| 62 | #define TEST 0x57 /* Horizontal size completion */ |
| 63 | #define TEST_HSIZE_SET(x) VAL_SET(x, 0x1, (9+2), 7) |
| 64 | #define ZMOW 0x5A /* Zoom: Out Width OUTW[7:0] (real/4) */ |
| 65 | #define ZMOW_OUTW_SET(x) VAL_SET(x, 0xFF, 2, 0) |
| 66 | #define ZMOH 0x5B /* Zoom: Out Height OUTH[7:0] (real/4) */ |
| 67 | #define ZMOH_OUTH_SET(x) VAL_SET(x, 0xFF, 2, 0) |
| 68 | #define ZMHH 0x5C /* Zoom: Speed and H&W completion */ |
| 69 | #define ZMHH_ZSPEED_SET(x) VAL_SET(x, 0x0F, 0, 4) |
| 70 | #define ZMHH_OUTH_SET(x) VAL_SET(x, 0x1, (8+2), 2) |
| 71 | #define ZMHH_OUTW_SET(x) VAL_SET(x, 0x3, (8+2), 0) |
| 72 | #define BPADDR 0x7C /* SDE Indirect Register Access: Address */ |
| 73 | #define BPDATA 0x7D /* SDE Indirect Register Access: Data */ |
| 74 | #define CTRL2 0x86 /* DSP Module enable 2 */ |
| 75 | #define CTRL2_DCW_EN 0x20 |
| 76 | #define CTRL2_SDE_EN 0x10 |
| 77 | #define CTRL2_UV_ADJ_EN 0x08 |
| 78 | #define CTRL2_UV_AVG_EN 0x04 |
| 79 | #define CTRL2_CMX_EN 0x01 |
| 80 | #define CTRL3 0x87 /* DSP Module enable 3 */ |
| 81 | #define CTRL3_BPC_EN 0x80 |
| 82 | #define CTRL3_WPC_EN 0x40 |
| 83 | #define SIZEL 0x8C /* Image Size Completion */ |
| 84 | #define SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6) |
| 85 | #define SIZEL_HSIZE8_SET(x) VAL_SET(x, 0x7, 0, 3) |
| 86 | #define SIZEL_VSIZE8_SET(x) VAL_SET(x, 0x7, 0, 0) |
| 87 | #define HSIZE8 0xC0 /* Image Horizontal Size HSIZE[10:3] */ |
| 88 | #define HSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) |
| 89 | #define VSIZE8 0xC1 /* Image Vertical Size VSIZE[10:3] */ |
| 90 | #define VSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0) |
| 91 | #define CTRL0 0xC2 /* DSP Module enable 0 */ |
| 92 | #define CTRL0_AEC_EN 0x80 |
| 93 | #define CTRL0_AEC_SEL 0x40 |
| 94 | #define CTRL0_STAT_SEL 0x20 |
| 95 | #define CTRL0_VFIRST 0x10 |
| 96 | #define CTRL0_YUV422 0x08 |
| 97 | #define CTRL0_YUV_EN 0x04 |
| 98 | #define CTRL0_RGB_EN 0x02 |
| 99 | #define CTRL0_RAW_EN 0x01 |
| 100 | #define CTRL1 0xC3 /* DSP Module enable 1 */ |
| 101 | #define CTRL1_CIP 0x80 |
| 102 | #define CTRL1_DMY 0x40 |
| 103 | #define CTRL1_RAW_GMA 0x20 |
| 104 | #define CTRL1_DG 0x10 |
| 105 | #define CTRL1_AWB 0x08 |
| 106 | #define CTRL1_AWB_GAIN 0x04 |
| 107 | #define CTRL1_LENC 0x02 |
| 108 | #define CTRL1_PRE 0x01 |
| 109 | /* REG 0xC7 (unknown name): affects Auto White Balance (AWB) |
| 110 | * AWB_OFF 0x40 |
| 111 | * AWB_SIMPLE 0x10 |
| 112 | * AWB_ON 0x00 (Advanced AWB ?) */ |
| 113 | #define R_DVP_SP 0xD3 /* DVP output speed control */ |
| 114 | #define R_DVP_SP_AUTO_MODE 0x80 |
| 115 | #define R_DVP_SP_DVP_MASK 0x3F /* DVP PCLK = sysclk (48)/[6:0] (YUV0); |
| 116 | * = sysclk (48)/(2*[6:0]) (RAW);*/ |
| 117 | #define IMAGE_MODE 0xDA /* Image Output Format Select */ |
| 118 | #define IMAGE_MODE_Y8_DVP_EN 0x40 |
| 119 | #define IMAGE_MODE_JPEG_EN 0x10 |
| 120 | #define IMAGE_MODE_YUV422 0x00 |
| 121 | #define IMAGE_MODE_RAW10 0x04 /* (DVP) */ |
| 122 | #define IMAGE_MODE_RGB565 0x08 |
| 123 | #define IMAGE_MODE_HREF_VSYNC 0x02 /* HREF timing select in DVP JPEG output |
| 124 | * mode (0 for HREF is same as sensor) */ |
| 125 | #define IMAGE_MODE_LBYTE_FIRST 0x01 /* Byte swap enable for DVP |
| 126 | * 1: Low byte first UYVY (C2[4] =0) |
| 127 | * VYUY (C2[4] =1) |
| 128 | * 0: High byte first YUYV (C2[4]=0) |
| 129 | * YVYU (C2[4] = 1) */ |
| 130 | #define RESET 0xE0 /* Reset */ |
| 131 | #define RESET_MICROC 0x40 |
| 132 | #define RESET_SCCB 0x20 |
| 133 | #define RESET_JPEG 0x10 |
| 134 | #define RESET_DVP 0x04 |
| 135 | #define RESET_IPU 0x02 |
| 136 | #define RESET_CIF 0x01 |
| 137 | #define REGED 0xED /* Register ED */ |
| 138 | #define REGED_CLK_OUT_DIS 0x10 |
| 139 | #define MS_SP 0xF0 /* SCCB Master Speed */ |
| 140 | #define SS_ID 0xF7 /* SCCB Slave ID */ |
| 141 | #define SS_CTRL 0xF8 /* SCCB Slave Control */ |
| 142 | #define SS_CTRL_ADD_AUTO_INC 0x20 |
| 143 | #define SS_CTRL_EN 0x08 |
| 144 | #define SS_CTRL_DELAY_CLK 0x04 |
| 145 | #define SS_CTRL_ACC_EN 0x02 |
| 146 | #define SS_CTRL_SEN_PASS_THR 0x01 |
| 147 | #define MC_BIST 0xF9 /* Microcontroller misc register */ |
| 148 | #define MC_BIST_RESET 0x80 /* Microcontroller Reset */ |
| 149 | #define MC_BIST_BOOT_ROM_SEL 0x40 |
| 150 | #define MC_BIST_12KB_SEL 0x20 |
| 151 | #define MC_BIST_12KB_MASK 0x30 |
| 152 | #define MC_BIST_512KB_SEL 0x08 |
| 153 | #define MC_BIST_512KB_MASK 0x0C |
| 154 | #define MC_BIST_BUSY_BIT_R 0x02 |
| 155 | #define MC_BIST_MC_RES_ONE_SH_W 0x02 |
| 156 | #define MC_BIST_LAUNCH 0x01 |
| 157 | #define BANK_SEL 0xFF /* Register Bank Select */ |
| 158 | #define BANK_SEL_DSP 0x00 |
| 159 | #define BANK_SEL_SENS 0x01 |
| 160 | |
| 161 | /* |
| 162 | * Sensor registers |
| 163 | * register offset for BANK_SEL == BANK_SEL_SENS |
| 164 | */ |
| 165 | #define GAIN 0x00 /* AGC - Gain control gain setting */ |
| 166 | #define COM1 0x03 /* Common control 1 */ |
| 167 | #define COM1_1_DUMMY_FR 0x40 |
| 168 | #define COM1_3_DUMMY_FR 0x80 |
| 169 | #define COM1_7_DUMMY_FR 0xC0 |
| 170 | #define COM1_VWIN_LSB_UXGA 0x0F |
| 171 | #define COM1_VWIN_LSB_SVGA 0x0A |
| 172 | #define COM1_VWIN_LSB_CIF 0x06 |
| 173 | #define REG04 0x04 /* Register 04 */ |
| 174 | #define REG04_DEF 0x20 /* Always set */ |
| 175 | #define REG04_HFLIP_IMG 0x80 /* Horizontal mirror image ON/OFF */ |
| 176 | #define REG04_VFLIP_IMG 0x40 /* Vertical flip image ON/OFF */ |
| 177 | #define REG04_VREF_EN 0x10 |
| 178 | #define REG04_HREF_EN 0x08 |
| 179 | #define REG04_AEC_SET(x) VAL_SET(x, 0x3, 0, 0) |
| 180 | #define REG08 0x08 /* Frame Exposure One-pin Control Pre-charge Row Num */ |
| 181 | #define COM2 0x09 /* Common control 2 */ |
| 182 | #define COM2_SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */ |
| 183 | /* Output drive capability */ |
| 184 | #define COM2_OCAP_Nx_SET(N) (((N) - 1) & 0x03) /* N = [1x .. 4x] */ |
| 185 | #define PID 0x0A /* Product ID Number MSB */ |
| 186 | #define VER 0x0B /* Product ID Number LSB */ |
| 187 | #define COM3 0x0C /* Common control 3 */ |
| 188 | #define COM3_BAND_50H 0x04 /* 0 For Banding at 60H */ |
| 189 | #define COM3_BAND_AUTO 0x02 /* Auto Banding */ |
| 190 | #define COM3_SING_FR_SNAPSH 0x01 /* 0 For enable live video output after the |
| 191 | * snapshot sequence*/ |
| 192 | #define AEC 0x10 /* AEC[9:2] Exposure Value */ |
| 193 | #define CLKRC 0x11 /* Internal clock */ |
| 194 | #define CLKRC_EN 0x80 |
| 195 | #define CLKRC_DIV_SET(x) (((x) - 1) & 0x1F) /* CLK = XVCLK/(x) */ |
| 196 | #define COM7 0x12 /* Common control 7 */ |
| 197 | #define COM7_SRST 0x80 /* Initiates system reset. All registers are |
| 198 | * set to factory default values after which |
| 199 | * the chip resumes normal operation */ |
| 200 | #define COM7_RES_UXGA 0x00 /* Resolution selectors for UXGA */ |
| 201 | #define COM7_RES_SVGA 0x40 /* SVGA */ |
| 202 | #define COM7_RES_CIF 0x20 /* CIF */ |
| 203 | #define COM7_ZOOM_EN 0x04 /* Enable Zoom mode */ |
| 204 | #define COM7_COLOR_BAR_TEST 0x02 /* Enable Color Bar Test Pattern */ |
| 205 | #define COM8 0x13 /* Common control 8 */ |
| 206 | #define COM8_DEF 0xC0 |
| 207 | #define COM8_BNDF_EN 0x20 /* Banding filter ON/OFF */ |
| 208 | #define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */ |
| 209 | #define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */ |
| 210 | #define COM9 0x14 /* Common control 9 |
| 211 | * Automatic gain ceiling - maximum AGC value [7:5]*/ |
| 212 | #define COM9_AGC_GAIN_2x 0x00 /* 000 : 2x */ |
| 213 | #define COM9_AGC_GAIN_4x 0x20 /* 001 : 4x */ |
| 214 | #define COM9_AGC_GAIN_8x 0x40 /* 010 : 8x */ |
| 215 | #define COM9_AGC_GAIN_16x 0x60 /* 011 : 16x */ |
| 216 | #define COM9_AGC_GAIN_32x 0x80 /* 100 : 32x */ |
| 217 | #define COM9_AGC_GAIN_64x 0xA0 /* 101 : 64x */ |
| 218 | #define COM9_AGC_GAIN_128x 0xC0 /* 110 : 128x */ |
| 219 | #define COM10 0x15 /* Common control 10 */ |
| 220 | #define COM10_PCLK_HREF 0x20 /* PCLK output qualified by HREF */ |
| 221 | #define COM10_PCLK_RISE 0x10 /* Data is updated at the rising edge of |
| 222 | * PCLK (user can latch data at the next |
| 223 | * falling edge of PCLK). |
| 224 | * 0 otherwise. */ |
| 225 | #define COM10_HREF_INV 0x08 /* Invert HREF polarity: |
| 226 | * HREF negative for valid data*/ |
| 227 | #define COM10_VSINC_INV 0x02 /* Invert VSYNC polarity */ |
| 228 | #define HSTART 0x17 /* Horizontal Window start MSB 8 bit */ |
| 229 | #define HEND 0x18 /* Horizontal Window end MSB 8 bit */ |
| 230 | #define VSTART 0x19 /* Vertical Window start MSB 8 bit */ |
| 231 | #define VEND 0x1A /* Vertical Window end MSB 8 bit */ |
| 232 | #define MIDH 0x1C /* Manufacturer ID byte - high */ |
| 233 | #define MIDL 0x1D /* Manufacturer ID byte - low */ |
| 234 | #define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */ |
| 235 | #define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */ |
| 236 | #define VV 0x26 /* AGC/AEC Fast mode operating region */ |
| 237 | #define VV_HIGH_TH_SET(x) VAL_SET(x, 0xF, 0, 4) |
| 238 | #define VV_LOW_TH_SET(x) VAL_SET(x, 0xF, 0, 0) |
| 239 | #define REG2A 0x2A /* Dummy pixel insert MSB */ |
| 240 | #define FRARL 0x2B /* Dummy pixel insert LSB */ |
| 241 | #define ADDVFL 0x2D /* LSB of insert dummy lines in Vertical direction */ |
| 242 | #define ADDVFH 0x2E /* MSB of insert dummy lines in Vertical direction */ |
| 243 | #define YAVG 0x2F /* Y/G Channel Average value */ |
| 244 | #define REG32 0x32 /* Common Control 32 */ |
| 245 | #define REG32_PCLK_DIV_2 0x80 /* PCLK freq divided by 2 */ |
| 246 | #define REG32_PCLK_DIV_4 0xC0 /* PCLK freq divided by 4 */ |
| 247 | #define ARCOM2 0x34 /* Zoom: Horizontal start point */ |
| 248 | #define REG45 0x45 /* Register 45 */ |
| 249 | #define FLL 0x46 /* Frame Length Adjustment LSBs */ |
| 250 | #define FLH 0x47 /* Frame Length Adjustment MSBs */ |
| 251 | #define COM19 0x48 /* Zoom: Vertical start point */ |
| 252 | #define ZOOMS 0x49 /* Zoom: Vertical start point */ |
| 253 | #define COM22 0x4B /* Flash light control */ |
| 254 | #define COM25 0x4E /* For Banding operations */ |
| 255 | #define COM25_50HZ_BANDING_AEC_MSBS_MASK 0xC0 /* 50Hz Bd. AEC 2 MSBs */ |
| 256 | #define COM25_60HZ_BANDING_AEC_MSBS_MASK 0x30 /* 60Hz Bd. AEC 2 MSBs */ |
| 257 | #define COM25_50HZ_BANDING_AEC_MSBS_SET(x) VAL_SET(x, 0x3, 8, 6) |
| 258 | #define COM25_60HZ_BANDING_AEC_MSBS_SET(x) VAL_SET(x, 0x3, 8, 4) |
| 259 | #define BD50 0x4F /* 50Hz Banding AEC 8 LSBs */ |
| 260 | #define BD50_50HZ_BANDING_AEC_LSBS_SET(x) VAL_SET(x, 0xFF, 0, 0) |
| 261 | #define BD60 0x50 /* 60Hz Banding AEC 8 LSBs */ |
| 262 | #define BD60_60HZ_BANDING_AEC_LSBS_SET(x) VAL_SET(x, 0xFF, 0, 0) |
| 263 | #define REG5A 0x5A /* 50/60Hz Banding Maximum AEC Step */ |
| 264 | #define BD50_MAX_AEC_STEP_MASK 0xF0 /* 50Hz Banding Max. AEC Step */ |
| 265 | #define BD60_MAX_AEC_STEP_MASK 0x0F /* 60Hz Banding Max. AEC Step */ |
| 266 | #define BD50_MAX_AEC_STEP_SET(x) VAL_SET((x - 1), 0x0F, 0, 4) |
| 267 | #define BD60_MAX_AEC_STEP_SET(x) VAL_SET((x - 1), 0x0F, 0, 0) |
| 268 | #define REG5D 0x5D /* AVGsel[7:0], 16-zone average weight option */ |
| 269 | #define REG5E 0x5E /* AVGsel[15:8], 16-zone average weight option */ |
| 270 | #define REG5F 0x5F /* AVGsel[23:16], 16-zone average weight option */ |
| 271 | #define REG60 0x60 /* AVGsel[31:24], 16-zone average weight option */ |
| 272 | #define HISTO_LOW 0x61 /* Histogram Algorithm Low Level */ |
| 273 | #define HISTO_HIGH 0x62 /* Histogram Algorithm High Level */ |
| 274 | |
| 275 | /* |
| 276 | * ID |
| 277 | */ |
| 278 | #define MANUFACTURER_ID 0x7FA2 |
| 279 | #define PID_OV2640 0x2642 |
| 280 | #define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF)) |
| 281 | |
| 282 | /* |
| 283 | * Struct |
| 284 | */ |
| 285 | struct regval_list { |
| 286 | u8 reg_num; |
| 287 | u8 value; |
| 288 | }; |
| 289 | |
| 290 | struct ov2640_win_size { |
| 291 | char *name; |
| 292 | u32 width; |
| 293 | u32 height; |
| 294 | const struct regval_list *regs; |
| 295 | }; |
| 296 | |
| 297 | |
| 298 | struct ov2640_priv { |
| 299 | struct v4l2_subdev subdev; |
| 300 | #if defined(CONFIG_MEDIA_CONTROLLER) |
| 301 | struct media_pad pad; |
| 302 | #endif |
| 303 | struct v4l2_ctrl_handler hdl; |
| 304 | u32 cfmt_code; |
| 305 | struct clk *clk; |
| 306 | const struct ov2640_win_size *win; |
| 307 | |
| 308 | struct gpio_desc *resetb_gpio; |
| 309 | struct gpio_desc *pwdn_gpio; |
| 310 | }; |
| 311 | |
| 312 | /* |
| 313 | * Registers settings |
| 314 | */ |
| 315 | |
| 316 | #define ENDMARKER { 0xff, 0xff } |
| 317 | |
| 318 | static const struct regval_list ov2640_init_regs[] = { |
| 319 | { BANK_SEL, BANK_SEL_DSP }, |
| 320 | { 0x2c, 0xff }, |
| 321 | { 0x2e, 0xdf }, |
| 322 | { BANK_SEL, BANK_SEL_SENS }, |
| 323 | { 0x3c, 0x32 }, |
| 324 | { CLKRC, CLKRC_DIV_SET(1) }, |
| 325 | { COM2, COM2_OCAP_Nx_SET(3) }, |
| 326 | { REG04, REG04_DEF | REG04_HREF_EN }, |
| 327 | { COM8, COM8_DEF | COM8_BNDF_EN | COM8_AGC_EN | COM8_AEC_EN }, |
| 328 | { COM9, COM9_AGC_GAIN_8x | 0x08}, |
| 329 | { 0x2c, 0x0c }, |
| 330 | { 0x33, 0x78 }, |
| 331 | { 0x3a, 0x33 }, |
| 332 | { 0x3b, 0xfb }, |
| 333 | { 0x3e, 0x00 }, |
| 334 | { 0x43, 0x11 }, |
| 335 | { 0x16, 0x10 }, |
| 336 | { 0x39, 0x02 }, |
| 337 | { 0x35, 0x88 }, |
| 338 | { 0x22, 0x0a }, |
| 339 | { 0x37, 0x40 }, |
| 340 | { 0x23, 0x00 }, |
| 341 | { ARCOM2, 0xa0 }, |
| 342 | { 0x06, 0x02 }, |
| 343 | { 0x06, 0x88 }, |
| 344 | { 0x07, 0xc0 }, |
| 345 | { 0x0d, 0xb7 }, |
| 346 | { 0x0e, 0x01 }, |
| 347 | { 0x4c, 0x00 }, |
| 348 | { 0x4a, 0x81 }, |
| 349 | { 0x21, 0x99 }, |
| 350 | { AEW, 0x40 }, |
| 351 | { AEB, 0x38 }, |
| 352 | { VV, VV_HIGH_TH_SET(0x08) | VV_LOW_TH_SET(0x02) }, |
| 353 | { 0x5c, 0x00 }, |
| 354 | { 0x63, 0x00 }, |
| 355 | { FLL, 0x22 }, |
| 356 | { COM3, 0x38 | COM3_BAND_AUTO }, |
| 357 | { REG5D, 0x55 }, |
| 358 | { REG5E, 0x7d }, |
| 359 | { REG5F, 0x7d }, |
| 360 | { REG60, 0x55 }, |
| 361 | { HISTO_LOW, 0x70 }, |
| 362 | { HISTO_HIGH, 0x80 }, |
| 363 | { 0x7c, 0x05 }, |
| 364 | { 0x20, 0x80 }, |
| 365 | { 0x28, 0x30 }, |
| 366 | { 0x6c, 0x00 }, |
| 367 | { 0x6d, 0x80 }, |
| 368 | { 0x6e, 0x00 }, |
| 369 | { 0x70, 0x02 }, |
| 370 | { 0x71, 0x94 }, |
| 371 | { 0x73, 0xc1 }, |
| 372 | { 0x3d, 0x34 }, |
| 373 | { COM7, COM7_RES_UXGA | COM7_ZOOM_EN }, |
| 374 | { REG5A, BD50_MAX_AEC_STEP_SET(6) |
| 375 | | BD60_MAX_AEC_STEP_SET(8) }, /* 0x57 */ |
| 376 | { COM25, COM25_50HZ_BANDING_AEC_MSBS_SET(0x0bb) |
| 377 | | COM25_60HZ_BANDING_AEC_MSBS_SET(0x09c) }, /* 0x00 */ |
| 378 | { BD50, BD50_50HZ_BANDING_AEC_LSBS_SET(0x0bb) }, /* 0xbb */ |
| 379 | { BD60, BD60_60HZ_BANDING_AEC_LSBS_SET(0x09c) }, /* 0x9c */ |
| 380 | { BANK_SEL, BANK_SEL_DSP }, |
| 381 | { 0xe5, 0x7f }, |
| 382 | { MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL }, |
| 383 | { 0x41, 0x24 }, |
| 384 | { RESET, RESET_JPEG | RESET_DVP }, |
| 385 | { 0x76, 0xff }, |
| 386 | { 0x33, 0xa0 }, |
| 387 | { 0x42, 0x20 }, |
| 388 | { 0x43, 0x18 }, |
| 389 | { 0x4c, 0x00 }, |
| 390 | { CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 }, |
| 391 | { 0x88, 0x3f }, |
| 392 | { 0xd7, 0x03 }, |
| 393 | { 0xd9, 0x10 }, |
| 394 | { R_DVP_SP, R_DVP_SP_AUTO_MODE | 0x2 }, |
| 395 | { 0xc8, 0x08 }, |
| 396 | { 0xc9, 0x80 }, |
| 397 | { BPADDR, 0x00 }, |
| 398 | { BPDATA, 0x00 }, |
| 399 | { BPADDR, 0x03 }, |
| 400 | { BPDATA, 0x48 }, |
| 401 | { BPDATA, 0x48 }, |
| 402 | { BPADDR, 0x08 }, |
| 403 | { BPDATA, 0x20 }, |
| 404 | { BPDATA, 0x10 }, |
| 405 | { BPDATA, 0x0e }, |
| 406 | { 0x90, 0x00 }, |
| 407 | { 0x91, 0x0e }, |
| 408 | { 0x91, 0x1a }, |
| 409 | { 0x91, 0x31 }, |
| 410 | { 0x91, 0x5a }, |
| 411 | { 0x91, 0x69 }, |
| 412 | { 0x91, 0x75 }, |
| 413 | { 0x91, 0x7e }, |
| 414 | { 0x91, 0x88 }, |
| 415 | { 0x91, 0x8f }, |
| 416 | { 0x91, 0x96 }, |
| 417 | { 0x91, 0xa3 }, |
| 418 | { 0x91, 0xaf }, |
| 419 | { 0x91, 0xc4 }, |
| 420 | { 0x91, 0xd7 }, |
| 421 | { 0x91, 0xe8 }, |
| 422 | { 0x91, 0x20 }, |
| 423 | { 0x92, 0x00 }, |
| 424 | { 0x93, 0x06 }, |
| 425 | { 0x93, 0xe3 }, |
| 426 | { 0x93, 0x03 }, |
| 427 | { 0x93, 0x03 }, |
| 428 | { 0x93, 0x00 }, |
| 429 | { 0x93, 0x02 }, |
| 430 | { 0x93, 0x00 }, |
| 431 | { 0x93, 0x00 }, |
| 432 | { 0x93, 0x00 }, |
| 433 | { 0x93, 0x00 }, |
| 434 | { 0x93, 0x00 }, |
| 435 | { 0x93, 0x00 }, |
| 436 | { 0x93, 0x00 }, |
| 437 | { 0x96, 0x00 }, |
| 438 | { 0x97, 0x08 }, |
| 439 | { 0x97, 0x19 }, |
| 440 | { 0x97, 0x02 }, |
| 441 | { 0x97, 0x0c }, |
| 442 | { 0x97, 0x24 }, |
| 443 | { 0x97, 0x30 }, |
| 444 | { 0x97, 0x28 }, |
| 445 | { 0x97, 0x26 }, |
| 446 | { 0x97, 0x02 }, |
| 447 | { 0x97, 0x98 }, |
| 448 | { 0x97, 0x80 }, |
| 449 | { 0x97, 0x00 }, |
| 450 | { 0x97, 0x00 }, |
| 451 | { 0xa4, 0x00 }, |
| 452 | { 0xa8, 0x00 }, |
| 453 | { 0xc5, 0x11 }, |
| 454 | { 0xc6, 0x51 }, |
| 455 | { 0xbf, 0x80 }, |
| 456 | { 0xc7, 0x10 }, /* simple AWB */ |
| 457 | { 0xb6, 0x66 }, |
| 458 | { 0xb8, 0xA5 }, |
| 459 | { 0xb7, 0x64 }, |
| 460 | { 0xb9, 0x7C }, |
| 461 | { 0xb3, 0xaf }, |
| 462 | { 0xb4, 0x97 }, |
| 463 | { 0xb5, 0xFF }, |
| 464 | { 0xb0, 0xC5 }, |
| 465 | { 0xb1, 0x94 }, |
| 466 | { 0xb2, 0x0f }, |
| 467 | { 0xc4, 0x5c }, |
| 468 | { 0xa6, 0x00 }, |
| 469 | { 0xa7, 0x20 }, |
| 470 | { 0xa7, 0xd8 }, |
| 471 | { 0xa7, 0x1b }, |
| 472 | { 0xa7, 0x31 }, |
| 473 | { 0xa7, 0x00 }, |
| 474 | { 0xa7, 0x18 }, |
| 475 | { 0xa7, 0x20 }, |
| 476 | { 0xa7, 0xd8 }, |
| 477 | { 0xa7, 0x19 }, |
| 478 | { 0xa7, 0x31 }, |
| 479 | { 0xa7, 0x00 }, |
| 480 | { 0xa7, 0x18 }, |
| 481 | { 0xa7, 0x20 }, |
| 482 | { 0xa7, 0xd8 }, |
| 483 | { 0xa7, 0x19 }, |
| 484 | { 0xa7, 0x31 }, |
| 485 | { 0xa7, 0x00 }, |
| 486 | { 0xa7, 0x18 }, |
| 487 | { 0x7f, 0x00 }, |
| 488 | { 0xe5, 0x1f }, |
| 489 | { 0xe1, 0x77 }, |
| 490 | { 0xdd, 0x7f }, |
| 491 | { CTRL0, CTRL0_YUV422 | CTRL0_YUV_EN | CTRL0_RGB_EN }, |
| 492 | ENDMARKER, |
| 493 | }; |
| 494 | |
| 495 | /* |
| 496 | * Register settings for window size |
| 497 | * The preamble, setup the internal DSP to input an UXGA (1600x1200) image. |
| 498 | * Then the different zooming configurations will setup the output image size. |
| 499 | */ |
| 500 | static const struct regval_list ov2640_size_change_preamble_regs[] = { |
| 501 | { BANK_SEL, BANK_SEL_DSP }, |
| 502 | { RESET, RESET_DVP }, |
| 503 | { SIZEL, SIZEL_HSIZE8_11_SET(UXGA_WIDTH) | |
| 504 | SIZEL_HSIZE8_SET(UXGA_WIDTH) | |
| 505 | SIZEL_VSIZE8_SET(UXGA_HEIGHT) }, |
| 506 | { HSIZE8, HSIZE8_SET(UXGA_WIDTH) }, |
| 507 | { VSIZE8, VSIZE8_SET(UXGA_HEIGHT) }, |
| 508 | { CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN | |
| 509 | CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN }, |
| 510 | { HSIZE, HSIZE_SET(UXGA_WIDTH) }, |
| 511 | { VSIZE, VSIZE_SET(UXGA_HEIGHT) }, |
| 512 | { XOFFL, XOFFL_SET(0) }, |
| 513 | { YOFFL, YOFFL_SET(0) }, |
| 514 | { VHYX, VHYX_HSIZE_SET(UXGA_WIDTH) | VHYX_VSIZE_SET(UXGA_HEIGHT) | |
| 515 | VHYX_XOFF_SET(0) | VHYX_YOFF_SET(0)}, |
| 516 | { TEST, TEST_HSIZE_SET(UXGA_WIDTH) }, |
| 517 | ENDMARKER, |
| 518 | }; |
| 519 | |
| 520 | #define PER_SIZE_REG_SEQ(x, y, v_div, h_div, pclk_div) \ |
| 521 | { CTRLI, CTRLI_LP_DP | CTRLI_V_DIV_SET(v_div) | \ |
| 522 | CTRLI_H_DIV_SET(h_div)}, \ |
| 523 | { ZMOW, ZMOW_OUTW_SET(x) }, \ |
| 524 | { ZMOH, ZMOH_OUTH_SET(y) }, \ |
| 525 | { ZMHH, ZMHH_OUTW_SET(x) | ZMHH_OUTH_SET(y) }, \ |
| 526 | { R_DVP_SP, pclk_div }, \ |
| 527 | { RESET, 0x00} |
| 528 | |
| 529 | static const struct regval_list ov2640_qcif_regs[] = { |
| 530 | PER_SIZE_REG_SEQ(QCIF_WIDTH, QCIF_HEIGHT, 3, 3, 4), |
| 531 | ENDMARKER, |
| 532 | }; |
| 533 | |
| 534 | static const struct regval_list ov2640_qvga_regs[] = { |
| 535 | PER_SIZE_REG_SEQ(QVGA_WIDTH, QVGA_HEIGHT, 2, 2, 4), |
| 536 | ENDMARKER, |
| 537 | }; |
| 538 | |
| 539 | static const struct regval_list ov2640_cif_regs[] = { |
| 540 | PER_SIZE_REG_SEQ(CIF_WIDTH, CIF_HEIGHT, 2, 2, 8), |
| 541 | ENDMARKER, |
| 542 | }; |
| 543 | |
| 544 | static const struct regval_list ov2640_vga_regs[] = { |
| 545 | PER_SIZE_REG_SEQ(VGA_WIDTH, VGA_HEIGHT, 0, 0, 2), |
| 546 | ENDMARKER, |
| 547 | }; |
| 548 | |
| 549 | static const struct regval_list ov2640_svga_regs[] = { |
| 550 | PER_SIZE_REG_SEQ(SVGA_WIDTH, SVGA_HEIGHT, 1, 1, 2), |
| 551 | ENDMARKER, |
| 552 | }; |
| 553 | |
| 554 | static const struct regval_list ov2640_xga_regs[] = { |
| 555 | PER_SIZE_REG_SEQ(XGA_WIDTH, XGA_HEIGHT, 0, 0, 2), |
| 556 | { CTRLI, 0x00}, |
| 557 | ENDMARKER, |
| 558 | }; |
| 559 | |
| 560 | static const struct regval_list ov2640_sxga_regs[] = { |
| 561 | PER_SIZE_REG_SEQ(SXGA_WIDTH, SXGA_HEIGHT, 0, 0, 2), |
| 562 | { CTRLI, 0x00}, |
| 563 | { R_DVP_SP, 2 | R_DVP_SP_AUTO_MODE }, |
| 564 | ENDMARKER, |
| 565 | }; |
| 566 | |
| 567 | static const struct regval_list ov2640_uxga_regs[] = { |
| 568 | PER_SIZE_REG_SEQ(UXGA_WIDTH, UXGA_HEIGHT, 0, 0, 0), |
| 569 | { CTRLI, 0x00}, |
| 570 | { R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE }, |
| 571 | ENDMARKER, |
| 572 | }; |
| 573 | |
| 574 | #define OV2640_SIZE(n, w, h, r) \ |
| 575 | {.name = n, .width = w , .height = h, .regs = r } |
| 576 | |
| 577 | static const struct ov2640_win_size ov2640_supported_win_sizes[] = { |
| 578 | OV2640_SIZE("QCIF", QCIF_WIDTH, QCIF_HEIGHT, ov2640_qcif_regs), |
| 579 | OV2640_SIZE("QVGA", QVGA_WIDTH, QVGA_HEIGHT, ov2640_qvga_regs), |
| 580 | OV2640_SIZE("CIF", CIF_WIDTH, CIF_HEIGHT, ov2640_cif_regs), |
| 581 | OV2640_SIZE("VGA", VGA_WIDTH, VGA_HEIGHT, ov2640_vga_regs), |
| 582 | OV2640_SIZE("SVGA", SVGA_WIDTH, SVGA_HEIGHT, ov2640_svga_regs), |
| 583 | OV2640_SIZE("XGA", XGA_WIDTH, XGA_HEIGHT, ov2640_xga_regs), |
| 584 | OV2640_SIZE("SXGA", SXGA_WIDTH, SXGA_HEIGHT, ov2640_sxga_regs), |
| 585 | OV2640_SIZE("UXGA", UXGA_WIDTH, UXGA_HEIGHT, ov2640_uxga_regs), |
| 586 | }; |
| 587 | |
| 588 | /* |
| 589 | * Register settings for pixel formats |
| 590 | */ |
| 591 | static const struct regval_list ov2640_format_change_preamble_regs[] = { |
| 592 | { BANK_SEL, BANK_SEL_DSP }, |
| 593 | { R_BYPASS, R_BYPASS_USE_DSP }, |
| 594 | ENDMARKER, |
| 595 | }; |
| 596 | |
| 597 | static const struct regval_list ov2640_yuyv_regs[] = { |
| 598 | { IMAGE_MODE, IMAGE_MODE_YUV422 }, |
| 599 | { 0xd7, 0x03 }, |
| 600 | { 0x33, 0xa0 }, |
| 601 | { 0xe5, 0x1f }, |
| 602 | { 0xe1, 0x67 }, |
| 603 | { RESET, 0x00 }, |
| 604 | { R_BYPASS, R_BYPASS_USE_DSP }, |
| 605 | ENDMARKER, |
| 606 | }; |
| 607 | |
| 608 | static const struct regval_list ov2640_uyvy_regs[] = { |
| 609 | { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_YUV422 }, |
| 610 | { 0xd7, 0x01 }, |
| 611 | { 0x33, 0xa0 }, |
| 612 | { 0xe1, 0x67 }, |
| 613 | { RESET, 0x00 }, |
| 614 | { R_BYPASS, R_BYPASS_USE_DSP }, |
| 615 | ENDMARKER, |
| 616 | }; |
| 617 | |
| 618 | static const struct regval_list ov2640_rgb565_be_regs[] = { |
| 619 | { IMAGE_MODE, IMAGE_MODE_RGB565 }, |
| 620 | { 0xd7, 0x03 }, |
| 621 | { RESET, 0x00 }, |
| 622 | { R_BYPASS, R_BYPASS_USE_DSP }, |
| 623 | ENDMARKER, |
| 624 | }; |
| 625 | |
| 626 | static const struct regval_list ov2640_rgb565_le_regs[] = { |
| 627 | { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_RGB565 }, |
| 628 | { 0xd7, 0x03 }, |
| 629 | { RESET, 0x00 }, |
| 630 | { R_BYPASS, R_BYPASS_USE_DSP }, |
| 631 | ENDMARKER, |
| 632 | }; |
| 633 | |
| 634 | static u32 ov2640_codes[] = { |
| 635 | MEDIA_BUS_FMT_YUYV8_2X8, |
| 636 | MEDIA_BUS_FMT_UYVY8_2X8, |
| 637 | MEDIA_BUS_FMT_YVYU8_2X8, |
| 638 | MEDIA_BUS_FMT_VYUY8_2X8, |
| 639 | MEDIA_BUS_FMT_RGB565_2X8_BE, |
| 640 | MEDIA_BUS_FMT_RGB565_2X8_LE, |
| 641 | }; |
| 642 | |
| 643 | /* |
| 644 | * General functions |
| 645 | */ |
| 646 | static struct ov2640_priv *to_ov2640(const struct i2c_client *client) |
| 647 | { |
| 648 | return container_of(i2c_get_clientdata(client), struct ov2640_priv, |
| 649 | subdev); |
| 650 | } |
| 651 | |
| 652 | static int ov2640_write_array(struct i2c_client *client, |
| 653 | const struct regval_list *vals) |
| 654 | { |
| 655 | int ret; |
| 656 | |
| 657 | while ((vals->reg_num != 0xff) || (vals->value != 0xff)) { |
| 658 | ret = i2c_smbus_write_byte_data(client, |
| 659 | vals->reg_num, vals->value); |
| 660 | dev_vdbg(&client->dev, "array: 0x%02x, 0x%02x", |
| 661 | vals->reg_num, vals->value); |
| 662 | |
| 663 | if (ret < 0) |
| 664 | return ret; |
| 665 | vals++; |
| 666 | } |
| 667 | return 0; |
| 668 | } |
| 669 | |
| 670 | static int ov2640_mask_set(struct i2c_client *client, |
| 671 | u8 reg, u8 mask, u8 set) |
| 672 | { |
| 673 | s32 val = i2c_smbus_read_byte_data(client, reg); |
| 674 | if (val < 0) |
| 675 | return val; |
| 676 | |
| 677 | val &= ~mask; |
| 678 | val |= set & mask; |
| 679 | |
| 680 | dev_vdbg(&client->dev, "masks: 0x%02x, 0x%02x", reg, val); |
| 681 | |
| 682 | return i2c_smbus_write_byte_data(client, reg, val); |
| 683 | } |
| 684 | |
| 685 | static int ov2640_reset(struct i2c_client *client) |
| 686 | { |
| 687 | int ret; |
| 688 | const struct regval_list reset_seq[] = { |
| 689 | {BANK_SEL, BANK_SEL_SENS}, |
| 690 | {COM7, COM7_SRST}, |
| 691 | ENDMARKER, |
| 692 | }; |
| 693 | |
| 694 | ret = ov2640_write_array(client, reset_seq); |
| 695 | if (ret) |
| 696 | goto err; |
| 697 | |
| 698 | msleep(5); |
| 699 | err: |
| 700 | dev_dbg(&client->dev, "%s: (ret %d)", __func__, ret); |
| 701 | return ret; |
| 702 | } |
| 703 | |
| 704 | /* |
| 705 | * functions |
| 706 | */ |
| 707 | static int ov2640_s_ctrl(struct v4l2_ctrl *ctrl) |
| 708 | { |
| 709 | struct v4l2_subdev *sd = |
| 710 | &container_of(ctrl->handler, struct ov2640_priv, hdl)->subdev; |
| 711 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
| 712 | u8 val; |
| 713 | int ret; |
| 714 | |
| 715 | ret = i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS); |
| 716 | if (ret < 0) |
| 717 | return ret; |
| 718 | |
| 719 | switch (ctrl->id) { |
| 720 | case V4L2_CID_VFLIP: |
| 721 | val = ctrl->val ? REG04_VFLIP_IMG | REG04_VREF_EN : 0x00; |
| 722 | return ov2640_mask_set(client, REG04, |
| 723 | REG04_VFLIP_IMG | REG04_VREF_EN, val); |
| 724 | /* NOTE: REG04_VREF_EN: 1 line shift / even/odd line swap */ |
| 725 | case V4L2_CID_HFLIP: |
| 726 | val = ctrl->val ? REG04_HFLIP_IMG : 0x00; |
| 727 | return ov2640_mask_set(client, REG04, REG04_HFLIP_IMG, val); |
| 728 | } |
| 729 | |
| 730 | return -EINVAL; |
| 731 | } |
| 732 | |
| 733 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
| 734 | static int ov2640_g_register(struct v4l2_subdev *sd, |
| 735 | struct v4l2_dbg_register *reg) |
| 736 | { |
| 737 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
| 738 | int ret; |
| 739 | |
| 740 | reg->size = 1; |
| 741 | if (reg->reg > 0xff) |
| 742 | return -EINVAL; |
| 743 | |
| 744 | ret = i2c_smbus_read_byte_data(client, reg->reg); |
| 745 | if (ret < 0) |
| 746 | return ret; |
| 747 | |
| 748 | reg->val = ret; |
| 749 | |
| 750 | return 0; |
| 751 | } |
| 752 | |
| 753 | static int ov2640_s_register(struct v4l2_subdev *sd, |
| 754 | const struct v4l2_dbg_register *reg) |
| 755 | { |
| 756 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
| 757 | |
| 758 | if (reg->reg > 0xff || |
| 759 | reg->val > 0xff) |
| 760 | return -EINVAL; |
| 761 | |
| 762 | return i2c_smbus_write_byte_data(client, reg->reg, reg->val); |
| 763 | } |
| 764 | #endif |
| 765 | |
| 766 | static int ov2640_s_power(struct v4l2_subdev *sd, int on) |
| 767 | { |
| 768 | #ifdef CONFIG_GPIOLIB |
| 769 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
| 770 | struct ov2640_priv *priv = to_ov2640(client); |
| 771 | |
| 772 | if (priv->pwdn_gpio) |
| 773 | gpiod_direction_output(priv->pwdn_gpio, !on); |
| 774 | if (on && priv->resetb_gpio) { |
| 775 | /* Active the resetb pin to perform a reset pulse */ |
| 776 | gpiod_direction_output(priv->resetb_gpio, 1); |
| 777 | usleep_range(3000, 5000); |
| 778 | gpiod_set_value(priv->resetb_gpio, 0); |
| 779 | } |
| 780 | #endif |
| 781 | return 0; |
| 782 | } |
| 783 | |
| 784 | /* Select the nearest higher resolution for capture */ |
| 785 | static const struct ov2640_win_size *ov2640_select_win(u32 width, u32 height) |
| 786 | { |
| 787 | int i, default_size = ARRAY_SIZE(ov2640_supported_win_sizes) - 1; |
| 788 | |
| 789 | for (i = 0; i < ARRAY_SIZE(ov2640_supported_win_sizes); i++) { |
| 790 | if (ov2640_supported_win_sizes[i].width >= width && |
| 791 | ov2640_supported_win_sizes[i].height >= height) |
| 792 | return &ov2640_supported_win_sizes[i]; |
| 793 | } |
| 794 | |
| 795 | return &ov2640_supported_win_sizes[default_size]; |
| 796 | } |
| 797 | |
| 798 | static int ov2640_set_params(struct i2c_client *client, |
| 799 | const struct ov2640_win_size *win, u32 code) |
| 800 | { |
| 801 | struct ov2640_priv *priv = to_ov2640(client); |
| 802 | const struct regval_list *selected_cfmt_regs; |
| 803 | u8 val; |
| 804 | int ret; |
| 805 | |
| 806 | /* select win */ |
| 807 | priv->win = win; |
| 808 | |
| 809 | /* select format */ |
| 810 | priv->cfmt_code = 0; |
| 811 | switch (code) { |
| 812 | case MEDIA_BUS_FMT_RGB565_2X8_BE: |
| 813 | dev_dbg(&client->dev, "%s: Selected cfmt RGB565 BE", __func__); |
| 814 | selected_cfmt_regs = ov2640_rgb565_be_regs; |
| 815 | break; |
| 816 | case MEDIA_BUS_FMT_RGB565_2X8_LE: |
| 817 | dev_dbg(&client->dev, "%s: Selected cfmt RGB565 LE", __func__); |
| 818 | selected_cfmt_regs = ov2640_rgb565_le_regs; |
| 819 | break; |
| 820 | case MEDIA_BUS_FMT_YUYV8_2X8: |
| 821 | dev_dbg(&client->dev, "%s: Selected cfmt YUYV (YUV422)", __func__); |
| 822 | selected_cfmt_regs = ov2640_yuyv_regs; |
| 823 | break; |
| 824 | case MEDIA_BUS_FMT_UYVY8_2X8: |
| 825 | default: |
| 826 | dev_dbg(&client->dev, "%s: Selected cfmt UYVY", __func__); |
| 827 | selected_cfmt_regs = ov2640_uyvy_regs; |
| 828 | break; |
| 829 | case MEDIA_BUS_FMT_YVYU8_2X8: |
| 830 | dev_dbg(&client->dev, "%s: Selected cfmt YVYU", __func__); |
| 831 | selected_cfmt_regs = ov2640_yuyv_regs; |
| 832 | break; |
| 833 | case MEDIA_BUS_FMT_VYUY8_2X8: |
| 834 | dev_dbg(&client->dev, "%s: Selected cfmt VYUY", __func__); |
| 835 | selected_cfmt_regs = ov2640_uyvy_regs; |
| 836 | break; |
| 837 | } |
| 838 | |
| 839 | /* reset hardware */ |
| 840 | ov2640_reset(client); |
| 841 | |
| 842 | /* initialize the sensor with default data */ |
| 843 | dev_dbg(&client->dev, "%s: Init default", __func__); |
| 844 | ret = ov2640_write_array(client, ov2640_init_regs); |
| 845 | if (ret < 0) |
| 846 | goto err; |
| 847 | |
| 848 | /* select preamble */ |
| 849 | dev_dbg(&client->dev, "%s: Set size to %s", __func__, priv->win->name); |
| 850 | ret = ov2640_write_array(client, ov2640_size_change_preamble_regs); |
| 851 | if (ret < 0) |
| 852 | goto err; |
| 853 | |
| 854 | /* set size win */ |
| 855 | ret = ov2640_write_array(client, priv->win->regs); |
| 856 | if (ret < 0) |
| 857 | goto err; |
| 858 | |
| 859 | /* cfmt preamble */ |
| 860 | dev_dbg(&client->dev, "%s: Set cfmt", __func__); |
| 861 | ret = ov2640_write_array(client, ov2640_format_change_preamble_regs); |
| 862 | if (ret < 0) |
| 863 | goto err; |
| 864 | |
| 865 | /* set cfmt */ |
| 866 | ret = ov2640_write_array(client, selected_cfmt_regs); |
| 867 | if (ret < 0) |
| 868 | goto err; |
| 869 | val = (code == MEDIA_BUS_FMT_YVYU8_2X8) |
| 870 | || (code == MEDIA_BUS_FMT_VYUY8_2X8) ? CTRL0_VFIRST : 0x00; |
| 871 | ret = ov2640_mask_set(client, CTRL0, CTRL0_VFIRST, val); |
| 872 | if (ret < 0) |
| 873 | goto err; |
| 874 | |
| 875 | priv->cfmt_code = code; |
| 876 | |
| 877 | return 0; |
| 878 | |
| 879 | err: |
| 880 | dev_err(&client->dev, "%s: Error %d", __func__, ret); |
| 881 | ov2640_reset(client); |
| 882 | priv->win = NULL; |
| 883 | |
| 884 | return ret; |
| 885 | } |
| 886 | |
| 887 | static int ov2640_get_fmt(struct v4l2_subdev *sd, |
| 888 | struct v4l2_subdev_pad_config *cfg, |
| 889 | struct v4l2_subdev_format *format) |
| 890 | { |
| 891 | struct v4l2_mbus_framefmt *mf = &format->format; |
| 892 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
| 893 | struct ov2640_priv *priv = to_ov2640(client); |
| 894 | |
| 895 | if (format->pad) |
| 896 | return -EINVAL; |
| 897 | |
| 898 | if (!priv->win) { |
| 899 | priv->win = ov2640_select_win(SVGA_WIDTH, SVGA_HEIGHT); |
| 900 | priv->cfmt_code = MEDIA_BUS_FMT_UYVY8_2X8; |
| 901 | } |
| 902 | |
| 903 | mf->width = priv->win->width; |
| 904 | mf->height = priv->win->height; |
| 905 | mf->code = priv->cfmt_code; |
| 906 | mf->colorspace = V4L2_COLORSPACE_SRGB; |
| 907 | mf->field = V4L2_FIELD_NONE; |
| 908 | |
| 909 | return 0; |
| 910 | } |
| 911 | |
| 912 | static int ov2640_set_fmt(struct v4l2_subdev *sd, |
| 913 | struct v4l2_subdev_pad_config *cfg, |
| 914 | struct v4l2_subdev_format *format) |
| 915 | { |
| 916 | struct v4l2_mbus_framefmt *mf = &format->format; |
| 917 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
| 918 | const struct ov2640_win_size *win; |
| 919 | |
| 920 | if (format->pad) |
| 921 | return -EINVAL; |
| 922 | |
| 923 | /* select suitable win */ |
| 924 | win = ov2640_select_win(mf->width, mf->height); |
| 925 | mf->width = win->width; |
| 926 | mf->height = win->height; |
| 927 | |
| 928 | mf->field = V4L2_FIELD_NONE; |
| 929 | mf->colorspace = V4L2_COLORSPACE_SRGB; |
| 930 | |
| 931 | switch (mf->code) { |
| 932 | case MEDIA_BUS_FMT_RGB565_2X8_BE: |
| 933 | case MEDIA_BUS_FMT_RGB565_2X8_LE: |
| 934 | case MEDIA_BUS_FMT_YUYV8_2X8: |
| 935 | case MEDIA_BUS_FMT_UYVY8_2X8: |
| 936 | case MEDIA_BUS_FMT_YVYU8_2X8: |
| 937 | case MEDIA_BUS_FMT_VYUY8_2X8: |
| 938 | break; |
| 939 | default: |
| 940 | mf->code = MEDIA_BUS_FMT_UYVY8_2X8; |
| 941 | break; |
| 942 | } |
| 943 | |
| 944 | if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) |
| 945 | return ov2640_set_params(client, win, mf->code); |
| 946 | cfg->try_fmt = *mf; |
| 947 | return 0; |
| 948 | } |
| 949 | |
| 950 | static int ov2640_enum_mbus_code(struct v4l2_subdev *sd, |
| 951 | struct v4l2_subdev_pad_config *cfg, |
| 952 | struct v4l2_subdev_mbus_code_enum *code) |
| 953 | { |
| 954 | if (code->pad || code->index >= ARRAY_SIZE(ov2640_codes)) |
| 955 | return -EINVAL; |
| 956 | |
| 957 | code->code = ov2640_codes[code->index]; |
| 958 | return 0; |
| 959 | } |
| 960 | |
| 961 | static int ov2640_get_selection(struct v4l2_subdev *sd, |
| 962 | struct v4l2_subdev_pad_config *cfg, |
| 963 | struct v4l2_subdev_selection *sel) |
| 964 | { |
| 965 | if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) |
| 966 | return -EINVAL; |
| 967 | |
| 968 | switch (sel->target) { |
| 969 | case V4L2_SEL_TGT_CROP_BOUNDS: |
| 970 | case V4L2_SEL_TGT_CROP_DEFAULT: |
| 971 | case V4L2_SEL_TGT_CROP: |
| 972 | sel->r.left = 0; |
| 973 | sel->r.top = 0; |
| 974 | sel->r.width = UXGA_WIDTH; |
| 975 | sel->r.height = UXGA_HEIGHT; |
| 976 | return 0; |
| 977 | default: |
| 978 | return -EINVAL; |
| 979 | } |
| 980 | } |
| 981 | |
| 982 | static int ov2640_video_probe(struct i2c_client *client) |
| 983 | { |
| 984 | struct ov2640_priv *priv = to_ov2640(client); |
| 985 | u8 pid, ver, midh, midl; |
| 986 | const char *devname; |
| 987 | int ret; |
| 988 | |
| 989 | ret = ov2640_s_power(&priv->subdev, 1); |
| 990 | if (ret < 0) |
| 991 | return ret; |
| 992 | |
| 993 | /* |
| 994 | * check and show product ID and manufacturer ID |
| 995 | */ |
| 996 | i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS); |
| 997 | pid = i2c_smbus_read_byte_data(client, PID); |
| 998 | ver = i2c_smbus_read_byte_data(client, VER); |
| 999 | midh = i2c_smbus_read_byte_data(client, MIDH); |
| 1000 | midl = i2c_smbus_read_byte_data(client, MIDL); |
| 1001 | |
| 1002 | switch (VERSION(pid, ver)) { |
| 1003 | case PID_OV2640: |
| 1004 | devname = "ov2640"; |
| 1005 | break; |
| 1006 | default: |
| 1007 | dev_err(&client->dev, |
| 1008 | "Product ID error %x:%x\n", pid, ver); |
| 1009 | ret = -ENODEV; |
| 1010 | goto done; |
| 1011 | } |
| 1012 | |
| 1013 | dev_info(&client->dev, |
| 1014 | "%s Product ID %0x:%0x Manufacturer ID %x:%x\n", |
| 1015 | devname, pid, ver, midh, midl); |
| 1016 | |
| 1017 | ret = v4l2_ctrl_handler_setup(&priv->hdl); |
| 1018 | |
| 1019 | done: |
| 1020 | ov2640_s_power(&priv->subdev, 0); |
| 1021 | return ret; |
| 1022 | } |
| 1023 | |
| 1024 | static const struct v4l2_ctrl_ops ov2640_ctrl_ops = { |
| 1025 | .s_ctrl = ov2640_s_ctrl, |
| 1026 | }; |
| 1027 | |
| 1028 | static const struct v4l2_subdev_core_ops ov2640_subdev_core_ops = { |
| 1029 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
| 1030 | .g_register = ov2640_g_register, |
| 1031 | .s_register = ov2640_s_register, |
| 1032 | #endif |
| 1033 | .s_power = ov2640_s_power, |
| 1034 | }; |
| 1035 | |
| 1036 | static const struct v4l2_subdev_pad_ops ov2640_subdev_pad_ops = { |
| 1037 | .enum_mbus_code = ov2640_enum_mbus_code, |
| 1038 | .get_selection = ov2640_get_selection, |
| 1039 | .get_fmt = ov2640_get_fmt, |
| 1040 | .set_fmt = ov2640_set_fmt, |
| 1041 | }; |
| 1042 | |
| 1043 | static const struct v4l2_subdev_ops ov2640_subdev_ops = { |
| 1044 | .core = &ov2640_subdev_core_ops, |
| 1045 | .pad = &ov2640_subdev_pad_ops, |
| 1046 | }; |
| 1047 | |
| 1048 | static int ov2640_probe_dt(struct i2c_client *client, |
| 1049 | struct ov2640_priv *priv) |
| 1050 | { |
| 1051 | int ret; |
| 1052 | |
| 1053 | /* Request the reset GPIO deasserted */ |
| 1054 | priv->resetb_gpio = devm_gpiod_get_optional(&client->dev, "resetb", |
| 1055 | GPIOD_OUT_LOW); |
| 1056 | |
| 1057 | if (!priv->resetb_gpio) |
| 1058 | dev_dbg(&client->dev, "resetb gpio is not assigned!\n"); |
| 1059 | |
| 1060 | ret = PTR_ERR_OR_ZERO(priv->resetb_gpio); |
| 1061 | if (ret && ret != -ENOSYS) { |
| 1062 | dev_dbg(&client->dev, |
| 1063 | "Error %d while getting resetb gpio\n", ret); |
| 1064 | return ret; |
| 1065 | } |
| 1066 | |
| 1067 | /* Request the power down GPIO asserted */ |
| 1068 | priv->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "pwdn", |
| 1069 | GPIOD_OUT_HIGH); |
| 1070 | |
| 1071 | if (!priv->pwdn_gpio) |
| 1072 | dev_dbg(&client->dev, "pwdn gpio is not assigned!\n"); |
| 1073 | |
| 1074 | ret = PTR_ERR_OR_ZERO(priv->pwdn_gpio); |
| 1075 | if (ret && ret != -ENOSYS) { |
| 1076 | dev_dbg(&client->dev, |
| 1077 | "Error %d while getting pwdn gpio\n", ret); |
| 1078 | return ret; |
| 1079 | } |
| 1080 | |
| 1081 | return 0; |
| 1082 | } |
| 1083 | |
| 1084 | /* |
| 1085 | * i2c_driver functions |
| 1086 | */ |
| 1087 | static int ov2640_probe(struct i2c_client *client, |
| 1088 | const struct i2c_device_id *did) |
| 1089 | { |
| 1090 | struct ov2640_priv *priv; |
| 1091 | struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); |
| 1092 | int ret; |
| 1093 | |
| 1094 | if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { |
| 1095 | dev_err(&adapter->dev, |
| 1096 | "OV2640: I2C-Adapter doesn't support SMBUS\n"); |
| 1097 | return -EIO; |
| 1098 | } |
| 1099 | |
| 1100 | priv = devm_kzalloc(&client->dev, sizeof(struct ov2640_priv), GFP_KERNEL); |
| 1101 | if (!priv) { |
| 1102 | dev_err(&adapter->dev, |
| 1103 | "Failed to allocate memory for private data!\n"); |
| 1104 | return -ENOMEM; |
| 1105 | } |
| 1106 | |
| 1107 | if (client->dev.of_node) { |
| 1108 | priv->clk = devm_clk_get(&client->dev, "xvclk"); |
| 1109 | if (IS_ERR(priv->clk)) |
| 1110 | return -EPROBE_DEFER; |
| 1111 | clk_prepare_enable(priv->clk); |
| 1112 | } |
| 1113 | |
| 1114 | ret = ov2640_probe_dt(client, priv); |
| 1115 | if (ret) |
| 1116 | goto err_clk; |
| 1117 | |
| 1118 | v4l2_i2c_subdev_init(&priv->subdev, client, &ov2640_subdev_ops); |
| 1119 | priv->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE; |
| 1120 | v4l2_ctrl_handler_init(&priv->hdl, 2); |
| 1121 | v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops, |
| 1122 | V4L2_CID_VFLIP, 0, 1, 1, 0); |
| 1123 | v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops, |
| 1124 | V4L2_CID_HFLIP, 0, 1, 1, 0); |
| 1125 | priv->subdev.ctrl_handler = &priv->hdl; |
| 1126 | if (priv->hdl.error) { |
| 1127 | ret = priv->hdl.error; |
| 1128 | goto err_hdl; |
| 1129 | } |
| 1130 | #if defined(CONFIG_MEDIA_CONTROLLER) |
| 1131 | priv->pad.flags = MEDIA_PAD_FL_SOURCE; |
| 1132 | priv->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR; |
| 1133 | ret = media_entity_pads_init(&priv->subdev.entity, 1, &priv->pad); |
| 1134 | if (ret < 0) |
| 1135 | goto err_hdl; |
| 1136 | #endif |
| 1137 | |
| 1138 | ret = ov2640_video_probe(client); |
| 1139 | if (ret < 0) |
| 1140 | goto err_videoprobe; |
| 1141 | |
| 1142 | ret = v4l2_async_register_subdev(&priv->subdev); |
| 1143 | if (ret < 0) |
| 1144 | goto err_videoprobe; |
| 1145 | |
| 1146 | dev_info(&adapter->dev, "OV2640 Probed\n"); |
| 1147 | |
| 1148 | return 0; |
| 1149 | |
| 1150 | err_videoprobe: |
| 1151 | #if defined(CONFIG_MEDIA_CONTROLLER) |
| 1152 | media_entity_cleanup(&priv->subdev.entity); |
| 1153 | #endif |
| 1154 | err_hdl: |
| 1155 | v4l2_ctrl_handler_free(&priv->hdl); |
| 1156 | err_clk: |
| 1157 | clk_disable_unprepare(priv->clk); |
| 1158 | return ret; |
| 1159 | } |
| 1160 | |
| 1161 | static int ov2640_remove(struct i2c_client *client) |
| 1162 | { |
| 1163 | struct ov2640_priv *priv = to_ov2640(client); |
| 1164 | |
| 1165 | v4l2_async_unregister_subdev(&priv->subdev); |
| 1166 | v4l2_ctrl_handler_free(&priv->hdl); |
| 1167 | #if defined(CONFIG_MEDIA_CONTROLLER) |
| 1168 | media_entity_cleanup(&priv->subdev.entity); |
| 1169 | #endif |
| 1170 | v4l2_device_unregister_subdev(&priv->subdev); |
| 1171 | clk_disable_unprepare(priv->clk); |
| 1172 | return 0; |
| 1173 | } |
| 1174 | |
| 1175 | static const struct i2c_device_id ov2640_id[] = { |
| 1176 | { "ov2640", 0 }, |
| 1177 | { } |
| 1178 | }; |
| 1179 | MODULE_DEVICE_TABLE(i2c, ov2640_id); |
| 1180 | |
| 1181 | static const struct of_device_id ov2640_of_match[] = { |
| 1182 | {.compatible = "ovti,ov2640", }, |
| 1183 | {}, |
| 1184 | }; |
| 1185 | MODULE_DEVICE_TABLE(of, ov2640_of_match); |
| 1186 | |
| 1187 | static struct i2c_driver ov2640_i2c_driver = { |
| 1188 | .driver = { |
| 1189 | .name = "ov2640", |
| 1190 | .of_match_table = of_match_ptr(ov2640_of_match), |
| 1191 | }, |
| 1192 | .probe = ov2640_probe, |
| 1193 | .remove = ov2640_remove, |
| 1194 | .id_table = ov2640_id, |
| 1195 | }; |
| 1196 | |
| 1197 | module_i2c_driver(ov2640_i2c_driver); |
| 1198 | |
| 1199 | MODULE_DESCRIPTION("Driver for Omni Vision 2640 sensor"); |
| 1200 | MODULE_AUTHOR("Alberto Panizzo"); |
| 1201 | MODULE_LICENSE("GPL v2"); |