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192.168.1.100 / T103 / 1f884588077ad3476b9c91cbb0ee9ee0332bbb68 / . / src / kernel / linux / v4.14 / drivers / mmc / host / mtk-sdio.h
blob: 22e7e7dd324bd66a98cfe7ba8c470c266ca050a4 [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +0800[diff] [blame^]1/*
2 * Copyright (c) 2014-2015 MediaTek Inc.
3 * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#define MAX_BD_NUM 1024
16
17/*--------------------------------------------------------------------------*/
18/* Common Definition */
19/*--------------------------------------------------------------------------*/
20#define MSDC_BUS_1BITS 0x0
21#define MSDC_BUS_4BITS 0x1
22#define MSDC_BUS_8BITS 0x2
23
24#define MSDC_BURST_64B 0x6
25
26/*--------------------------------------------------------------------------*/
27/* Register Offset */
28/*--------------------------------------------------------------------------*/
29#define MSDC_CFG 0x0
30#define MSDC_IOCON 0x04
31#define MSDC_PS 0x08
32#define MSDC_INT 0x0c
33#define MSDC_INTEN 0x10
34#define MSDC_FIFOCS 0x14
35#define MSDC_TXDATA 0x18
36#define MSDC_RXDATA 0x1c
37#define SDC_CFG 0x30
38#define SDC_CMD 0x34
39#define SDC_ARG 0x38
40#define SDC_STS 0x3c
41#define SDC_RESP0 0x40
42#define SDC_RESP1 0x44
43#define SDC_RESP2 0x48
44#define SDC_RESP3 0x4c
45#define SDC_BLK_NUM 0x50
46#define SDC_ADV_CFG0 0x64
47#define EMMC_IOCON 0x7c
48#define SDC_ACMD_RESP 0x80
49#define MSDC_DMA_SA 0x90
50#define MSDC_DMA_CTRL 0x98
51#define MSDC_DMA_CFG 0x9c
52#define MSDC_DBG_SEL 0xa0
53#define MSDC_DBG_OUT 0xa4
54#define MSDC_DMA_LEN 0xa8
55#define MSDC_PATCH_BIT0 0xb0
56#define MSDC_PATCH_BIT1 0xb4
57#define MSDC_PATCH_BIT2 0xb8
58#define DAT0_TUNE_CRC 0xc0
59#define DAT1_TUNE_CRC 0xc4
60#define DAT2_TUNE_CRC 0xc8
61#define DAT3_TUNE_CRC 0xcc
62#define CMD_TUNE_CRC 0xd0
63#define SDIO_TUNE_WIND 0xd4
64#define MSDC_PAD_TUNE0 0xf0
65#define MSDC_PAD_TUNE1 0xf4
66#define MSDC_DAT_RDDLY0 0xf8
67#define MSDC_DAT_RDDLY1 0xfc
68#define MSDC_DAT_RDDLY2 0x100
69#define MSDC_DAT_RDDLY3 0x104
70#define MSDC_HW_DBG 0x110
71#define MSDC_VERSION 0x114
72#define MSDC_ECO_VER 0x118
73#define EMMC50_PAD_CTL0 0x180
74#define PAD_DS_CTL0 0x184
75#define PAD_DS_TUNE 0x188
76#define EMMC50_PAD_DS_TUNE 0x188
77
78#define PAD_CMD_TUNE 0x18c
79#define PAD_DAT01_TUNE 0x190
80#define PAD_DAT23_TUNE 0x194
81#define PAD_DAT45_TUNE 0x198
82#define PAD_DAT67_TUNE 0x19c
83#define EMMC51_CFG0 0x204
84#define EMMC50_CFG0 0x208
85#define EMMC50_CFG1 0x20c
86#define EMMC50_CFG2 0x21c
87#define EMMC50_CFG3 0x220
88#define EMMC50_CFG4 0x224
89#define SDC_FIFO_CFG 0x228
90
91
92/*--------------------------------------------------------------------------*/
93/* Top Register Offset */
94/*--------------------------------------------------------------------------*/
95#define EMMC_TOP_CONTROL (0x00)
96#define EMMC_TOP_CMD (0x04)
97#define TOP_EMMC50_PAD_CTL0 (0x08)
98#define TOP_EMMC50_PAD_DS_TUNE (0x0c)
99#define TOP_EMMC50_PAD_DAT0_TUNE (0x10)
100#define TOP_EMMC50_PAD_DAT1_TUNE (0x14)
101#define TOP_EMMC50_PAD_DAT2_TUNE (0x18)
102#define TOP_EMMC50_PAD_DAT3_TUNE (0x1c)
103
104
105/*--------------------------------------------------------------------------*/
106/* Register Mask */
107/*--------------------------------------------------------------------------*/
108
109/* MSDC_CFG mask */
110#define MSDC_CFG_MODE (0x1 << 0) /* RW */
111#define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
112#define MSDC_CFG_RST (0x1 << 2) /* RW */
113#define MSDC_CFG_PIO (0x1 << 3) /* RW */
114#define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
115#define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
116#define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
117#define MSDC_CFG_CKSTB (0x1 << 7) /* R */
118#define MSDC_CFG_CKDIV (0xfff << 8) /* RW */
119#define MSDC_CFG_CKDIV_BITS (12)
120#define MSDC_CFG_CKMOD (0x3 << 20) /* RW */
121#define MSDC_CFG_CKMOD_BITS (2)
122#define MSDC_CFG_HS400_CK_MODE (0x1 << 22) /* RW */
123#define MSDC_CFG_START_BIT (0x3 << 23) /* RW */
124#define MSDC_CFG_SCLK_STOP_DDR (0x1 << 25) /* RW */
125#define MSDC_CFG_DVFS_EN (0x1 << 30) /* RW */
126
127/* MSDC_IOCON mask */
128#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
129#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
130#define MSDC_IOCON_R_D_SMPL (0x1 << 2) /* RW */
131#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
132#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
133#define MSDC_IOCON_R_D_SMPL_SEL (0x1 << 5) /* RW */
134#define MSDC_IOCON_W_D_SMPL (0x1 << 8) /* RW */
135#define MSDC_IOCON_W_D_SMPL_SEL (0x1 << 9) /* RW */
136#define MSDC_IOCON_W_D0SPL (0x1 << 10) /* RW */
137#define MSDC_IOCON_W_D1SPL (0x1 << 11) /* RW */
138#define MSDC_IOCON_W_D2SPL (0x1 << 12) /* RW */
139#define MSDC_IOCON_W_D3SPL (0x1 << 13) /* RW */
140#define MSDC_IOCON_R_D0SPL (0x1 << 16) /* RW */
141#define MSDC_IOCON_R_D1SPL (0x1 << 17) /* RW */
142#define MSDC_IOCON_R_D2SPL (0x1 << 18) /* RW */
143#define MSDC_IOCON_R_D3SPL (0x1 << 19) /* RW */
144#define MSDC_IOCON_R_D4SPL (0x1 << 20) /* RW */
145#define MSDC_IOCON_R_D5SPL (0x1 << 21) /* RW */
146#define MSDC_IOCON_R_D6SPL (0x1 << 22) /* RW */
147#define MSDC_IOCON_R_D7SPL (0x1 << 23) /* RW */
148
149/* MSDC_PS mask */
150#define MSDC_PS_CDEN (0x1 << 0) /* RW */
151#define MSDC_PS_CDSTS (0x1 << 1) /* R */
152#define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
153#define MSDC_PS_DAT (0xff << 16) /* R */
154#define MSDC_PS_DATA1 (0x1 << 17) /* R */
155#define MSDC_PS_CMD (0x1 << 24) /* R */
156#define MSDC_PS_WP (0x1 << 31) /* R */
157
158/* MSDC_INT mask */
159#define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
160#define MSDC_INT_CDSC (0x1 << 1) /* W1C */
161#define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
162#define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
163#define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
164#define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
165#define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
166#define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
167#define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
168#define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
169#define MSDC_INT_CSTA (0x1 << 11) /* R */
170#define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
171#define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
172#define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
173#define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
174#define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
175#define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */
176#define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */
177#define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */
178
179/* MSDC_INTEN mask */
180#define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
181#define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
182#define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
183#define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
184#define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
185#define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
186#define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
187#define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
188#define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
189#define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
190#define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
191#define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
192#define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
193#define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
194#define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
195#define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
196#define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */
197#define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */
198#define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */
199
200/* MSDC_FIFOCS mask */
201#define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
202#define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
203#define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */
204
205/* SDC_CFG mask */
206#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
207#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
208#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
209#define SDC_CFG_SDIO (0x1 << 19) /* RW */
210#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
211#define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
212#define SDC_CFG_DTOC (0xff << 24) /* RW */
213
214/* SDC_STS mask */
215#define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
216#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
217#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
218
219/* SDC_ADV_CFG0 mask */
220#define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */
221
222/* DMA_SA_H4BIT mask */
223#define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */
224
225/* MSDC_DMA_CTRL mask */
226#define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
227#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
228#define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
229#define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
230#define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
231#define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
232
233/* MSDC_DMA_CFG mask */
234#define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
235#define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
236#define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */
237#define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */
238#define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */
239
240/* MSDC_PATCH_BIT0 mask */
241#define MSDC_PB0_RESV1 (0x1 << 0)
242#define MSDC_PB0_EN_8BITSUP (0x1 << 1)
243#define MSDC_PB0_DIS_RECMDWR (0x1 << 2)
244#define MSDC_PB0_RD_DAT_SEL (0x1 << 3)
245#define MSDC_PB0_RESV2 (0x3 << 4)
246#define MSDC_PB0_DESCUP (0x1 << 6)
247#define MSDC_PB0_INT_DAT_LATCH_CK_SEL (0x7 << 7)
248#define MSDC_PB0_CKGEN_MSDC_DLY_SEL (0x1F<<10)
249#define MSDC_PB0_FIFORD_DIS (0x1 << 15)
250#define MSDC_PB0_BLKNUM_SEL (0x1 << 16)
251#define MSDC_PB0_SDIO_INTCSEL (0x1 << 17)
252#define MSDC_PB0_SDC_BSYDLY (0xf << 18)
253#define MSDC_PB0_SDC_WDOD (0xf << 22)
254#define MSDC_PB0_CMDIDRTSEL (0x1 << 26)
255#define MSDC_PB0_CMDFAILSEL (0x1 << 27)
256#define MSDC_PB0_SDIO_INTDLYSEL (0x1 << 28)
257#define MSDC_PB0_SPCPUSH (0x1 << 29)
258#define MSDC_PB0_DETWR_CRCTMO (0x1 << 30)
259#define MSDC_PB0_EN_DRVRSP (0x1UL << 31)
260
261/* MSDC_PATCH_BIT1 mask */
262#define MSDC_PB1_WRDAT_CRCS_TA_CNTR (0x7 << 0)
263#define MSDC_PB1_CMD_RSP_TA_CNTR (0x7 << 3)
264#define MSDC_PB1_GET_BUSY_MA (0x1 << 6)
265#define MSDC_PB1_GET_CRC_MA (0x1 << 7)
266#define MSDC_PB1_STOP_DLY_SEL (0xf << 8)
267#define MSDC_PB1_BIAS_EN18IO_28NM (0x1 << 12)
268#define MSDC_PB1_BIAS_EXT_28NM (0x1 << 13)
269#define MSDC_PB1_RESV2 (0x1 << 14)
270#define MSDC_PB1_RESET_GDMA (0x1 << 15)
271#define MSDC_PB1_SINGLE_BURST (0x1 << 16)
272#define MSDC_PB1_FROCE_STOP (0x1 << 17)
273#define MSDC_PB1_POP_MARK_WATER (0x1 << 19)
274#define MSDC_PB1_STATE_CLEAR (0x1 << 20)
275#define MSDC_PB1_DCM_EN (0x1 << 21)
276#define MSDC_PB1_AXI_WRAP_CKEN (0x1 << 22)
277#define MSDC_PB1_CKCLK_GDMA_EN (0x1 << 23)
278#define MSDC_PB1_CKSPCEN (0x1 << 24)
279#define MSDC_PB1_CKPSCEN (0x1 << 25)
280#define MSDC_PB1_CKVOLDETEN (0x1 << 26)
281#define MSDC_PB1_CKACMDEN (0x1 << 27)
282#define MSDC_PB1_CKSDEN (0x1 << 28)
283#define MSDC_PB1_CKWCTLEN (0x1 << 29)
284#define MSDC_PB1_CKRCTLEN (0x1 << 30)
285#define MSDC_PB1_CKSHBFFEN (0x1UL << 31)
286
287/* MSDC_PATCH_BIT2 mask */
288#define MSDC_PB2_ENHANCEGPD (0x1 << 0)
289#define MSDC_PB2_SUPPORT64G (0x1 << 1)
290#define MSDC_PB2_RESPWAITCNT (0x3 << 2)
291#define MSDC_PB2_CFGRDATCNT (0x1f << 4)
292#define MSDC_PB2_CFGRDAT (0x1 << 9)
293#define MSDC_PB2_INTCRESPSEL (0x1 << 11)
294#define MSDC_PB2_CFGRESPCNT (0x7 << 12)
295#define MSDC_PB2_CFGRESP (0x1 << 15)
296#define MSDC_PB2_RESPSTSENSEL (0x7 << 16)
297#define MSDC_PB2_POPENCNT (0xf << 20)
298#define MSDC_PB2_CFG_CRCSTS_SEL (0x1 << 24)
299#define MSDC_PB2_CFGCRCSTSEDGE (0x1 << 25)
300#define MSDC_PB2_CFGCRCSTSCNT (0x3 << 26)
301#define MSDC_PB2_CFGCRCSTS (0x1 << 28)
302#define MSDC_PB2_CRCSTSENSEL (0x7UL << 29)
303
304#define MSDC_MASK_ACMD53_CRC_ERR_INTR (0x1<<4)
305#define MSDC_ACMD53_FAIL_ONE_SHOT (0X1<<5)
306
307/* MSDC_PAD_TUNE mask */
308#define MSDC_PAD_TUNE0_DATWRDLY (0x1F << 0) /* RW */
309#define MSDC_PAD_TUNE0_DELAYEN (0x1 << 7) /* RW */
310#define MSDC_PAD_TUNE0_DATRRDLY (0x1F << 8) /* RW */
311#define MSDC_PAD_TUNE0_DATRRDLYSEL (0x1 << 13) /* RW */
312#define MSDC_PAD_TUNE0_RXDLYSEL (0x1 << 15) /* RW */
313#define MSDC_PAD_TUNE0_CMDRDLY (0x1F << 16) /* RW */
314#define MSDC_PAD_TUNE0_CMDRRDLYSEL (0x1 << 21) /* RW */
315#define MSDC_PAD_TUNE0_CMDRRDLY (0x1FUL << 22) /* RW */
316#define MSDC_PAD_TUNE0_CLKTXDLY (0x1FUL << 27) /* RW */
317
318/* MSDC_PAD_TUNE1 mask */
319#define MSDC_PAD_TUNE1_DATRRDLY2 (0x1F << 8) /* RW */
320#define MSDC_PAD_TUNE1_DATRRDLY2SEL (0x1 << 13) /* RW */
321#define MSDC_PAD_TUNE1_CMDRDLY2 (0x1F << 16) /* RW */
322#define MSDC_PAD_TUNE1_CMDRRDLY2SEL (0x1 << 21) /* RW */
323
324/* MSDC_DAT_RDDLY0/1/2/3 mask */
325#define MSDC_DAT_RDDLY0_D3 (0x1F << 0) /* RW */
326#define MSDC_DAT_RDDLY0_D2 (0x1F << 8) /* RW */
327#define MSDC_DAT_RDDLY0_D1 (0x1F << 16) /* RW */
328#define MSDC_DAT_RDDLY0_D0 (0x1FUL << 24) /* RW */
329
330#define MSDC_DAT_RDDLY1_D7 (0x1F << 0) /* RW */
331#define MSDC_DAT_RDDLY1_D6 (0x1F << 8) /* RW */
332#define MSDC_DAT_RDDLY1_D5 (0x1F << 16) /* RW */
333#define MSDC_DAT_RDDLY1_D4 (0x1FUL << 24) /* RW */
334
335#define MSDC_DAT_RDDLY2_D3 (0x1F << 0) /* RW */
336#define MSDC_DAT_RDDLY2_D2 (0x1F << 8) /* RW */
337#define MSDC_DAT_RDDLY2_D1 (0x1F << 16) /* RW */
338#define MSDC_DAT_RDDLY2_D0 (0x1FUL << 24) /* RW */
339
340#define MSDC_DAT_RDDLY3_D7 (0x1F << 0) /* RW */
341#define MSDC_DAT_RDDLY3_D6 (0x1F << 8) /* RW */
342#define MSDC_DAT_RDDLY3_D5 (0x1F << 16) /* RW */
343#define MSDC_DAT_RDDLY3_D4 (0x1FUL << 24) /* RW */
344
345/* MSDC_HW_DBG_SEL mask */
346#define MSDC_HW_DBG0_SEL (0xFF << 0)
347#define MSDC_HW_DBG1_SEL (0x3F << 8)
348#define MSDC_HW_DBG2_SEL (0xFF << 16)
349#define MSDC_HW_DBG3_SEL (0x3F << 24)
350#define MSDC_HW_DBG_WRAPTYPE_SEL (0x1 << 30)
351
352/* MSDC_PATCH_BIT mask */
353#define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
354#define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7)
355#define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10)
356#define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
357#define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
358#define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
359#define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
360#define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
361#define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
362#define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
363#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
364#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
365
366/* MSDC_PATCH_BIT1 mask */
367#define MSDC_PATCH_BIT1_WRDAT_CRCS (0x7 << 0)
368#define MSDC_PATCH_BIT1_CMD_RSP (0x7 << 3)
369
370/* MSDC_PAD_TUNE mask */
371#define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */
372#define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */
373#define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */
374#define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */
375#define MSDC_PAD_TUNE_CLKTXDLY (0x1f << 27) /* RW */
376
377#define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */
378#define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */
379#define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */
380
381/* MSDC_EMMC50_PAD_CTL0 mask*/
382#define MSDC_EMMC50_PAD_CTL0_DCCSEL (0x1 << 0)
383#define MSDC_EMMC50_PAD_CTL0_HLSEL (0x1 << 1)
384#define MSDC_EMMC50_PAD_CTL0_DLP0 (0x3 << 2)
385#define MSDC_EMMC50_PAD_CTL0_DLN0 (0x3 << 4)
386#define MSDC_EMMC50_PAD_CTL0_DLP1 (0x3 << 6)
387#define MSDC_EMMC50_PAD_CTL0_DLN1 (0x3 << 8)
388
389/* MSDC_EMMC50_PAD_DS_CTL0 mask */
390#define MSDC_EMMC50_PAD_DS_CTL0_SR (0x1 << 0)
391#define MSDC_EMMC50_PAD_DS_CTL0_R0 (0x1 << 1)
392#define MSDC_EMMC50_PAD_DS_CTL0_R1 (0x1 << 2)
393#define MSDC_EMMC50_PAD_DS_CTL0_PUPD (0x1 << 3)
394#define MSDC_EMMC50_PAD_DS_CTL0_IES (0x1 << 4)
395#define MSDC_EMMC50_PAD_DS_CTL0_SMT (0x1 << 5)
396#define MSDC_EMMC50_PAD_DS_CTL0_RDSEL (0x3F << 6)
397#define MSDC_EMMC50_PAD_DS_CTL0_TDSEL (0xf << 12)
398#define MSDC_EMMC50_PAD_DS_CTL0_DRV (0x7 << 16)
399
400/* EMMC50_PAD_DS_TUNE mask */
401#define MSDC_EMMC50_PAD_DS_TUNE_DLYSEL (0x1 << 0)
402#define MSDC_EMMC50_PAD_DS_TUNE_DLY2SEL (0x1 << 1)
403#define MSDC_EMMC50_PAD_DS_TUNE_DLY1 (0x1F << 2)
404#define MSDC_EMMC50_PAD_DS_TUNE_DLY2 (0x1F << 7)
405#define MSDC_EMMC50_PAD_DS_TUNE_DLY3 (0x1F << 12)
406
407/* EMMC50_PAD_CMD_TUNE mask */
408#define MSDC_EMMC50_PAD_CMD_TUNE_DLY3SEL (0x1 << 0)
409#define MSDC_EMMC50_PAD_CMD_TUNE_RXDLY3 (0x1F << 1)
410#define MSDC_EMMC50_PAD_CMD_TUNE_TXDLY (0x1F << 6)
411
412/* EMMC50_PAD_DAT01_TUNE mask */
413#define MSDC_EMMC50_PAD_DAT0_RXDLY3SEL (0x1 << 0)
414#define MSDC_EMMC50_PAD_DAT0_RXDLY3 (0x1F << 1)
415#define MSDC_EMMC50_PAD_DAT0_TXDLY (0x1F << 6)
416#define MSDC_EMMC50_PAD_DAT1_RXDLY3SEL (0x1 << 16)
417#define MSDC_EMMC50_PAD_DAT1_RXDLY3 (0x1F << 17)
418#define MSDC_EMMC50_PAD_DAT1_TXDLY (0x1F << 22)
419
420/* EMMC50_PAD_DAT23_TUNE mask */
421#define MSDC_EMMC50_PAD_DAT2_RXDLY3SEL (0x1 << 0)
422#define MSDC_EMMC50_PAD_DAT2_RXDLY3 (0x1F << 1)
423#define MSDC_EMMC50_PAD_DAT2_TXDLY (0x1F << 6)
424#define MSDC_EMMC50_PAD_DAT3_RXDLY3SEL (0x1 << 16)
425#define MSDC_EMMC50_PAD_DAT3_RXDLY3 (0x1F << 17)
426#define MSDC_EMMC50_PAD_DAT3_TXDLY (0x1F << 22)
427
428/* EMMC50_PAD_DAT45_TUNE mask */
429#define MSDC_EMMC50_PAD_DAT4_RXDLY3SEL (0x1 << 0)
430#define MSDC_EMMC50_PAD_DAT4_RXDLY3 (0x1F << 1)
431#define MSDC_EMMC50_PAD_DAT4_TXDLY (0x1F << 6)
432#define MSDC_EMMC50_PAD_DAT5_RXDLY3SEL (0x1 << 16)
433#define MSDC_EMMC50_PAD_DAT5_RXDLY3 (0x1F << 17)
434#define MSDC_EMMC50_PAD_DAT5_TXDLY (0x1F << 22)
435
436/* EMMC50_PAD_DAT67_TUNE mask */
437#define MSDC_EMMC50_PAD_DAT6_RXDLY3SEL (0x1 << 0)
438#define MSDC_EMMC50_PAD_DAT6_RXDLY3 (0x1F << 1)
439#define MSDC_EMMC50_PAD_DAT6_TXDLY (0x1F << 6)
440#define MSDC_EMMC50_PAD_DAT7_RXDLY3SEL (0x1 << 16)
441#define MSDC_EMMC50_PAD_DAT7_RXDLY3 (0x1F << 17)
442#define MSDC_EMMC50_PAD_DAT7_TXDLY (0x1F << 22)
443
444/* EMMC51_CFG0 mask */
445#define MSDC_EMMC51_CFG_CMDQEN (0x1 << 0)
446#define MSDC_EMMC51_CFG_NUM (0x3F << 1)
447#define MSDC_EMMC51_CFG_RSPTYPE (0x7 << 7)
448#define MSDC_EMMC51_CFG_DTYPE (0x3 << 10)
449#define MSDC_EMMC51_CFG_RDATCNT (0x3FF << 12)
450#define MSDC_EMMC51_CFG_WDATCNT (0x3FF << 22)
451
452/* EMMC50_CFG0 mask */
453#define MSDC_EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0)
454#define MSDC_EMMC50_CFG_CRC_STS_CNT (0x3 << 1)
455#define MSDC_EMMC50_CFG_CRC_STS_EDGE (0x1 << 3)
456#define MSDC_EMMC50_CFG_CRC_STS_SEL (0x1 << 4)
457#define MSDC_EMMC50_CFG_END_BIT_CHK_CNT (0xf << 5)
458#define MSDC_EMMC50_CFG_CMD_RESP_SEL (0x1 << 9)
459#define MSDC_EMMC50_CFG_CMD_EDGE_SEL (0x1 << 10)
460#define MSDC_EMMC50_CFG_ENDBIT_CNT (0x3FF << 11)
461#define MSDC_EMMC50_CFG_READ_DAT_CNT (0x7 << 21)
462#define MSDC_EMMC50_CFG_EMMC50_MON_SEL (0x1 << 24)
463#define MSDC_EMMC50_CFG_MSDC_WR_VALID (0x1 << 25)
464#define MSDC_EMMC50_CFG_MSDC_RD_VALID (0x1 << 26)
465#define MSDC_EMMC50_CFG_MSDC_WR_VALID_SEL (0x1 << 27)
466#define MSDC_EMMC50_CFG_MSDC_RD_VALID_SEL (0x1 << 28)
467#define MSDC_EMMC50_CFG_TXSKEW_SEL (0x1 << 29)
468
469/* EMMC50_CFG1 mask */
470#define MSDC_EMMC50_CFG1_WRPTR_MARGIN (0xFF << 0)
471#define MSDC_EMMC50_CFG1_CKSWITCH_CNT (0x7 << 8)
472#define MSDC_EMMC50_CFG1_RDDAT_STOP (0x1 << 11)
473#define MSDC_EMMC50_CFG1_WAITCLK_CNT (0xF << 12)
474#define MSDC_EMMC50_CFG1_DBG_SEL (0xFF << 16)
475#define MSDC_EMMC50_CFG1_PSHCNT (0x7 << 24)
476#define MSDC_EMMC50_CFG1_PSHPSSEL (0x1 << 27)
477#define MSDC_EMMC50_CFG1_DSCFG (0x1 << 28)
478#define MSDC_EMMC50_CFG1_SPARE1 (0x7UL << 29)
479
480/* EMMC50_CFG2_mask */
481/*#define MSDC_EMMC50_CFG2_AXI_GPD_UP (0x1 << 0)*/
482#define MSDC_EMMC50_CFG2_AXI_IOMMU_WR_EMI (0x1 << 1)
483#define MSDC_EMMC50_CFG2_AXI_SHARE_EN_WR_EMI (0x1 << 2)
484#define MSDC_EMMC50_CFG2_AXI_IOMMU_RD_EMI (0x1 << 7)
485#define MSDC_EMMC50_CFG2_AXI_SHARE_EN_RD_EMI (0x1 << 8)
486#define MSDC_EMMC50_CFG2_AXI_BOUND_128B (0x1 << 13)
487#define MSDC_EMMC50_CFG2_AXI_BOUND_256B (0x1 << 14)
488#define MSDC_EMMC50_CFG2_AXI_BOUND_512B (0x1 << 15)
489#define MSDC_EMMC50_CFG2_AXI_BOUND_1K (0x1 << 16)
490#define MSDC_EMMC50_CFG2_AXI_BOUND_2K (0x1 << 17)
491#define MSDC_EMMC50_CFG2_AXI_BOUND_4K (0x1 << 18)
492#define MSDC_EMMC50_CFG2_AXI_RD_OUTS_NUM (0x1F << 19)
493#define MSDC_EMMC50_CFG2_AXI_SET_LEN (0xf << 24)
494#define MSDC_EMMC50_CFG2_AXI_RESP_ERR_TYPE (0x3 << 28)
495#define MSDC_EMMC50_CFG2_AXI_BUSY (0x1 << 30)
496
497/* EMMC50_CFG3_mask */
498#define MSDC_EMMC50_CFG3_OUTS_WR (0x1F << 0)
499#define MSDC_EMMC50_CFG3_ULTRA_SET_WR (0x3F << 5)
500#define MSDC_EMMC50_CFG3_PREULTRA_SET_WR (0x3F << 11)
501#define MSDC_EMMC50_CFG3_ULTRA_SET_RD (0x3F << 17)
502#define MSDC_EMMC50_CFG3_PREULTRA_SET_RD (0x3F << 23)
503
504/* EMMC50_CFG4_mask */
505#define MSDC_EMMC50_CFG4_IMPR_ULTRA_SET_WR (0xFF << 0)
506#define MSDC_EMMC50_CFG4_IMPR_ULTRA_SET_RD (0xFF << 8)
507#define MSDC_EMMC50_CFG4_ULTRA_EN (0x3 << 16)
508#define MSDC_EMMC50_CFG4_AXI_WRAP_DBG_SEL (0x1F << 18)
509
510/* EMMC50_BLOCK_LENGTH mask */
511#define MSDC_EMMC50_BLOCK_LENGTH_MASK (0x1FF << 0)
512
513/* MSDC SDC FIFO CFG masd */
514#define MSDC_WR_VALID_SEL (0x1 << 24)
515#define MSDC_RD_VALID_SEL (0x1 << 25)
516
517#define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */
518#define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */
519#define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */
520
521/* EMMC_TOP_CONTROL mask */
522#define PAD_RXDLY_SEL (0x1 << 0) /* RW */
523#define DELAY_EN (0x1 << 1) /* RW */
524#define PAD_DAT_RD_RXDLY2 (0x1F << 2) /* RW */
525#define PAD_DAT_RD_RXDLY (0x1F << 7) /* RW */
526#define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */
527#define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */
528#define DATA_K_VALUE_SEL (0x1 << 14) /* RW */
529#define SDC_RX_ENH_EN (0x1 << 15) /* TW */
530
531/* EMMC_TOP_CMD mask */
532#define PAD_CMD_RXDLY2 (0x1F << 0) /* RW */
533#define PAD_CMD_RXDLY (0x1F << 5) /* RW */
534#define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */
535#define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */
536#define PAD_CMD_TX_DLY (0x1F << 12) /* RW */
537
538/* TOP_EMMC50_PAD_CTL0 mask */
539#define HL_SEL (0x1 << 0) /* RW */
540#define DCC_SEL (0x1 << 1) /* RW */
541#define DLN1 (0x3 << 2) /* RW */
542#define DLN0 (0x3 << 4) /* RW */
543#define DLP1 (0x3 << 6) /* RW */
544#define DLP0 (0x3 << 8) /* RW */
545#define PAD_CLK_TXDLY (0x1F << 10) /* RW */
546
547/* TOP_EMMC50_PAD_DS_TUNE mask */
548#define PAD_DS_DLY3 (0x1F << 0) /* RW */
549#define PAD_DS_DLY2 (0x1F << 5) /* RW */
550#define PAD_DS_DLY1 (0x1F << 10) /* RW */
551#define PAD_DS_DLY2_SEL (0x1 << 15) /* RW */
552#define PAD_DS_DLY_SEL (0x1 << 16) /* RW */
553
554/* TOP_EMMC50_PAD_DAT0_TUNE mask */
555#define DAT0_RD_DLY2 (0x1F << 0) /* RW */
556#define DAT0_RD_DLY1 (0x1F << 5) /* RW */
557#define PAD_DAT0_TX_DLY (0x1F << 10) /* RW */
558
559/* TOP_EMMC50_PAD_DAT1_TUNE mask */
560#define DAT1_RD_DLY2 (0x1F << 0) /* RW */
561#define DAT1_RD_DLY1 (0x1F << 5) /* RW */
562#define PAD_DAT1_TX_DLY (0x1F << 10) /* RW */
563
564/* TOP_EMMC50_PAD_DAT2_TUNE mask */
565#define DAT2_RD_DLY2 (0x1F << 0) /* RW */
566#define DAT2_RD_DLY1 (0x1F << 5) /* RW */
567#define PAD_DAT2_TX_DLY (0x1F << 10) /* RW */
568
569/* TOP_EMMC50_PAD_DAT3_TUNE mask */
570#define DAT3_RD_DLY2 (0x1F << 0) /* RW */
571#define DAT3_RD_DLY1 (0x1F << 5) /* RW */
572#define PAD_DAT3_TX_DLY (0x1F << 10) /* RW */
573
574/* TOP_EMMC50_PAD_DAT4_TUNE mask */
575#define DAT4_RD_DLY2 (0x1F << 0) /* RW */
576#define DAT4_RD_DLY1 (0x1F << 5) /* RW */
577#define PAD_DAT4_TX_DLY (0x1F << 10) /* RW */
578
579/* TOP_EMMC50_PAD_DAT5_TUNE mask */
580#define DAT5_RD_DLY2 (0x1F << 0) /* RW */
581#define DAT5_RD_DLY1 (0x1F << 5) /* RW */
582#define PAD_DAT5_TX_DLY (0x1F << 10) /* RW */
583
584/* TOP_EMMC50_PAD_DAT6_TUNE mask */
585#define DAT6_RD_DLY2 (0x1F << 0) /* RW */
586#define DAT6_RD_DLY1 (0x1F << 5) /* RW */
587#define PAD_DAT6_TX_DLY (0x1F << 10) /* RW */
588
589/* TOP_EMMC50_PAD_DAT7_TUNE mask */
590#define DAT7_RD_DLY2 (0x1F << 0) /* RW */
591#define DAT7_RD_DLY1 (0x1F << 5) /* RW */
592#define PAD_DAT7_TX_DLY (0x1F << 10) /* RW */
593
594
595
596#ifdef CONFIG_MMC_MTK_SDIO
597#define SUPPORT_LEGACY_SDIO
598#endif
599
600#ifdef SUPPORT_LEGACY_SDIO
601#define SDIO_USE_PORT0 0
602#define SDIO_USE_PORT1 1
603#define SDIO_USE_PORT2 2
604#define SDIO_USE_PORT3 3
605#define SDIO_USE_PORT SDIO_USE_PORT2
606
607typedef void (*sdio_irq_handler_t)(void *); /* external irq handler */
608typedef void (*pm_callback_t)(pm_message_t state, void *data);
609
610struct sdio_ops {
611 void (*sdio_request_eirq)(sdio_irq_handler_t irq_handler, void *data);
612 void (*sdio_enable_eirq)(void);
613 void (*sdio_disable_eirq)(void);
614 void (*sdio_register_pm)(pm_callback_t pm_cb, void *data);
615};
616extern struct sdio_ops mt_sdio_ops[4] __attribute__((weak));
617#endif
618
619#define REQ_CMD_EIO (0x1 << 0)
620#define REQ_CMD_TMO (0x1 << 1)
621#define REQ_DAT_ERR (0x1 << 2)
622#define REQ_STOP_EIO (0x1 << 3)
623#define REQ_STOP_TMO (0x1 << 4)
624#define REQ_CMD_BUSY (0x1 << 5)
625
626#define MSDC_PREPARE_FLAG (0x1 << 0)
627#define MSDC_ASYNC_FLAG (0x1 << 1)
628#define MSDC_MMAP_FLAG (0x1 << 2)
629
630#define MTK_MMC_AUTOSUSPEND_DELAY 50
631#define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
632#define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
633
634#define PAD_DELAY_MAX 32 /* PAD delay cells */
635/*--------------------------------------------------------------------------*/
636/* Descriptor Structure */
637/*--------------------------------------------------------------------------*/
638struct mt_gpdma_desc {
639 u32 gpd_info;
640#define GPDMA_DESC_HWO (0x1 << 0)
641#define GPDMA_DESC_BDP (0x1 << 1)
642#define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
643#define GPDMA_DESC_INT (0x1 << 16)
644 u32 next;
645 u32 ptr;
646 u32 gpd_data_len;
647#define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
648#define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */
649 u32 arg;
650 u32 blknum;
651 u32 cmd;
652};
653
654struct mt_bdma_desc {
655 u32 bd_info;
656#define BDMA_DESC_EOL (0x1 << 0)
657#define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
658#define BDMA_DESC_BLKPAD (0x1 << 17)
659#define BDMA_DESC_DWPAD (0x1 << 18)
660 u32 next;
661 u32 ptr;
662 u32 bd_data_len;
663#define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
664};
665
666struct msdc_dma {
667 struct scatterlist *sg; /* I/O scatter list */
668 struct mt_gpdma_desc *gpd; /* pointer to gpd array */
669 struct mt_bdma_desc *bd; /* pointer to bd array */
670 dma_addr_t gpd_addr; /* the physical address of gpd array */
671 dma_addr_t bd_addr; /* the physical address of bd array */
672};
673
674struct msdc_save_para {
675 u32 msdc_cfg;
676 u32 iocon;
677 u32 sdc_cfg;
678 u32 pad_tune;
679 u32 pad_tune0;
680 u32 pad_tune1;
681 u32 patch_bit0;
682 u32 patch_bit1;
683 u32 patch_bit2;
684 u32 pad_cmd_tune;
685 u32 pad_ds_tune;
686 u32 emmc50_cfg0;
687 u32 emmc50_cfg3;
688 u32 sdc_fifo_cfg;
689 u32 emmc_top_control;
690 u32 emmc_top_cmd;
691 u32 emmc50_pad_ds_tune;
692 u32 top_emmc50_pad_dat_tune[4];
693};
694
695struct mtk_mmc_compatible {
696 u8 clk_div_bits;
697 bool hs400_tune; /* only used for MT8173 */
698 u32 pad_tune_reg;
699 bool async_fifo;
700 bool data_tune;
701 bool busy_check;
702 bool stop_clk_fix;
703 bool enhance_rx;
704 bool support_64g;
705 bool tune_resp_data_together;
706 bool fix_200m;
707};
708
709struct msdc_tune_para {
710 u32 iocon;
711 u32 pad_tune;
712 u32 pad_tune0;
713 u32 pad_tune1;
714 u32 pad_cmd_tune;
715 u32 emmc_top_control;
716 u32 emmc_top_cmd;
717};
718
719struct msdc_delay_phase {
720 u8 maxlen;
721 u8 start;
722 u8 final_phase;
723};
724
725struct msdc_host {
726 struct device *dev;
727 const struct mtk_mmc_compatible *dev_comp;
728 struct mmc_host *mmc; /* mmc structure */
729 int cmd_rsp;
730
731 spinlock_t lock;
732 spinlock_t irqlock;
733 struct mmc_request *mrq;
734 struct mmc_command *cmd;
735 struct mmc_data *data;
736 int error;
737
738 void __iomem *base; /* host base address */
739 void __iomem *top_base; /* host top register base address */
740
741 struct msdc_dma dma; /* dma channel */
742 u64 dma_mask;
743
744 u32 timeout_ns; /* data timeout ns */
745 u32 timeout_clks; /* data timeout clks */
746 u32 tune_latch_ck_cnt;
747
748 struct pinctrl *pinctrl;
749 struct pinctrl_state *pins_default;
750 struct pinctrl_state *pins_uhs;
751 struct pinctrl_state *pins_dat1;
752 struct pinctrl_state *pins_dat1_eint;
753 struct delayed_work req_timeout;
754 int irq; /* host interrupt */
755 int eint_irq;
756 int sdio_clk_cnt;
757 int sdio_irq_cnt;
758 bool irq_thread_alive;
759
760 struct clk *src_clk; /* msdc source clock */
761 struct clk *h_clk; /* msdc bus_clk */
762 struct clk *bus_clk; /* bus clock which used to access register */
763 struct clk *src_clk_cg;
764 struct clk *src_mux; /* msdc src_mux */
765 struct clk *src_pll; /* msdc src_pll */
766 u32 pll_frequency;
767 u32 mclk; /* mmc subsystem clock frequency */
768 u32 src_clk_freq; /* source clock frequency */
769 u32 sclk; /* SD/MS bus clock frequency */
770 bool clock_on;
771 unsigned char timing;
772 bool vqmmc_enabled;
773 u32 hs400_ds_delay;
774 bool hs400_mode; /* current eMMC will run at hs400 mode */
775 struct msdc_save_para save_para; /* used when gate HCLK */
776 struct msdc_tune_para def_tune_para; /* default tune setting */
777 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
778 bool autok_done;
779 int autok_error;
780
781#ifdef SUPPORT_LEGACY_SDIO
782 bool cap_eirq;
783 int suspend;
784 /* external sdio irq operations */
785 void (*request_sdio_eirq)(sdio_irq_handler_t sdio_irq_handler,
786 void *data);
787 void (*enable_sdio_eirq)(void);
788 void (*disable_sdio_eirq)(void);
789
790 /* power management callback for external module */
791 void (*register_pm)(pm_callback_t pm_cb, void *data);
792#endif
793};
794
795static bool sdio_online_tune_fail;
796extern int sdio_proc_init(struct mmc_host *host);
797