| rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Freescale eSDHC controller driver generics for OF and pltfm. |
| 3 | * |
| 4 | * Copyright (c) 2007 Freescale Semiconductor, Inc. |
| 5 | * Copyright (c) 2009 MontaVista Software, Inc. |
| 6 | * Copyright (c) 2010 Pengutronix e.K. |
| 7 | * Author: Wolfram Sang <w.sang@pengutronix.de> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License. |
| 12 | */ |
| 13 | |
| 14 | #ifndef _DRIVERS_MMC_SDHCI_ESDHC_H |
| 15 | #define _DRIVERS_MMC_SDHCI_ESDHC_H |
| 16 | |
| 17 | /* |
| 18 | * Ops and quirks for the Freescale eSDHC controller. |
| 19 | */ |
| 20 | |
| 21 | #define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \ |
| 22 | SDHCI_QUIRK_32BIT_DMA_ADDR | \ |
| 23 | SDHCI_QUIRK_NO_BUSY_IRQ | \ |
| 24 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \ |
| 25 | SDHCI_QUIRK_PIO_NEEDS_DELAY | \ |
| 26 | SDHCI_QUIRK_NO_HISPD_BIT) |
| 27 | |
| 28 | /* pltfm-specific */ |
| 29 | #define ESDHC_HOST_CONTROL_LE 0x20 |
| 30 | |
| 31 | /* |
| 32 | * eSDHC register definition |
| 33 | */ |
| 34 | |
| 35 | /* Present State Register */ |
| 36 | #define ESDHC_PRSSTAT 0x24 |
| 37 | #define ESDHC_CLOCK_STABLE 0x00000008 |
| 38 | |
| 39 | /* Protocol Control Register */ |
| 40 | #define ESDHC_PROCTL 0x28 |
| 41 | #define ESDHC_VOLT_SEL 0x00000400 |
| 42 | #define ESDHC_CTRL_4BITBUS (0x1 << 1) |
| 43 | #define ESDHC_CTRL_8BITBUS (0x2 << 1) |
| 44 | #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) |
| 45 | #define ESDHC_HOST_CONTROL_RES 0x01 |
| 46 | |
| 47 | /* System Control Register */ |
| 48 | #define ESDHC_SYSTEM_CONTROL 0x2c |
| 49 | #define ESDHC_CLOCK_MASK 0x0000fff0 |
| 50 | #define ESDHC_PREDIV_SHIFT 8 |
| 51 | #define ESDHC_DIVIDER_SHIFT 4 |
| 52 | #define ESDHC_CLOCK_SDCLKEN 0x00000008 |
| 53 | #define ESDHC_CLOCK_PEREN 0x00000004 |
| 54 | #define ESDHC_CLOCK_HCKEN 0x00000002 |
| 55 | #define ESDHC_CLOCK_IPGEN 0x00000001 |
| 56 | |
| 57 | /* Host Controller Capabilities Register 2 */ |
| 58 | #define ESDHC_CAPABILITIES_1 0x114 |
| 59 | |
| 60 | /* Tuning Block Control Register */ |
| 61 | #define ESDHC_TBCTL 0x120 |
| 62 | #define ESDHC_TB_EN 0x00000004 |
| 63 | |
| 64 | /* Control Register for DMA transfer */ |
| 65 | #define ESDHC_DMA_SYSCTL 0x40c |
| 66 | #define ESDHC_PERIPHERAL_CLK_SEL 0x00080000 |
| 67 | #define ESDHC_FLUSH_ASYNC_FIFO 0x00040000 |
| 68 | #define ESDHC_DMA_SNOOP 0x00000040 |
| 69 | |
| 70 | #endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */ |