blob: 2e5981f0cf77d8bb77fefc42eeab702d66bcacf9 [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +08001/*
2 * Driver for ICPlus PHYs
3 *
4 * Copyright (c) 2007 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 */
12#include <linux/kernel.h>
13#include <linux/string.h>
14#include <linux/errno.h>
15#include <linux/unistd.h>
16#include <linux/interrupt.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/netdevice.h>
20#include <linux/etherdevice.h>
21#include <linux/skbuff.h>
22#include <linux/spinlock.h>
23#include <linux/mm.h>
24#include <linux/module.h>
25#include <linux/mii.h>
26#include <linux/ethtool.h>
27#include <linux/phy.h>
28
29#include <asm/io.h>
30#include <asm/irq.h>
31#include <linux/uaccess.h>
32
33MODULE_DESCRIPTION("ICPlus IP175C/IP101A/IP101G/IC1001 PHY drivers");
34MODULE_AUTHOR("Michael Barkowski");
35MODULE_LICENSE("GPL");
36
37/* IP101A/G - IP1001 */
38#define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */
39#define IP1001_RXPHASE_SEL (1<<0) /* Add delay on RX_CLK */
40#define IP1001_TXPHASE_SEL (1<<1) /* Add delay on TX_CLK */
41#define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */
42#define IP1001_APS_ON 11 /* IP1001 APS Mode bit */
43#define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */
44#define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */
45#define IP101A_G_IRQ_PIN_USED (1<<15) /* INTR pin used */
46#define IP101A_G_IRQ_DEFAULT IP101A_G_IRQ_PIN_USED
47
48static int ip175c_config_init(struct phy_device *phydev)
49{
50 int err, i;
51 static int full_reset_performed;
52
53 if (full_reset_performed == 0) {
54
55 /* master reset */
56 err = mdiobus_write(phydev->mdio.bus, 30, 0, 0x175c);
57 if (err < 0)
58 return err;
59
60 /* ensure no bus delays overlap reset period */
61 err = mdiobus_read(phydev->mdio.bus, 30, 0);
62
63 /* data sheet specifies reset period is 2 msec */
64 mdelay(2);
65
66 /* enable IP175C mode */
67 err = mdiobus_write(phydev->mdio.bus, 29, 31, 0x175c);
68 if (err < 0)
69 return err;
70
71 /* Set MII0 speed and duplex (in PHY mode) */
72 err = mdiobus_write(phydev->mdio.bus, 29, 22, 0x420);
73 if (err < 0)
74 return err;
75
76 /* reset switch ports */
77 for (i = 0; i < 5; i++) {
78 err = mdiobus_write(phydev->mdio.bus, i,
79 MII_BMCR, BMCR_RESET);
80 if (err < 0)
81 return err;
82 }
83
84 for (i = 0; i < 5; i++)
85 err = mdiobus_read(phydev->mdio.bus, i, MII_BMCR);
86
87 mdelay(2);
88
89 full_reset_performed = 1;
90 }
91
92 if (phydev->mdio.addr != 4) {
93 phydev->state = PHY_RUNNING;
94 phydev->speed = SPEED_100;
95 phydev->duplex = DUPLEX_FULL;
96 phydev->link = 1;
97 netif_carrier_on(phydev->attached_dev);
98 }
99
100 return 0;
101}
102
103static int ip1xx_reset(struct phy_device *phydev)
104{
105 int bmcr;
106
107 /* Software Reset PHY */
108 bmcr = phy_read(phydev, MII_BMCR);
109 if (bmcr < 0)
110 return bmcr;
111 bmcr |= BMCR_RESET;
112 bmcr = phy_write(phydev, MII_BMCR, bmcr);
113 if (bmcr < 0)
114 return bmcr;
115
116 do {
117 bmcr = phy_read(phydev, MII_BMCR);
118 if (bmcr < 0)
119 return bmcr;
120 } while (bmcr & BMCR_RESET);
121
122 return 0;
123}
124
125static int ip1001_loopback(struct phy_device *phydev, bool enable)
126{
127 int ret;
128
129 ret = genphy_loopback(phydev, enable);
130 if (ret)
131 return ret;
132
133 return genphy_restart_aneg(phydev);
134}
135
136static int ip1001_config_init(struct phy_device *phydev)
137{
138 int c;
139
140 c = ip1xx_reset(phydev);
141 if (c < 0)
142 return c;
143
144 /* Enable Auto Power Saving mode */
145 c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2);
146 if (c < 0)
147 return c;
148 c |= IP1001_APS_ON;
149 c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c);
150 if (c < 0)
151 return c;
152
153 if (phy_interface_is_rgmii(phydev)) {
154
155 c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
156 if (c < 0)
157 return c;
158
159 c &= ~(IP1001_RXPHASE_SEL | IP1001_TXPHASE_SEL);
160
161 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
162 c |= (IP1001_RXPHASE_SEL | IP1001_TXPHASE_SEL);
163 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
164 c |= IP1001_RXPHASE_SEL;
165 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
166 c |= IP1001_TXPHASE_SEL;
167
168 c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
169 if (c < 0)
170 return c;
171 }
172
173 return 0;
174}
175
176static int ip101a_g_config_init(struct phy_device *phydev)
177{
178 int c;
179
180 c = ip1xx_reset(phydev);
181 if (c < 0)
182 return c;
183
184 /* INTR pin used: speed/link/duplex will cause an interrupt */
185 c = phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, IP101A_G_IRQ_DEFAULT);
186 if (c < 0)
187 return c;
188
189 /* Enable Auto Power Saving mode */
190 c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
191 c |= IP101A_G_APS_ON;
192
193 return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
194}
195
196static int ip175c_read_status(struct phy_device *phydev)
197{
198 if (phydev->mdio.addr == 4) /* WAN port */
199 genphy_read_status(phydev);
200 else
201 /* Don't need to read status for switch ports */
202 phydev->irq = PHY_IGNORE_INTERRUPT;
203
204 return 0;
205}
206
207static int ip175c_config_aneg(struct phy_device *phydev)
208{
209 if (phydev->mdio.addr == 4) /* WAN port */
210 genphy_config_aneg(phydev);
211
212 return 0;
213}
214
215static int ip101a_g_ack_interrupt(struct phy_device *phydev)
216{
217 int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
218 if (err < 0)
219 return err;
220
221 return 0;
222}
223
224static struct phy_driver icplus_driver[] = {
225{
226 .phy_id = 0x02430d80,
227 .name = "ICPlus IP175C",
228 .phy_id_mask = 0x0ffffff0,
229 .features = PHY_BASIC_FEATURES,
230 .config_init = &ip175c_config_init,
231 .config_aneg = &ip175c_config_aneg,
232 .read_status = &ip175c_read_status,
233 .suspend = genphy_suspend,
234 .resume = genphy_resume,
235}, {
236 .phy_id = 0x02430d90,
237 .name = "ICPlus IP1001",
238 .phy_id_mask = 0x0ffffff0,
239 .features = PHY_GBIT_FEATURES,
240 .config_init = &ip1001_config_init,
241 .config_aneg = &genphy_config_aneg,
242 .read_status = &genphy_read_status,
243 .set_loopback = ip1001_loopback,
244 .suspend = genphy_suspend,
245 .resume = genphy_resume,
246}, {
247 .phy_id = 0x02430c54,
248 .name = "ICPlus IP101A/G",
249 .phy_id_mask = 0x0ffffff0,
250 .features = PHY_BASIC_FEATURES,
251 .flags = PHY_HAS_INTERRUPT,
252 .ack_interrupt = ip101a_g_ack_interrupt,
253 .config_init = &ip101a_g_config_init,
254 .config_aneg = &genphy_config_aneg,
255 .read_status = &genphy_read_status,
256 .suspend = genphy_suspend,
257 .resume = genphy_resume,
258} };
259
260module_phy_driver(icplus_driver);
261
262static struct mdio_device_id __maybe_unused icplus_tbl[] = {
263 { 0x02430d80, 0x0ffffff0 },
264 { 0x02430d90, 0x0ffffff0 },
265 { 0x02430c54, 0x0ffffff0 },
266 { }
267};
268
269MODULE_DEVICE_TABLE(mdio, icplus_tbl);