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rjw1f884582022-01-06 17:20:42 +08001/*
2 * DesignWare application register space functions for Keystone PCI controller
3 *
4 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
5 * http://www.ti.com
6 *
7 * Author: Murali Karicheri <m-karicheri2@ti.com>
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/irq.h>
16#include <linux/irqdomain.h>
17#include <linux/irqreturn.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_pci.h>
21#include <linux/pci.h>
22#include <linux/platform_device.h>
23
24#include "pcie-designware.h"
25#include "pci-keystone.h"
26
27/* Application register defines */
28#define LTSSM_EN_VAL 1
29#define LTSSM_STATE_MASK 0x1f
30#define LTSSM_STATE_L0 0x11
31#define DBI_CS2_EN_VAL 0x20
32#define OB_XLAT_EN_VAL 2
33
34/* Application registers */
35#define CMD_STATUS 0x004
36#define CFG_SETUP 0x008
37#define OB_SIZE 0x030
38#define CFG_PCIM_WIN_SZ_IDX 3
39#define CFG_PCIM_WIN_CNT 32
40#define SPACE0_REMOTE_CFG_OFFSET 0x1000
41#define OB_OFFSET_INDEX(n) (0x200 + (8 * n))
42#define OB_OFFSET_HI(n) (0x204 + (8 * n))
43
44/* IRQ register defines */
45#define IRQ_EOI 0x050
46#define IRQ_STATUS 0x184
47#define IRQ_ENABLE_SET 0x188
48#define IRQ_ENABLE_CLR 0x18c
49
50#define MSI_IRQ 0x054
51#define MSI0_IRQ_STATUS 0x104
52#define MSI0_IRQ_ENABLE_SET 0x108
53#define MSI0_IRQ_ENABLE_CLR 0x10c
54#define IRQ_STATUS 0x184
55#define MSI_IRQ_OFFSET 4
56
57/* Error IRQ bits */
58#define ERR_AER BIT(5) /* ECRC error */
59#define ERR_AXI BIT(4) /* AXI tag lookup fatal error */
60#define ERR_CORR BIT(3) /* Correctable error */
61#define ERR_NONFATAL BIT(2) /* Non-fatal error */
62#define ERR_FATAL BIT(1) /* Fatal error */
63#define ERR_SYS BIT(0) /* System (fatal, non-fatal, or correctable) */
64#define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \
65 ERR_NONFATAL | ERR_FATAL | ERR_SYS)
66#define ERR_FATAL_IRQ (ERR_FATAL | ERR_AXI)
67#define ERR_IRQ_STATUS_RAW 0x1c0
68#define ERR_IRQ_STATUS 0x1c4
69#define ERR_IRQ_ENABLE_SET 0x1c8
70#define ERR_IRQ_ENABLE_CLR 0x1cc
71
72/* Config space registers */
73#define DEBUG0 0x728
74
75#define to_keystone_pcie(x) dev_get_drvdata((x)->dev)
76
77static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
78 u32 *bit_pos)
79{
80 *reg_offset = offset % 8;
81 *bit_pos = offset >> 3;
82}
83
84phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp)
85{
86 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
87 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
88
89 return ks_pcie->app.start + MSI_IRQ;
90}
91
92static u32 ks_dw_app_readl(struct keystone_pcie *ks_pcie, u32 offset)
93{
94 return readl(ks_pcie->va_app_base + offset);
95}
96
97static void ks_dw_app_writel(struct keystone_pcie *ks_pcie, u32 offset, u32 val)
98{
99 writel(val, ks_pcie->va_app_base + offset);
100}
101
102void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
103{
104 struct dw_pcie *pci = ks_pcie->pci;
105 struct pcie_port *pp = &pci->pp;
106 struct device *dev = pci->dev;
107 u32 pending, vector;
108 int src, virq;
109
110 pending = ks_dw_app_readl(ks_pcie, MSI0_IRQ_STATUS + (offset << 4));
111
112 /*
113 * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
114 * shows 1, 9, 17, 25 and so forth
115 */
116 for (src = 0; src < 4; src++) {
117 if (BIT(src) & pending) {
118 vector = offset + (src << 3);
119 virq = irq_linear_revmap(pp->irq_domain, vector);
120 dev_dbg(dev, "irq: bit %d, vector %d, virq %d\n",
121 src, vector, virq);
122 generic_handle_irq(virq);
123 }
124 }
125}
126
127static void ks_dw_pcie_msi_irq_ack(struct irq_data *d)
128{
129 u32 offset, reg_offset, bit_pos;
130 struct keystone_pcie *ks_pcie;
131 struct msi_desc *msi;
132 struct pcie_port *pp;
133 struct dw_pcie *pci;
134
135 msi = irq_data_get_msi_desc(d);
136 pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
137 pci = to_dw_pcie_from_pp(pp);
138 ks_pcie = to_keystone_pcie(pci);
139 offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
140 update_reg_offset_bit_pos(offset, &reg_offset, &bit_pos);
141
142 ks_dw_app_writel(ks_pcie, MSI0_IRQ_STATUS + (reg_offset << 4),
143 BIT(bit_pos));
144 ks_dw_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET);
145}
146
147void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
148{
149 u32 reg_offset, bit_pos;
150 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
151 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
152
153 update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
154 ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_SET + (reg_offset << 4),
155 BIT(bit_pos));
156}
157
158void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
159{
160 u32 reg_offset, bit_pos;
161 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
162 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
163
164 update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
165 ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_CLR + (reg_offset << 4),
166 BIT(bit_pos));
167}
168
169static void ks_dw_pcie_msi_irq_mask(struct irq_data *d)
170{
171 struct msi_desc *msi;
172 struct pcie_port *pp;
173 u32 offset;
174
175 msi = irq_data_get_msi_desc(d);
176 pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
177 offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
178
179 /* Mask the end point if PVM implemented */
180 if (IS_ENABLED(CONFIG_PCI_MSI)) {
181 if (msi->msi_attrib.maskbit)
182 pci_msi_mask_irq(d);
183 }
184
185 ks_dw_pcie_msi_clear_irq(pp, offset);
186}
187
188static void ks_dw_pcie_msi_irq_unmask(struct irq_data *d)
189{
190 struct msi_desc *msi;
191 struct pcie_port *pp;
192 u32 offset;
193
194 msi = irq_data_get_msi_desc(d);
195 pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
196 offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
197
198 /* Mask the end point if PVM implemented */
199 if (IS_ENABLED(CONFIG_PCI_MSI)) {
200 if (msi->msi_attrib.maskbit)
201 pci_msi_unmask_irq(d);
202 }
203
204 ks_dw_pcie_msi_set_irq(pp, offset);
205}
206
207static struct irq_chip ks_dw_pcie_msi_irq_chip = {
208 .name = "Keystone-PCIe-MSI-IRQ",
209 .irq_ack = ks_dw_pcie_msi_irq_ack,
210 .irq_mask = ks_dw_pcie_msi_irq_mask,
211 .irq_unmask = ks_dw_pcie_msi_irq_unmask,
212};
213
214static int ks_dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
215 irq_hw_number_t hwirq)
216{
217 irq_set_chip_and_handler(irq, &ks_dw_pcie_msi_irq_chip,
218 handle_level_irq);
219 irq_set_chip_data(irq, domain->host_data);
220
221 return 0;
222}
223
224static const struct irq_domain_ops ks_dw_pcie_msi_domain_ops = {
225 .map = ks_dw_pcie_msi_map,
226};
227
228int ks_dw_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip)
229{
230 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
231 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
232 struct device *dev = pci->dev;
233 int i;
234
235 pp->irq_domain = irq_domain_add_linear(ks_pcie->msi_intc_np,
236 MAX_MSI_IRQS,
237 &ks_dw_pcie_msi_domain_ops,
238 chip);
239 if (!pp->irq_domain) {
240 dev_err(dev, "irq domain init failed\n");
241 return -ENXIO;
242 }
243
244 for (i = 0; i < MAX_MSI_IRQS; i++)
245 irq_create_mapping(pp->irq_domain, i);
246
247 return 0;
248}
249
250void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie)
251{
252 int i;
253
254 for (i = 0; i < PCI_NUM_INTX; i++)
255 ks_dw_app_writel(ks_pcie, IRQ_ENABLE_SET + (i << 4), 0x1);
256}
257
258void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset)
259{
260 struct dw_pcie *pci = ks_pcie->pci;
261 struct device *dev = pci->dev;
262 u32 pending;
263 int virq;
264
265 pending = ks_dw_app_readl(ks_pcie, IRQ_STATUS + (offset << 4));
266
267 if (BIT(0) & pending) {
268 virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset);
269 dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", offset, virq);
270 generic_handle_irq(virq);
271 }
272
273 /* EOI the INTx interrupt */
274 ks_dw_app_writel(ks_pcie, IRQ_EOI, offset);
275}
276
277void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie)
278{
279 ks_dw_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL);
280}
281
282irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie)
283{
284 u32 status;
285
286 status = ks_dw_app_readl(ks_pcie, ERR_IRQ_STATUS_RAW) & ERR_IRQ_ALL;
287 if (!status)
288 return IRQ_NONE;
289
290 if (status & ERR_FATAL_IRQ)
291 dev_err(ks_pcie->pci->dev, "fatal error (status %#010x)\n",
292 status);
293
294 /* Ack the IRQ; status bits are RW1C */
295 ks_dw_app_writel(ks_pcie, ERR_IRQ_STATUS, status);
296 return IRQ_HANDLED;
297}
298
299static void ks_dw_pcie_ack_legacy_irq(struct irq_data *d)
300{
301}
302
303static void ks_dw_pcie_mask_legacy_irq(struct irq_data *d)
304{
305}
306
307static void ks_dw_pcie_unmask_legacy_irq(struct irq_data *d)
308{
309}
310
311static struct irq_chip ks_dw_pcie_legacy_irq_chip = {
312 .name = "Keystone-PCI-Legacy-IRQ",
313 .irq_ack = ks_dw_pcie_ack_legacy_irq,
314 .irq_mask = ks_dw_pcie_mask_legacy_irq,
315 .irq_unmask = ks_dw_pcie_unmask_legacy_irq,
316};
317
318static int ks_dw_pcie_init_legacy_irq_map(struct irq_domain *d,
319 unsigned int irq, irq_hw_number_t hw_irq)
320{
321 irq_set_chip_and_handler(irq, &ks_dw_pcie_legacy_irq_chip,
322 handle_level_irq);
323 irq_set_chip_data(irq, d->host_data);
324
325 return 0;
326}
327
328static const struct irq_domain_ops ks_dw_pcie_legacy_irq_domain_ops = {
329 .map = ks_dw_pcie_init_legacy_irq_map,
330 .xlate = irq_domain_xlate_onetwocell,
331};
332
333/**
334 * ks_dw_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask
335 * registers
336 *
337 * Since modification of dbi_cs2 involves different clock domain, read the
338 * status back to ensure the transition is complete.
339 */
340static void ks_dw_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie)
341{
342 u32 val;
343
344 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
345 ks_dw_app_writel(ks_pcie, CMD_STATUS, DBI_CS2_EN_VAL | val);
346
347 do {
348 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
349 } while (!(val & DBI_CS2_EN_VAL));
350}
351
352/**
353 * ks_dw_pcie_clear_dbi_mode() - Disable DBI mode
354 *
355 * Since modification of dbi_cs2 involves different clock domain, read the
356 * status back to ensure the transition is complete.
357 */
358static void ks_dw_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
359{
360 u32 val;
361
362 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
363 ks_dw_app_writel(ks_pcie, CMD_STATUS, ~DBI_CS2_EN_VAL & val);
364
365 do {
366 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
367 } while (val & DBI_CS2_EN_VAL);
368}
369
370void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
371{
372 struct dw_pcie *pci = ks_pcie->pci;
373 struct pcie_port *pp = &pci->pp;
374 u32 start = pp->mem->start, end = pp->mem->end;
375 int i, tr_size;
376 u32 val;
377
378 /* Disable BARs for inbound access */
379 ks_dw_pcie_set_dbi_mode(ks_pcie);
380 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
381 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0);
382 ks_dw_pcie_clear_dbi_mode(ks_pcie);
383
384 /* Set outbound translation size per window division */
385 ks_dw_app_writel(ks_pcie, OB_SIZE, CFG_PCIM_WIN_SZ_IDX & 0x7);
386
387 tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M;
388
389 /* Using Direct 1:1 mapping of RC <-> PCI memory space */
390 for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) {
391 ks_dw_app_writel(ks_pcie, OB_OFFSET_INDEX(i), start | 1);
392 ks_dw_app_writel(ks_pcie, OB_OFFSET_HI(i), 0);
393 start += tr_size;
394 }
395
396 /* Enable OB translation */
397 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
398 ks_dw_app_writel(ks_pcie, CMD_STATUS, OB_XLAT_EN_VAL | val);
399}
400
401/**
402 * ks_pcie_cfg_setup() - Set up configuration space address for a device
403 *
404 * @ks_pcie: ptr to keystone_pcie structure
405 * @bus: Bus number the device is residing on
406 * @devfn: device, function number info
407 *
408 * Forms and returns the address of configuration space mapped in PCIESS
409 * address space 0. Also configures CFG_SETUP for remote configuration space
410 * access.
411 *
412 * The address space has two regions to access configuration - local and remote.
413 * We access local region for bus 0 (as RC is attached on bus 0) and remote
414 * region for others with TYPE 1 access when bus > 1. As for device on bus = 1,
415 * we will do TYPE 0 access as it will be on our secondary bus (logical).
416 * CFG_SETUP is needed only for remote configuration access.
417 */
418static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus,
419 unsigned int devfn)
420{
421 u8 device = PCI_SLOT(devfn), function = PCI_FUNC(devfn);
422 struct dw_pcie *pci = ks_pcie->pci;
423 struct pcie_port *pp = &pci->pp;
424 u32 regval;
425
426 if (bus == 0)
427 return pci->dbi_base;
428
429 regval = (bus << 16) | (device << 8) | function;
430
431 /*
432 * Since Bus#1 will be a virtual bus, we need to have TYPE0
433 * access only.
434 * TYPE 1
435 */
436 if (bus != 1)
437 regval |= BIT(24);
438
439 ks_dw_app_writel(ks_pcie, CFG_SETUP, regval);
440 return pp->va_cfg0_base;
441}
442
443int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
444 unsigned int devfn, int where, int size, u32 *val)
445{
446 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
447 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
448 u8 bus_num = bus->number;
449 void __iomem *addr;
450
451 addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
452
453 return dw_pcie_read(addr + where, size, val);
454}
455
456int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
457 unsigned int devfn, int where, int size, u32 val)
458{
459 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
460 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
461 u8 bus_num = bus->number;
462 void __iomem *addr;
463
464 addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
465
466 return dw_pcie_write(addr + where, size, val);
467}
468
469/**
470 * ks_dw_pcie_v3_65_scan_bus() - keystone scan_bus post initialization
471 *
472 * This sets BAR0 to enable inbound access for MSI_IRQ register
473 */
474void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
475{
476 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
477 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
478
479 /* Configure and set up BAR0 */
480 ks_dw_pcie_set_dbi_mode(ks_pcie);
481
482 /* Enable BAR0 */
483 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
484 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
485
486 ks_dw_pcie_clear_dbi_mode(ks_pcie);
487
488 /*
489 * For BAR0, just setting bus address for inbound writes (MSI) should
490 * be sufficient. Use physical address to avoid any conflicts.
491 */
492 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
493}
494
495/**
496 * ks_dw_pcie_link_up() - Check if link up
497 */
498int ks_dw_pcie_link_up(struct dw_pcie *pci)
499{
500 u32 val;
501
502 val = dw_pcie_readl_dbi(pci, DEBUG0);
503 return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
504}
505
506void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
507{
508 u32 val;
509
510 /* Disable Link training */
511 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
512 val &= ~LTSSM_EN_VAL;
513 ks_dw_app_writel(ks_pcie, CMD_STATUS, val);
514
515 /* Initiate Link Training */
516 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
517 ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
518}
519
520/**
521 * ks_dw_pcie_host_init() - initialize host for v3_65 dw hardware
522 *
523 * Ioremap the register resources, initialize legacy irq domain
524 * and call dw_pcie_v3_65_host_init() API to initialize the Keystone
525 * PCI host controller.
526 */
527int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
528 struct device_node *msi_intc_np)
529{
530 struct dw_pcie *pci = ks_pcie->pci;
531 struct pcie_port *pp = &pci->pp;
532 struct device *dev = pci->dev;
533 struct platform_device *pdev = to_platform_device(dev);
534 struct resource *res;
535
536 /* Index 0 is the config reg. space address */
537 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
538 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
539 if (IS_ERR(pci->dbi_base))
540 return PTR_ERR(pci->dbi_base);
541
542 /*
543 * We set these same and is used in pcie rd/wr_other_conf
544 * functions
545 */
546 pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET;
547 pp->va_cfg1_base = pp->va_cfg0_base;
548
549 /* Index 1 is the application reg. space address */
550 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
551 ks_pcie->va_app_base = devm_ioremap_resource(dev, res);
552 if (IS_ERR(ks_pcie->va_app_base))
553 return PTR_ERR(ks_pcie->va_app_base);
554
555 ks_pcie->app = *res;
556
557 /* Create legacy IRQ domain */
558 ks_pcie->legacy_irq_domain =
559 irq_domain_add_linear(ks_pcie->legacy_intc_np,
560 PCI_NUM_INTX,
561 &ks_dw_pcie_legacy_irq_domain_ops,
562 NULL);
563 if (!ks_pcie->legacy_irq_domain) {
564 dev_err(dev, "Failed to add irq domain for legacy irqs\n");
565 return -EINVAL;
566 }
567
568 return dw_pcie_host_init(pp);
569}