blob: 981a5195686f3c084476218a6c13061aa1119fff [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +08001/*
2 * PCIe host controller driver for NWL PCIe Bridge
3 * Based on pcie-xilinx.c, pci-tegra.c
4 *
5 * (C) Copyright 2014 - 2015, Xilinx, Inc.
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/delay.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/irqdomain.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/msi.h>
20#include <linux/of_address.h>
21#include <linux/of_pci.h>
22#include <linux/of_platform.h>
23#include <linux/of_irq.h>
24#include <linux/pci.h>
25#include <linux/platform_device.h>
26#include <linux/irqchip/chained_irq.h>
27
28/* Bridge core config registers */
29#define BRCFG_PCIE_RX0 0x00000000
30#define BRCFG_INTERRUPT 0x00000010
31#define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
32
33/* Egress - Bridge translation registers */
34#define E_BREG_CAPABILITIES 0x00000200
35#define E_BREG_CONTROL 0x00000208
36#define E_BREG_BASE_LO 0x00000210
37#define E_BREG_BASE_HI 0x00000214
38#define E_ECAM_CAPABILITIES 0x00000220
39#define E_ECAM_CONTROL 0x00000228
40#define E_ECAM_BASE_LO 0x00000230
41#define E_ECAM_BASE_HI 0x00000234
42
43/* Ingress - address translations */
44#define I_MSII_CAPABILITIES 0x00000300
45#define I_MSII_CONTROL 0x00000308
46#define I_MSII_BASE_LO 0x00000310
47#define I_MSII_BASE_HI 0x00000314
48
49#define I_ISUB_CONTROL 0x000003E8
50#define SET_ISUB_CONTROL BIT(0)
51/* Rxed msg fifo - Interrupt status registers */
52#define MSGF_MISC_STATUS 0x00000400
53#define MSGF_MISC_MASK 0x00000404
54#define MSGF_LEG_STATUS 0x00000420
55#define MSGF_LEG_MASK 0x00000424
56#define MSGF_MSI_STATUS_LO 0x00000440
57#define MSGF_MSI_STATUS_HI 0x00000444
58#define MSGF_MSI_MASK_LO 0x00000448
59#define MSGF_MSI_MASK_HI 0x0000044C
60
61/* Msg filter mask bits */
62#define CFG_ENABLE_PM_MSG_FWD BIT(1)
63#define CFG_ENABLE_INT_MSG_FWD BIT(2)
64#define CFG_ENABLE_ERR_MSG_FWD BIT(3)
65#define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \
66 CFG_ENABLE_INT_MSG_FWD | \
67 CFG_ENABLE_ERR_MSG_FWD)
68
69/* Misc interrupt status mask bits */
70#define MSGF_MISC_SR_RXMSG_AVAIL BIT(0)
71#define MSGF_MISC_SR_RXMSG_OVER BIT(1)
72#define MSGF_MISC_SR_SLAVE_ERR BIT(4)
73#define MSGF_MISC_SR_MASTER_ERR BIT(5)
74#define MSGF_MISC_SR_I_ADDR_ERR BIT(6)
75#define MSGF_MISC_SR_E_ADDR_ERR BIT(7)
76#define MSGF_MISC_SR_FATAL_AER BIT(16)
77#define MSGF_MISC_SR_NON_FATAL_AER BIT(17)
78#define MSGF_MISC_SR_CORR_AER BIT(18)
79#define MSGF_MISC_SR_UR_DETECT BIT(20)
80#define MSGF_MISC_SR_NON_FATAL_DEV BIT(22)
81#define MSGF_MISC_SR_FATAL_DEV BIT(23)
82#define MSGF_MISC_SR_LINK_DOWN BIT(24)
83#define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25)
84#define MSGF_MSIC_SR_LINK_BWIDTH BIT(26)
85
86#define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \
87 MSGF_MISC_SR_RXMSG_OVER | \
88 MSGF_MISC_SR_SLAVE_ERR | \
89 MSGF_MISC_SR_MASTER_ERR | \
90 MSGF_MISC_SR_I_ADDR_ERR | \
91 MSGF_MISC_SR_E_ADDR_ERR | \
92 MSGF_MISC_SR_FATAL_AER | \
93 MSGF_MISC_SR_NON_FATAL_AER | \
94 MSGF_MISC_SR_CORR_AER | \
95 MSGF_MISC_SR_UR_DETECT | \
96 MSGF_MISC_SR_NON_FATAL_DEV | \
97 MSGF_MISC_SR_FATAL_DEV | \
98 MSGF_MISC_SR_LINK_DOWN | \
99 MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \
100 MSGF_MSIC_SR_LINK_BWIDTH)
101
102/* Legacy interrupt status mask bits */
103#define MSGF_LEG_SR_INTA BIT(0)
104#define MSGF_LEG_SR_INTB BIT(1)
105#define MSGF_LEG_SR_INTC BIT(2)
106#define MSGF_LEG_SR_INTD BIT(3)
107#define MSGF_LEG_SR_MASKALL (MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \
108 MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
109
110/* MSI interrupt status mask bits */
111#define MSGF_MSI_SR_LO_MASK GENMASK(31, 0)
112#define MSGF_MSI_SR_HI_MASK GENMASK(31, 0)
113
114#define MSII_PRESENT BIT(0)
115#define MSII_ENABLE BIT(0)
116#define MSII_STATUS_ENABLE BIT(15)
117
118/* Bridge config interrupt mask */
119#define BRCFG_INTERRUPT_MASK BIT(0)
120#define BREG_PRESENT BIT(0)
121#define BREG_ENABLE BIT(0)
122#define BREG_ENABLE_FORCE BIT(1)
123
124/* E_ECAM status mask bits */
125#define E_ECAM_PRESENT BIT(0)
126#define E_ECAM_CR_ENABLE BIT(0)
127#define E_ECAM_SIZE_LOC GENMASK(20, 16)
128#define E_ECAM_SIZE_SHIFT 16
129#define ECAM_BUS_LOC_SHIFT 20
130#define ECAM_DEV_LOC_SHIFT 12
131#define NWL_ECAM_VALUE_DEFAULT 12
132
133#define CFG_DMA_REG_BAR GENMASK(2, 0)
134
135#define INT_PCI_MSI_NR (2 * 32)
136
137/* Readin the PS_LINKUP */
138#define PS_LINKUP_OFFSET 0x00000238
139#define PCIE_PHY_LINKUP_BIT BIT(0)
140#define PHY_RDY_LINKUP_BIT BIT(1)
141
142/* Parameters for the waiting for link up routine */
143#define LINK_WAIT_MAX_RETRIES 10
144#define LINK_WAIT_USLEEP_MIN 90000
145#define LINK_WAIT_USLEEP_MAX 100000
146
147struct nwl_msi { /* MSI information */
148 struct irq_domain *msi_domain;
149 unsigned long *bitmap;
150 struct irq_domain *dev_domain;
151 struct mutex lock; /* protect bitmap variable */
152 int irq_msi0;
153 int irq_msi1;
154};
155
156struct nwl_pcie {
157 struct device *dev;
158 void __iomem *breg_base;
159 void __iomem *pcireg_base;
160 void __iomem *ecam_base;
161 phys_addr_t phys_breg_base; /* Physical Bridge Register Base */
162 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
163 phys_addr_t phys_ecam_base; /* Physical Configuration Base */
164 u32 breg_size;
165 u32 pcie_reg_size;
166 u32 ecam_size;
167 int irq_intx;
168 int irq_misc;
169 u32 ecam_value;
170 u8 last_busno;
171 u8 root_busno;
172 struct nwl_msi msi;
173 struct irq_domain *legacy_irq_domain;
174 raw_spinlock_t leg_mask_lock;
175};
176
177static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
178{
179 return readl(pcie->breg_base + off);
180}
181
182static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
183{
184 writel(val, pcie->breg_base + off);
185}
186
187static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
188{
189 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
190 return true;
191 return false;
192}
193
194static bool nwl_phy_link_up(struct nwl_pcie *pcie)
195{
196 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
197 return true;
198 return false;
199}
200
201static int nwl_wait_for_link(struct nwl_pcie *pcie)
202{
203 struct device *dev = pcie->dev;
204 int retries;
205
206 /* check if the link is up or not */
207 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
208 if (nwl_phy_link_up(pcie))
209 return 0;
210 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
211 }
212
213 dev_err(dev, "PHY link never came up\n");
214 return -ETIMEDOUT;
215}
216
217static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
218{
219 struct nwl_pcie *pcie = bus->sysdata;
220
221 /* Check link before accessing downstream ports */
222 if (bus->number != pcie->root_busno) {
223 if (!nwl_pcie_link_up(pcie))
224 return false;
225 }
226
227 /* Only one device down on each root port */
228 if (bus->number == pcie->root_busno && devfn > 0)
229 return false;
230
231 return true;
232}
233
234/**
235 * nwl_pcie_map_bus - Get configuration base
236 *
237 * @bus: Bus structure of current bus
238 * @devfn: Device/function
239 * @where: Offset from base
240 *
241 * Return: Base address of the configuration space needed to be
242 * accessed.
243 */
244static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
245 int where)
246{
247 struct nwl_pcie *pcie = bus->sysdata;
248 int relbus;
249
250 if (!nwl_pcie_valid_device(bus, devfn))
251 return NULL;
252
253 relbus = (bus->number << ECAM_BUS_LOC_SHIFT) |
254 (devfn << ECAM_DEV_LOC_SHIFT);
255
256 return pcie->ecam_base + relbus + where;
257}
258
259/* PCIe operations */
260static struct pci_ops nwl_pcie_ops = {
261 .map_bus = nwl_pcie_map_bus,
262 .read = pci_generic_config_read,
263 .write = pci_generic_config_write,
264};
265
266static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
267{
268 struct nwl_pcie *pcie = data;
269 struct device *dev = pcie->dev;
270 u32 misc_stat;
271
272 /* Checking for misc interrupts */
273 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
274 MSGF_MISC_SR_MASKALL;
275 if (!misc_stat)
276 return IRQ_NONE;
277
278 if (misc_stat & MSGF_MISC_SR_RXMSG_OVER)
279 dev_err(dev, "Received Message FIFO Overflow\n");
280
281 if (misc_stat & MSGF_MISC_SR_SLAVE_ERR)
282 dev_err(dev, "Slave error\n");
283
284 if (misc_stat & MSGF_MISC_SR_MASTER_ERR)
285 dev_err(dev, "Master error\n");
286
287 if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR)
288 dev_err(dev, "In Misc Ingress address translation error\n");
289
290 if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR)
291 dev_err(dev, "In Misc Egress address translation error\n");
292
293 if (misc_stat & MSGF_MISC_SR_FATAL_AER)
294 dev_err(dev, "Fatal Error in AER Capability\n");
295
296 if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER)
297 dev_err(dev, "Non-Fatal Error in AER Capability\n");
298
299 if (misc_stat & MSGF_MISC_SR_CORR_AER)
300 dev_err(dev, "Correctable Error in AER Capability\n");
301
302 if (misc_stat & MSGF_MISC_SR_UR_DETECT)
303 dev_err(dev, "Unsupported request Detected\n");
304
305 if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV)
306 dev_err(dev, "Non-Fatal Error Detected\n");
307
308 if (misc_stat & MSGF_MISC_SR_FATAL_DEV)
309 dev_err(dev, "Fatal Error Detected\n");
310
311 if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH)
312 dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n");
313
314 if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH)
315 dev_info(dev, "Link Bandwidth Management Status bit set\n");
316
317 /* Clear misc interrupt status */
318 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);
319
320 return IRQ_HANDLED;
321}
322
323static void nwl_pcie_leg_handler(struct irq_desc *desc)
324{
325 struct irq_chip *chip = irq_desc_get_chip(desc);
326 struct nwl_pcie *pcie;
327 unsigned long status;
328 u32 bit;
329 u32 virq;
330
331 chained_irq_enter(chip, desc);
332 pcie = irq_desc_get_handler_data(desc);
333
334 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
335 MSGF_LEG_SR_MASKALL) != 0) {
336 for_each_set_bit(bit, &status, PCI_NUM_INTX) {
337 virq = irq_find_mapping(pcie->legacy_irq_domain, bit);
338 if (virq)
339 generic_handle_irq(virq);
340 }
341 }
342
343 chained_irq_exit(chip, desc);
344}
345
346static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)
347{
348 struct nwl_msi *msi;
349 unsigned long status;
350 u32 bit;
351 u32 virq;
352
353 msi = &pcie->msi;
354
355 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {
356 for_each_set_bit(bit, &status, 32) {
357 nwl_bridge_writel(pcie, 1 << bit, status_reg);
358 virq = irq_find_mapping(msi->dev_domain, bit);
359 if (virq)
360 generic_handle_irq(virq);
361 }
362 }
363}
364
365static void nwl_pcie_msi_handler_high(struct irq_desc *desc)
366{
367 struct irq_chip *chip = irq_desc_get_chip(desc);
368 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
369
370 chained_irq_enter(chip, desc);
371 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);
372 chained_irq_exit(chip, desc);
373}
374
375static void nwl_pcie_msi_handler_low(struct irq_desc *desc)
376{
377 struct irq_chip *chip = irq_desc_get_chip(desc);
378 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
379
380 chained_irq_enter(chip, desc);
381 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);
382 chained_irq_exit(chip, desc);
383}
384
385static void nwl_mask_leg_irq(struct irq_data *data)
386{
387 struct irq_desc *desc = irq_to_desc(data->irq);
388 struct nwl_pcie *pcie;
389 unsigned long flags;
390 u32 mask;
391 u32 val;
392
393 pcie = irq_desc_get_chip_data(desc);
394 mask = 1 << (data->hwirq - 1);
395 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
396 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
397 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);
398 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
399}
400
401static void nwl_unmask_leg_irq(struct irq_data *data)
402{
403 struct irq_desc *desc = irq_to_desc(data->irq);
404 struct nwl_pcie *pcie;
405 unsigned long flags;
406 u32 mask;
407 u32 val;
408
409 pcie = irq_desc_get_chip_data(desc);
410 mask = 1 << (data->hwirq - 1);
411 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
412 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
413 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);
414 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
415}
416
417static struct irq_chip nwl_leg_irq_chip = {
418 .name = "nwl_pcie:legacy",
419 .irq_enable = nwl_unmask_leg_irq,
420 .irq_disable = nwl_mask_leg_irq,
421 .irq_mask = nwl_mask_leg_irq,
422 .irq_unmask = nwl_unmask_leg_irq,
423};
424
425static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq,
426 irq_hw_number_t hwirq)
427{
428 irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_level_irq);
429 irq_set_chip_data(irq, domain->host_data);
430 irq_set_status_flags(irq, IRQ_LEVEL);
431
432 return 0;
433}
434
435static const struct irq_domain_ops legacy_domain_ops = {
436 .map = nwl_legacy_map,
437 .xlate = pci_irqd_intx_xlate,
438};
439
440#ifdef CONFIG_PCI_MSI
441static struct irq_chip nwl_msi_irq_chip = {
442 .name = "nwl_pcie:msi",
443 .irq_enable = unmask_msi_irq,
444 .irq_disable = mask_msi_irq,
445 .irq_mask = mask_msi_irq,
446 .irq_unmask = unmask_msi_irq,
447
448};
449
450static struct msi_domain_info nwl_msi_domain_info = {
451 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
452 MSI_FLAG_MULTI_PCI_MSI),
453 .chip = &nwl_msi_irq_chip,
454};
455#endif
456
457static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
458{
459 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
460 phys_addr_t msi_addr = pcie->phys_pcie_reg_base;
461
462 msg->address_lo = lower_32_bits(msi_addr);
463 msg->address_hi = upper_32_bits(msi_addr);
464 msg->data = data->hwirq;
465}
466
467static int nwl_msi_set_affinity(struct irq_data *irq_data,
468 const struct cpumask *mask, bool force)
469{
470 return -EINVAL;
471}
472
473static struct irq_chip nwl_irq_chip = {
474 .name = "Xilinx MSI",
475 .irq_compose_msi_msg = nwl_compose_msi_msg,
476 .irq_set_affinity = nwl_msi_set_affinity,
477};
478
479static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
480 unsigned int nr_irqs, void *args)
481{
482 struct nwl_pcie *pcie = domain->host_data;
483 struct nwl_msi *msi = &pcie->msi;
484 int bit;
485 int i;
486
487 mutex_lock(&msi->lock);
488 bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR,
489 get_count_order(nr_irqs));
490 if (bit < 0) {
491 mutex_unlock(&msi->lock);
492 return -ENOSPC;
493 }
494
495 for (i = 0; i < nr_irqs; i++) {
496 irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip,
497 domain->host_data, handle_simple_irq,
498 NULL, NULL);
499 }
500 mutex_unlock(&msi->lock);
501 return 0;
502}
503
504static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq,
505 unsigned int nr_irqs)
506{
507 struct irq_data *data = irq_domain_get_irq_data(domain, virq);
508 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
509 struct nwl_msi *msi = &pcie->msi;
510
511 mutex_lock(&msi->lock);
512 bitmap_release_region(msi->bitmap, data->hwirq,
513 get_count_order(nr_irqs));
514 mutex_unlock(&msi->lock);
515}
516
517static const struct irq_domain_ops dev_msi_domain_ops = {
518 .alloc = nwl_irq_domain_alloc,
519 .free = nwl_irq_domain_free,
520};
521
522static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
523{
524#ifdef CONFIG_PCI_MSI
525 struct device *dev = pcie->dev;
526 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
527 struct nwl_msi *msi = &pcie->msi;
528
529 msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR,
530 &dev_msi_domain_ops, pcie);
531 if (!msi->dev_domain) {
532 dev_err(dev, "failed to create dev IRQ domain\n");
533 return -ENOMEM;
534 }
535 msi->msi_domain = pci_msi_create_irq_domain(fwnode,
536 &nwl_msi_domain_info,
537 msi->dev_domain);
538 if (!msi->msi_domain) {
539 dev_err(dev, "failed to create msi IRQ domain\n");
540 irq_domain_remove(msi->dev_domain);
541 return -ENOMEM;
542 }
543#endif
544 return 0;
545}
546
547static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
548{
549 struct device *dev = pcie->dev;
550 struct device_node *node = dev->of_node;
551 struct device_node *legacy_intc_node;
552
553 legacy_intc_node = of_get_next_child(node, NULL);
554 if (!legacy_intc_node) {
555 dev_err(dev, "No legacy intc node found\n");
556 return -EINVAL;
557 }
558
559 pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node,
560 PCI_NUM_INTX,
561 &legacy_domain_ops,
562 pcie);
563 of_node_put(legacy_intc_node);
564 if (!pcie->legacy_irq_domain) {
565 dev_err(dev, "failed to create IRQ domain\n");
566 return -ENOMEM;
567 }
568
569 raw_spin_lock_init(&pcie->leg_mask_lock);
570 nwl_pcie_init_msi_irq_domain(pcie);
571 return 0;
572}
573
574static int nwl_pcie_enable_msi(struct nwl_pcie *pcie)
575{
576 struct device *dev = pcie->dev;
577 struct platform_device *pdev = to_platform_device(dev);
578 struct nwl_msi *msi = &pcie->msi;
579 unsigned long base;
580 int ret;
581 int size = BITS_TO_LONGS(INT_PCI_MSI_NR) * sizeof(long);
582
583 mutex_init(&msi->lock);
584
585 msi->bitmap = kzalloc(size, GFP_KERNEL);
586 if (!msi->bitmap)
587 return -ENOMEM;
588
589 /* Get msi_1 IRQ number */
590 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1");
591 if (msi->irq_msi1 < 0) {
592 dev_err(dev, "failed to get IRQ#%d\n", msi->irq_msi1);
593 ret = -EINVAL;
594 goto err;
595 }
596
597 irq_set_chained_handler_and_data(msi->irq_msi1,
598 nwl_pcie_msi_handler_high, pcie);
599
600 /* Get msi_0 IRQ number */
601 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0");
602 if (msi->irq_msi0 < 0) {
603 dev_err(dev, "failed to get IRQ#%d\n", msi->irq_msi0);
604 ret = -EINVAL;
605 goto err;
606 }
607
608 irq_set_chained_handler_and_data(msi->irq_msi0,
609 nwl_pcie_msi_handler_low, pcie);
610
611 /* Check for msii_present bit */
612 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
613 if (!ret) {
614 dev_err(dev, "MSI not present\n");
615 ret = -EIO;
616 goto err;
617 }
618
619 /* Enable MSII */
620 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
621 MSII_ENABLE, I_MSII_CONTROL);
622
623 /* Enable MSII status */
624 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
625 MSII_STATUS_ENABLE, I_MSII_CONTROL);
626
627 /* setup AFI/FPCI range */
628 base = pcie->phys_pcie_reg_base;
629 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
630 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
631
632 /*
633 * For high range MSI interrupts: disable, clear any pending,
634 * and enable
635 */
636 nwl_bridge_writel(pcie, (u32)~MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
637
638 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) &
639 MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI);
640
641 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
642
643 /*
644 * For low range MSI interrupts: disable, clear any pending,
645 * and enable
646 */
647 nwl_bridge_writel(pcie, (u32)~MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
648
649 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &
650 MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO);
651
652 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
653
654 return 0;
655err:
656 kfree(msi->bitmap);
657 msi->bitmap = NULL;
658 return ret;
659}
660
661static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
662{
663 struct device *dev = pcie->dev;
664 struct platform_device *pdev = to_platform_device(dev);
665 u32 breg_val, ecam_val, first_busno = 0;
666 int err;
667
668 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
669 if (!breg_val) {
670 dev_err(dev, "BREG is not present\n");
671 return breg_val;
672 }
673
674 /* Write bridge_off to breg base */
675 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),
676 E_BREG_BASE_LO);
677 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),
678 E_BREG_BASE_HI);
679
680 /* Enable BREG */
681 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
682 E_BREG_CONTROL);
683
684 /* Disable DMA channel registers */
685 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |
686 CFG_DMA_REG_BAR, BRCFG_PCIE_RX0);
687
688 /* Enable Ingress subtractive decode translation */
689 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);
690
691 /* Enable msg filtering details */
692 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
693 BRCFG_PCIE_RX_MSG_FILTER);
694
695 err = nwl_wait_for_link(pcie);
696 if (err)
697 return err;
698
699 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
700 if (!ecam_val) {
701 dev_err(dev, "ECAM is not present\n");
702 return ecam_val;
703 }
704
705 /* Enable ECAM */
706 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
707 E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
708
709 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
710 (pcie->ecam_value << E_ECAM_SIZE_SHIFT),
711 E_ECAM_CONTROL);
712
713 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
714 E_ECAM_BASE_LO);
715 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
716 E_ECAM_BASE_HI);
717
718 /* Get bus range */
719 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);
720 pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;
721 /* Write primary, secondary and subordinate bus numbers */
722 ecam_val = first_busno;
723 ecam_val |= (first_busno + 1) << 8;
724 ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);
725 writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));
726
727 if (nwl_pcie_link_up(pcie))
728 dev_info(dev, "Link is UP\n");
729 else
730 dev_info(dev, "Link is DOWN\n");
731
732 /* Get misc IRQ number */
733 pcie->irq_misc = platform_get_irq_byname(pdev, "misc");
734 if (pcie->irq_misc < 0) {
735 dev_err(dev, "failed to get misc IRQ %d\n",
736 pcie->irq_misc);
737 return -EINVAL;
738 }
739
740 err = devm_request_irq(dev, pcie->irq_misc,
741 nwl_pcie_misc_handler, IRQF_SHARED,
742 "nwl_pcie:misc", pcie);
743 if (err) {
744 dev_err(dev, "fail to register misc IRQ#%d\n",
745 pcie->irq_misc);
746 return err;
747 }
748
749 /* Disable all misc interrupts */
750 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
751
752 /* Clear pending misc interrupts */
753 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
754 MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS);
755
756 /* Enable all misc interrupts */
757 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
758
759
760 /* Disable all legacy interrupts */
761 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
762
763 /* Clear pending legacy interrupts */
764 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
765 MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);
766
767 /* Enable all legacy interrupts */
768 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
769
770 /* Enable the bridge config interrupt */
771 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |
772 BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT);
773
774 return 0;
775}
776
777static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
778 struct platform_device *pdev)
779{
780 struct device *dev = pcie->dev;
781 struct device_node *node = dev->of_node;
782 struct resource *res;
783 const char *type;
784
785 /* Check for device type */
786 type = of_get_property(node, "device_type", NULL);
787 if (!type || strcmp(type, "pci")) {
788 dev_err(dev, "invalid \"device_type\" %s\n", type);
789 return -EINVAL;
790 }
791
792 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
793 pcie->breg_base = devm_ioremap_resource(dev, res);
794 if (IS_ERR(pcie->breg_base))
795 return PTR_ERR(pcie->breg_base);
796 pcie->phys_breg_base = res->start;
797
798 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg");
799 pcie->pcireg_base = devm_ioremap_resource(dev, res);
800 if (IS_ERR(pcie->pcireg_base))
801 return PTR_ERR(pcie->pcireg_base);
802 pcie->phys_pcie_reg_base = res->start;
803
804 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
805 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res);
806 if (IS_ERR(pcie->ecam_base))
807 return PTR_ERR(pcie->ecam_base);
808 pcie->phys_ecam_base = res->start;
809
810 /* Get intx IRQ number */
811 pcie->irq_intx = platform_get_irq_byname(pdev, "intx");
812 if (pcie->irq_intx < 0) {
813 dev_err(dev, "failed to get intx IRQ %d\n", pcie->irq_intx);
814 return pcie->irq_intx;
815 }
816
817 irq_set_chained_handler_and_data(pcie->irq_intx,
818 nwl_pcie_leg_handler, pcie);
819
820 return 0;
821}
822
823static const struct of_device_id nwl_pcie_of_match[] = {
824 { .compatible = "xlnx,nwl-pcie-2.11", },
825 {}
826};
827
828static int nwl_pcie_probe(struct platform_device *pdev)
829{
830 struct device *dev = &pdev->dev;
831 struct device_node *node = dev->of_node;
832 struct nwl_pcie *pcie;
833 struct pci_bus *bus;
834 struct pci_bus *child;
835 struct pci_host_bridge *bridge;
836 int err;
837 resource_size_t iobase = 0;
838 LIST_HEAD(res);
839
840 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
841 if (!bridge)
842 return -ENODEV;
843
844 pcie = pci_host_bridge_priv(bridge);
845
846 pcie->dev = dev;
847 pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
848
849 err = nwl_pcie_parse_dt(pcie, pdev);
850 if (err) {
851 dev_err(dev, "Parsing DT failed\n");
852 return err;
853 }
854
855 err = nwl_pcie_bridge_init(pcie);
856 if (err) {
857 dev_err(dev, "HW Initialization failed\n");
858 return err;
859 }
860
861 err = of_pci_get_host_bridge_resources(node, 0, 0xff, &res, &iobase);
862 if (err) {
863 dev_err(dev, "Getting bridge resources failed\n");
864 return err;
865 }
866
867 err = devm_request_pci_bus_resources(dev, &res);
868 if (err)
869 goto error;
870
871 err = nwl_pcie_init_irq_domain(pcie);
872 if (err) {
873 dev_err(dev, "Failed creating IRQ Domain\n");
874 goto error;
875 }
876
877 list_splice_init(&res, &bridge->windows);
878 bridge->dev.parent = dev;
879 bridge->sysdata = pcie;
880 bridge->busnr = pcie->root_busno;
881 bridge->ops = &nwl_pcie_ops;
882 bridge->map_irq = of_irq_parse_and_map_pci;
883 bridge->swizzle_irq = pci_common_swizzle;
884
885 if (IS_ENABLED(CONFIG_PCI_MSI)) {
886 err = nwl_pcie_enable_msi(pcie);
887 if (err < 0) {
888 dev_err(dev, "failed to enable MSI support: %d\n", err);
889 goto error;
890 }
891 }
892
893 err = pci_scan_root_bus_bridge(bridge);
894 if (err)
895 goto error;
896
897 bus = bridge->bus;
898
899 pci_assign_unassigned_bus_resources(bus);
900 list_for_each_entry(child, &bus->children, node)
901 pcie_bus_configure_settings(child);
902 pci_bus_add_devices(bus);
903 return 0;
904
905error:
906 pci_free_resource_list(&res);
907 return err;
908}
909
910static struct platform_driver nwl_pcie_driver = {
911 .driver = {
912 .name = "nwl-pcie",
913 .suppress_bind_attrs = true,
914 .of_match_table = nwl_pcie_of_match,
915 },
916 .probe = nwl_pcie_probe,
917};
918builtin_platform_driver(nwl_pcie_driver);