rjw | 1f88458 | 2022-01-06 17:20:42 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * PCI Express Precision Time Measurement |
| 3 | * Copyright (c) 2016, Intel Corporation. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms and conditions of the GNU General Public License, |
| 7 | * version 2, as published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | */ |
| 14 | |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/pci.h> |
| 18 | #include "../pci.h" |
| 19 | |
| 20 | static void pci_ptm_info(struct pci_dev *dev) |
| 21 | { |
| 22 | char clock_desc[8]; |
| 23 | |
| 24 | switch (dev->ptm_granularity) { |
| 25 | case 0: |
| 26 | snprintf(clock_desc, sizeof(clock_desc), "unknown"); |
| 27 | break; |
| 28 | case 255: |
| 29 | snprintf(clock_desc, sizeof(clock_desc), ">254ns"); |
| 30 | break; |
| 31 | default: |
| 32 | snprintf(clock_desc, sizeof(clock_desc), "%uns", |
| 33 | dev->ptm_granularity); |
| 34 | break; |
| 35 | } |
| 36 | dev_info(&dev->dev, "PTM enabled%s, %s granularity\n", |
| 37 | dev->ptm_root ? " (root)" : "", clock_desc); |
| 38 | } |
| 39 | |
| 40 | void pci_ptm_init(struct pci_dev *dev) |
| 41 | { |
| 42 | int pos; |
| 43 | u32 cap, ctrl; |
| 44 | u8 local_clock; |
| 45 | struct pci_dev *ups; |
| 46 | |
| 47 | if (!pci_is_pcie(dev)) |
| 48 | return; |
| 49 | |
| 50 | /* |
| 51 | * Enable PTM only on interior devices (root ports, switch ports, |
| 52 | * etc.) on the assumption that it causes no link traffic until an |
| 53 | * endpoint enables it. |
| 54 | */ |
| 55 | if ((pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT || |
| 56 | pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END)) |
| 57 | return; |
| 58 | |
| 59 | /* |
| 60 | * Switch Downstream Ports are not permitted to have a PTM |
| 61 | * capability; their PTM behavior is controlled by the Upstream |
| 62 | * Port (PCIe r5.0, sec 7.9.16). |
| 63 | */ |
| 64 | ups = pci_upstream_bridge(dev); |
| 65 | if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM && |
| 66 | ups && ups->ptm_enabled) { |
| 67 | dev->ptm_granularity = ups->ptm_granularity; |
| 68 | dev->ptm_enabled = 1; |
| 69 | return; |
| 70 | } |
| 71 | |
| 72 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM); |
| 73 | if (!pos) |
| 74 | return; |
| 75 | |
| 76 | pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap); |
| 77 | local_clock = (cap & PCI_PTM_GRANULARITY_MASK) >> 8; |
| 78 | |
| 79 | /* |
| 80 | * There's no point in enabling PTM unless it's enabled in the |
| 81 | * upstream device or this device can be a PTM Root itself. Per |
| 82 | * the spec recommendation (PCIe r3.1, sec 7.32.3), select the |
| 83 | * furthest upstream Time Source as the PTM Root. |
| 84 | */ |
| 85 | if (ups && ups->ptm_enabled) { |
| 86 | ctrl = PCI_PTM_CTRL_ENABLE; |
| 87 | if (ups->ptm_granularity == 0) |
| 88 | dev->ptm_granularity = 0; |
| 89 | else if (ups->ptm_granularity > local_clock) |
| 90 | dev->ptm_granularity = ups->ptm_granularity; |
| 91 | } else { |
| 92 | if (cap & PCI_PTM_CAP_ROOT) { |
| 93 | ctrl = PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT; |
| 94 | dev->ptm_root = 1; |
| 95 | dev->ptm_granularity = local_clock; |
| 96 | } else |
| 97 | return; |
| 98 | } |
| 99 | |
| 100 | ctrl |= dev->ptm_granularity << 8; |
| 101 | pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl); |
| 102 | dev->ptm_enabled = 1; |
| 103 | |
| 104 | pci_ptm_info(dev); |
| 105 | } |
| 106 | |
| 107 | int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) |
| 108 | { |
| 109 | int pos; |
| 110 | u32 cap, ctrl; |
| 111 | struct pci_dev *ups; |
| 112 | |
| 113 | if (!pci_is_pcie(dev)) |
| 114 | return -EINVAL; |
| 115 | |
| 116 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM); |
| 117 | if (!pos) |
| 118 | return -EINVAL; |
| 119 | |
| 120 | pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap); |
| 121 | if (!(cap & PCI_PTM_CAP_REQ)) |
| 122 | return -EINVAL; |
| 123 | |
| 124 | /* |
| 125 | * For a PCIe Endpoint, PTM is only useful if the endpoint can |
| 126 | * issue PTM requests to upstream devices that have PTM enabled. |
| 127 | * |
| 128 | * For Root Complex Integrated Endpoints, there is no upstream |
| 129 | * device, so there must be some implementation-specific way to |
| 130 | * associate the endpoint with a time source. |
| 131 | */ |
| 132 | if (pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT) { |
| 133 | ups = pci_upstream_bridge(dev); |
| 134 | if (!ups || !ups->ptm_enabled) |
| 135 | return -EINVAL; |
| 136 | |
| 137 | dev->ptm_granularity = ups->ptm_granularity; |
| 138 | } else if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) { |
| 139 | dev->ptm_granularity = 0; |
| 140 | } else |
| 141 | return -EINVAL; |
| 142 | |
| 143 | ctrl = PCI_PTM_CTRL_ENABLE; |
| 144 | ctrl |= dev->ptm_granularity << 8; |
| 145 | pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl); |
| 146 | dev->ptm_enabled = 1; |
| 147 | |
| 148 | pci_ptm_info(dev); |
| 149 | |
| 150 | if (granularity) |
| 151 | *granularity = dev->ptm_granularity; |
| 152 | return 0; |
| 153 | } |
| 154 | EXPORT_SYMBOL(pci_enable_ptm); |