blob: 890f296f58400298b2fa9115d1d242e9cbb1f0b4 [file] [log] [blame]
rjw1f884582022-01-06 17:20:42 +08001/*
2 * Pin controller and GPIO driver for Amlogic Meson SoCs
3 *
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * You should have received a copy of the GNU General Public License
11 * along with this program. If not, see <http://www.gnu.org/licenses/>.
12 */
13
14#include <linux/gpio.h>
15#include <linux/pinctrl/pinctrl.h>
16#include <linux/regmap.h>
17#include <linux/types.h>
18
19/**
20 * struct meson_pmx_group - a pinmux group
21 *
22 * @name: group name
23 * @pins: pins in the group
24 * @num_pins: number of pins in the group
25 * @is_gpio: whether the group is a single GPIO group
26 * @reg: register offset for the group in the domain mux registers
27 * @bit bit index enabling the group
28 * @domain: index of the domain this group belongs to
29 */
30struct meson_pmx_group {
31 const char *name;
32 const unsigned int *pins;
33 unsigned int num_pins;
34 bool is_gpio;
35 unsigned int reg;
36 unsigned int bit;
37};
38
39/**
40 * struct meson_pmx_func - a pinmux function
41 *
42 * @name: function name
43 * @groups: groups in the function
44 * @num_groups: number of groups in the function
45 */
46struct meson_pmx_func {
47 const char *name;
48 const char * const *groups;
49 unsigned int num_groups;
50};
51
52/**
53 * struct meson_reg_desc - a register descriptor
54 *
55 * @reg: register offset in the regmap
56 * @bit: bit index in register
57 *
58 * The structure describes the information needed to control pull,
59 * pull-enable, direction, etc. for a single pin
60 */
61struct meson_reg_desc {
62 unsigned int reg;
63 unsigned int bit;
64};
65
66/**
67 * enum meson_reg_type - type of registers encoded in @meson_reg_desc
68 */
69enum meson_reg_type {
70 REG_PULLEN,
71 REG_PULL,
72 REG_DIR,
73 REG_OUT,
74 REG_IN,
75 NUM_REG,
76};
77
78/**
79 * struct meson bank
80 *
81 * @name: bank name
82 * @first: first pin of the bank
83 * @last: last pin of the bank
84 * @irq: hwirq base number of the bank
85 * @regs: array of register descriptors
86 *
87 * A bank represents a set of pins controlled by a contiguous set of
88 * bits in the domain registers. The structure specifies which bits in
89 * the regmap control the different functionalities. Each member of
90 * the @regs array refers to the first pin of the bank.
91 */
92struct meson_bank {
93 const char *name;
94 unsigned int first;
95 unsigned int last;
96 int irq_first;
97 int irq_last;
98 struct meson_reg_desc regs[NUM_REG];
99};
100
101struct meson_pinctrl_data {
102 const char *name;
103 const struct pinctrl_pin_desc *pins;
104 struct meson_pmx_group *groups;
105 struct meson_pmx_func *funcs;
106 unsigned int pin_base;
107 unsigned int num_pins;
108 unsigned int num_groups;
109 unsigned int num_funcs;
110 struct meson_bank *banks;
111 unsigned int num_banks;
112};
113
114struct meson_pinctrl {
115 struct device *dev;
116 struct pinctrl_dev *pcdev;
117 struct pinctrl_desc desc;
118 struct meson_pinctrl_data *data;
119 struct regmap *reg_mux;
120 struct regmap *reg_pullen;
121 struct regmap *reg_pull;
122 struct regmap *reg_gpio;
123 struct gpio_chip chip;
124 struct device_node *of_node;
125};
126
127#define PIN(x, b) (b + x)
128
129#define GROUP(grp, r, b) \
130 { \
131 .name = #grp, \
132 .pins = grp ## _pins, \
133 .num_pins = ARRAY_SIZE(grp ## _pins), \
134 .reg = r, \
135 .bit = b, \
136 }
137
138#define GPIO_GROUP(gpio, b) \
139 { \
140 .name = #gpio, \
141 .pins = (const unsigned int[]){ PIN(gpio, b) }, \
142 .num_pins = 1, \
143 .is_gpio = true, \
144 }
145
146#define FUNCTION(fn) \
147 { \
148 .name = #fn, \
149 .groups = fn ## _groups, \
150 .num_groups = ARRAY_SIZE(fn ## _groups), \
151 }
152
153#define BANK(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
154 { \
155 .name = n, \
156 .first = f, \
157 .last = l, \
158 .irq_first = fi, \
159 .irq_last = li, \
160 .regs = { \
161 [REG_PULLEN] = { per, peb }, \
162 [REG_PULL] = { pr, pb }, \
163 [REG_DIR] = { dr, db }, \
164 [REG_OUT] = { or, ob }, \
165 [REG_IN] = { ir, ib }, \
166 }, \
167 }
168
169#define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x)
170
171extern struct meson_pinctrl_data meson8_cbus_pinctrl_data;
172extern struct meson_pinctrl_data meson8_aobus_pinctrl_data;
173extern struct meson_pinctrl_data meson8b_cbus_pinctrl_data;
174extern struct meson_pinctrl_data meson8b_aobus_pinctrl_data;
175extern struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data;
176extern struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data;
177extern struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data;
178extern struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data;